1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines wrappers for the Target class and related global
11 // functionality. This makes it easier to access the data and provides a single
12 // place that needs to check it for validity. All of these classes throw
13 // exceptions on error conditions.
15 //===----------------------------------------------------------------------===//
17 #ifndef CODEGEN_TARGET_H
18 #define CODEGEN_TARGET_H
20 #include "CodeGenRegisters.h"
21 #include "CodeGenInstruction.h"
30 struct CodeGenRegister;
33 // SelectionDAG node properties.
34 // SDNPMemOperand: indicates that a node touches memory and therefore must
35 // have an associated memory operand that describes the access.
51 // ComplexPattern attributes.
52 enum CPAttr { CPAttrParentAsRoot };
54 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
55 /// record corresponds to.
56 MVT::SimpleValueType getValueType(Record *Rec);
58 std::string getName(MVT::SimpleValueType T);
59 std::string getEnumName(MVT::SimpleValueType T);
61 /// getQualifiedName - Return the name of the specified record, with a
62 /// namespace qualifier if the record contains one.
63 std::string getQualifiedName(const Record *R);
65 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
70 mutable std::map<std::string, CodeGenInstruction> Instructions;
71 mutable std::vector<CodeGenRegister> Registers;
72 mutable std::vector<CodeGenRegisterClass> RegisterClasses;
73 mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
74 void ReadRegisters() const;
75 void ReadRegisterClasses() const;
76 void ReadInstructions() const;
77 void ReadLegalValueTypes() const;
81 Record *getTargetRecord() const { return TargetRec; }
82 const std::string &getName() const;
84 /// getInstNamespace - Return the target-specific instruction namespace.
86 std::string getInstNamespace() const;
88 /// getInstructionSet - Return the InstructionSet object.
90 Record *getInstructionSet() const;
92 /// getAsmWriter - Return the AssemblyWriter definition for this target.
94 Record *getAsmWriter() const;
96 const std::vector<CodeGenRegister> &getRegisters() const {
97 if (Registers.empty()) ReadRegisters();
101 const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
102 if (RegisterClasses.empty()) ReadRegisterClasses();
103 return RegisterClasses;
106 const CodeGenRegisterClass &getRegisterClass(Record *R) const {
107 const std::vector<CodeGenRegisterClass> &RC = getRegisterClasses();
108 for (unsigned i = 0, e = RC.size(); i != e; ++i)
109 if (RC[i].TheDef == R)
111 assert(0 && "Didn't find the register class");
115 /// getRegisterClassForRegister - Find the register class that contains the
116 /// specified physical register. If the register is not in a register
117 /// class, return null. If the register is in multiple classes, and the
118 /// classes have a superset-subset relationship and the same set of
119 /// types, return the superclass. Otherwise return null.
120 const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const {
121 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
122 const CodeGenRegisterClass *FoundRC = 0;
123 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
124 const CodeGenRegisterClass &RC = RegisterClasses[i];
125 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
126 if (R != RC.Elements[ei])
129 // If a register's classes have different types, return null.
130 if (FoundRC && RC.getValueTypes() != FoundRC->getValueTypes())
133 // If this is the first class that contains the register,
134 // make a note of it and go on to the next class.
140 std::vector<Record *> Elements(RC.Elements);
141 std::vector<Record *> FoundElements(FoundRC->Elements);
142 std::sort(Elements.begin(), Elements.end());
143 std::sort(FoundElements.begin(), FoundElements.end());
145 // Check to see if the previously found class that contains
146 // the register is a subclass of the current class. If so,
147 // prefer the superclass.
148 if (std::includes(Elements.begin(), Elements.end(),
149 FoundElements.begin(), FoundElements.end())) {
154 // Check to see if the previously found class that contains
155 // the register is a superclass of the current class. If so,
156 // prefer the superclass.
157 if (std::includes(FoundElements.begin(), FoundElements.end(),
158 Elements.begin(), Elements.end()))
161 // Multiple classes, and neither is a superclass of the other.
169 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
170 /// specified physical register.
171 std::vector<unsigned char> getRegisterVTs(Record *R) const;
173 const std::vector<MVT::SimpleValueType> &getLegalValueTypes() const {
174 if (LegalValueTypes.empty()) ReadLegalValueTypes();
175 return LegalValueTypes;
178 /// isLegalValueType - Return true if the specified value type is natively
179 /// supported by the target (i.e. there are registers that directly hold it).
180 bool isLegalValueType(MVT::SimpleValueType VT) const {
181 const std::vector<MVT::SimpleValueType> &LegalVTs = getLegalValueTypes();
182 for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
183 if (LegalVTs[i] == VT) return true;
187 /// getInstructions - Return all of the instructions defined for this target.
189 const std::map<std::string, CodeGenInstruction> &getInstructions() const {
190 if (Instructions.empty()) ReadInstructions();
193 std::map<std::string, CodeGenInstruction> &getInstructions() {
194 if (Instructions.empty()) ReadInstructions();
198 CodeGenInstruction &getInstruction(const std::string &Name) const {
199 const std::map<std::string, CodeGenInstruction> &Insts = getInstructions();
200 assert(Insts.count(Name) && "Not an instruction!");
201 return const_cast<CodeGenInstruction&>(Insts.find(Name)->second);
204 typedef std::map<std::string,
205 CodeGenInstruction>::const_iterator inst_iterator;
206 inst_iterator inst_begin() const { return getInstructions().begin(); }
207 inst_iterator inst_end() const { return Instructions.end(); }
209 /// getInstructionsByEnumValue - Return all of the instructions defined by the
210 /// target, ordered by their enum value.
211 void getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
212 &NumberedInstructions);
214 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
216 bool isLittleEndianEncoding() const;
218 /// supportsHasI1 - does this target understand HasI1 for ADDE and ADDC?
219 bool supportsHasI1() const;
222 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
223 /// tablegen class in TargetSelectionDAG.td
224 class ComplexPattern {
225 MVT::SimpleValueType Ty;
226 unsigned NumOperands;
227 std::string SelectFunc;
228 std::vector<Record*> RootNodes;
229 unsigned Properties; // Node properties
230 unsigned Attributes; // Pattern attributes
232 ComplexPattern() : NumOperands(0) {};
233 ComplexPattern(Record *R);
235 MVT::SimpleValueType getValueType() const { return Ty; }
236 unsigned getNumOperands() const { return NumOperands; }
237 const std::string &getSelectFunc() const { return SelectFunc; }
238 const std::vector<Record*> &getRootNodes() const {
241 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
242 bool hasAttribute(enum CPAttr Attr) const { return Attributes & (1 << Attr); }
245 } // End llvm namespace