1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines wrappers for the Target class and related global
11 // functionality. This makes it easier to access the data and provides a single
12 // place that needs to check it for validity. All of these classes throw
13 // exceptions on error conditions.
15 //===----------------------------------------------------------------------===//
17 #ifndef CODEGEN_TARGET_H
18 #define CODEGEN_TARGET_H
20 #include "llvm/Support/raw_ostream.h"
21 #include "CodeGenRegisters.h"
22 #include "CodeGenInstruction.h"
30 struct CodeGenRegister;
33 // SelectionDAG node properties.
34 // SDNPMemOperand: indicates that a node touches memory and therefore must
35 // have an associated memory operand that describes the access.
49 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
50 /// record corresponds to.
51 MVT::SimpleValueType getValueType(Record *Rec);
53 std::string getName(MVT::SimpleValueType T);
54 std::string getEnumName(MVT::SimpleValueType T);
56 /// getQualifiedName - Return the name of the specified record, with a
57 /// namespace qualifier if the record contains one.
58 std::string getQualifiedName(const Record *R);
60 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
65 mutable std::map<std::string, CodeGenInstruction> Instructions;
66 mutable std::vector<CodeGenRegister> Registers;
67 mutable std::vector<CodeGenRegisterClass> RegisterClasses;
68 mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
69 void ReadRegisters() const;
70 void ReadRegisterClasses() const;
71 void ReadInstructions() const;
72 void ReadLegalValueTypes() const;
74 mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
78 Record *getTargetRecord() const { return TargetRec; }
79 const std::string &getName() const;
81 /// getInstNamespace - Return the target-specific instruction namespace.
83 std::string getInstNamespace() const;
85 /// getInstructionSet - Return the InstructionSet object.
87 Record *getInstructionSet() const;
89 /// getAsmParser - Return the AssemblyParser definition for this target.
91 Record *getAsmParser() const;
93 /// getAsmWriter - Return the AssemblyWriter definition for this target.
95 Record *getAsmWriter() const;
97 const std::vector<CodeGenRegister> &getRegisters() const {
98 if (Registers.empty()) ReadRegisters();
102 const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
103 if (RegisterClasses.empty()) ReadRegisterClasses();
104 return RegisterClasses;
107 const CodeGenRegisterClass &getRegisterClass(Record *R) const {
108 const std::vector<CodeGenRegisterClass> &RC = getRegisterClasses();
109 for (unsigned i = 0, e = RC.size(); i != e; ++i)
110 if (RC[i].TheDef == R)
112 assert(0 && "Didn't find the register class");
116 /// getRegisterClassForRegister - Find the register class that contains the
117 /// specified physical register. If the register is not in a register
118 /// class, return null. If the register is in multiple classes, and the
119 /// classes have a superset-subset relationship and the same set of
120 /// types, return the superclass. Otherwise return null.
121 const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const {
122 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
123 const CodeGenRegisterClass *FoundRC = 0;
124 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
125 const CodeGenRegisterClass &RC = RegisterClasses[i];
126 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
127 if (R != RC.Elements[ei])
130 // If a register's classes have different types, return null.
131 if (FoundRC && RC.getValueTypes() != FoundRC->getValueTypes())
134 // If this is the first class that contains the register,
135 // make a note of it and go on to the next class.
141 std::vector<Record *> Elements(RC.Elements);
142 std::vector<Record *> FoundElements(FoundRC->Elements);
143 std::sort(Elements.begin(), Elements.end());
144 std::sort(FoundElements.begin(), FoundElements.end());
146 // Check to see if the previously found class that contains
147 // the register is a subclass of the current class. If so,
148 // prefer the superclass.
149 if (std::includes(Elements.begin(), Elements.end(),
150 FoundElements.begin(), FoundElements.end())) {
155 // Check to see if the previously found class that contains
156 // the register is a superclass of the current class. If so,
157 // prefer the superclass.
158 if (std::includes(FoundElements.begin(), FoundElements.end(),
159 Elements.begin(), Elements.end()))
162 // Multiple classes, and neither is a superclass of the other.
170 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
171 /// specified physical register.
172 std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const;
174 const std::vector<MVT::SimpleValueType> &getLegalValueTypes() const {
175 if (LegalValueTypes.empty()) ReadLegalValueTypes();
176 return LegalValueTypes;
179 /// isLegalValueType - Return true if the specified value type is natively
180 /// supported by the target (i.e. there are registers that directly hold it).
181 bool isLegalValueType(MVT::SimpleValueType VT) const {
182 const std::vector<MVT::SimpleValueType> &LegalVTs = getLegalValueTypes();
183 for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
184 if (LegalVTs[i] == VT) return true;
188 /// getInstructions - Return all of the instructions defined for this target.
191 const std::map<std::string, CodeGenInstruction> &getInstructions() const {
192 if (Instructions.empty()) ReadInstructions();
195 std::map<std::string, CodeGenInstruction> &getInstructions() {
196 if (Instructions.empty()) ReadInstructions();
199 CodeGenInstruction &getInstruction(const std::string &Name) const {
200 const std::map<std::string, CodeGenInstruction> &Insts = getInstructions();
201 assert(Insts.count(Name) && "Not an instruction!");
202 return const_cast<CodeGenInstruction&>(Insts.find(Name)->second);
206 CodeGenInstruction &getInstruction(const Record *InstRec) const;
208 /// getInstructionsByEnumValue - Return all of the instructions defined by the
209 /// target, ordered by their enum value.
210 const std::vector<const CodeGenInstruction*> &
211 getInstructionsByEnumValue() const {
212 if (InstrsByEnum.empty()) ComputeInstrsByEnum();
216 typedef std::vector<const CodeGenInstruction*>::const_iterator inst_iterator;
217 inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
218 inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
221 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
223 bool isLittleEndianEncoding() const;
226 void ComputeInstrsByEnum() const;
229 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
230 /// tablegen class in TargetSelectionDAG.td
231 class ComplexPattern {
232 MVT::SimpleValueType Ty;
233 unsigned NumOperands;
234 std::string SelectFunc;
235 std::vector<Record*> RootNodes;
236 unsigned Properties; // Node properties
238 ComplexPattern() : NumOperands(0) {}
239 ComplexPattern(Record *R);
241 MVT::SimpleValueType getValueType() const { return Ty; }
242 unsigned getNumOperands() const { return NumOperands; }
243 const std::string &getSelectFunc() const { return SelectFunc; }
244 const std::vector<Record*> &getRootNodes() const {
247 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
250 } // End llvm namespace