1 //===- DAGISelMatcherGen.cpp - Matcher generator --------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "DAGISelMatcher.h"
11 #include "CodeGenDAGPatterns.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/ADT/StringMap.h"
19 /// getRegisterValueType - Look up and return the ValueType of the specified
20 /// register. If the register is a member of multiple register classes which
21 /// have different associated types, return MVT::Other.
22 static MVT::SimpleValueType getRegisterValueType(Record *R,
23 const CodeGenTarget &T) {
25 MVT::SimpleValueType VT = MVT::Other;
26 const std::vector<CodeGenRegisterClass> &RCs = T.getRegisterClasses();
27 std::vector<Record*>::const_iterator Element;
29 for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) {
30 const CodeGenRegisterClass &RC = RCs[rc];
31 if (!std::count(RC.Elements.begin(), RC.Elements.end(), R))
36 VT = RC.getValueTypeNum(0);
40 // If this occurs in multiple register classes, they all have to agree.
41 assert(VT == RC.getValueTypeNum(0));
49 const PatternToMatch &Pattern;
50 const CodeGenDAGPatterns &CGP;
52 /// PatWithNoTypes - This is a clone of Pattern.getSrcPattern() that starts
53 /// out with all of the types removed. This allows us to insert type checks
54 /// as we scan the tree.
55 TreePatternNode *PatWithNoTypes;
57 /// VariableMap - A map from variable names ('$dst') to the recorded operand
58 /// number that they were captured as. These are biased by 1 to make
60 StringMap<unsigned> VariableMap;
62 /// NextRecordedOperandNo - As we emit opcodes to record matched values in
63 /// the RecordedNodes array, this keeps track of which slot will be next to
65 unsigned NextRecordedOperandNo;
67 /// MatchedChainNodes - This maintains the position in the recorded nodes
68 /// array of all of the recorded input nodes that have chains.
69 SmallVector<unsigned, 2> MatchedChainNodes;
71 /// MatchedFlagResultNodes - This maintains the position in the recorded
72 /// nodes array of all of the recorded input nodes that have flag results.
73 SmallVector<unsigned, 2> MatchedFlagResultNodes;
75 /// PhysRegInputs - List list has an entry for each explicitly specified
76 /// physreg input to the pattern. The first elt is the Register node, the
77 /// second is the recorded slot number the input pattern match saved it in.
78 SmallVector<std::pair<Record*, unsigned>, 2> PhysRegInputs;
80 /// Matcher - This is the top level of the generated matcher, the result.
83 /// CurPredicate - As we emit matcher nodes, this points to the latest check
84 /// which should have future checks stuck into its Next position.
85 Matcher *CurPredicate;
87 MatcherGen(const PatternToMatch &pattern, const CodeGenDAGPatterns &cgp);
90 delete PatWithNoTypes;
93 bool EmitMatcherCode(unsigned Variant);
94 void EmitResultCode();
96 Matcher *GetMatcher() const { return TheMatcher; }
97 Matcher *GetCurPredicate() const { return CurPredicate; }
99 void AddMatcher(Matcher *NewNode);
100 void InferPossibleTypes();
102 // Matcher Generation.
103 void EmitMatchCode(const TreePatternNode *N, TreePatternNode *NodeNoTypes);
104 void EmitLeafMatchCode(const TreePatternNode *N);
105 void EmitOperatorMatchCode(const TreePatternNode *N,
106 TreePatternNode *NodeNoTypes);
108 // Result Code Generation.
109 unsigned getNamedArgumentSlot(StringRef Name) {
110 unsigned VarMapEntry = VariableMap[Name];
111 assert(VarMapEntry != 0 &&
112 "Variable referenced but not defined and not caught earlier!");
113 return VarMapEntry-1;
116 /// GetInstPatternNode - Get the pattern for an instruction.
117 const TreePatternNode *GetInstPatternNode(const DAGInstruction &Ins,
118 const TreePatternNode *N);
120 void EmitResultOperand(const TreePatternNode *N,
121 SmallVectorImpl<unsigned> &ResultOps);
122 void EmitResultOfNamedOperand(const TreePatternNode *N,
123 SmallVectorImpl<unsigned> &ResultOps);
124 void EmitResultLeafAsOperand(const TreePatternNode *N,
125 SmallVectorImpl<unsigned> &ResultOps);
126 void EmitResultInstructionAsOperand(const TreePatternNode *N,
127 SmallVectorImpl<unsigned> &ResultOps);
128 void EmitResultSDNodeXFormAsOperand(const TreePatternNode *N,
129 SmallVectorImpl<unsigned> &ResultOps);
132 } // end anon namespace.
134 MatcherGen::MatcherGen(const PatternToMatch &pattern,
135 const CodeGenDAGPatterns &cgp)
136 : Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0),
137 TheMatcher(0), CurPredicate(0) {
138 // We need to produce the matcher tree for the patterns source pattern. To do
139 // this we need to match the structure as well as the types. To do the type
140 // matching, we want to figure out the fewest number of type checks we need to
141 // emit. For example, if there is only one integer type supported by a
142 // target, there should be no type comparisons at all for integer patterns!
144 // To figure out the fewest number of type checks needed, clone the pattern,
145 // remove the types, then perform type inference on the pattern as a whole.
146 // If there are unresolved types, emit an explicit check for those types,
147 // apply the type to the tree, then rerun type inference. Iterate until all
148 // types are resolved.
150 PatWithNoTypes = Pattern.getSrcPattern()->clone();
151 PatWithNoTypes->RemoveAllTypes();
153 // If there are types that are manifestly known, infer them.
154 InferPossibleTypes();
157 /// InferPossibleTypes - As we emit the pattern, we end up generating type
158 /// checks and applying them to the 'PatWithNoTypes' tree. As we do this, we
159 /// want to propagate implied types as far throughout the tree as possible so
160 /// that we avoid doing redundant type checks. This does the type propagation.
161 void MatcherGen::InferPossibleTypes() {
162 // TP - Get *SOME* tree pattern, we don't care which. It is only used for
163 // diagnostics, which we know are impossible at this point.
164 TreePattern &TP = *CGP.pf_begin()->second;
167 bool MadeChange = true;
169 MadeChange = PatWithNoTypes->ApplyTypeConstraints(TP,
170 true/*Ignore reg constraints*/);
172 errs() << "Type constraint application shouldn't fail!";
178 /// AddMatcher - Add a matcher node to the current graph we're building.
179 void MatcherGen::AddMatcher(Matcher *NewNode) {
180 if (CurPredicate != 0)
181 CurPredicate->setNext(NewNode);
183 TheMatcher = NewNode;
184 CurPredicate = NewNode;
188 //===----------------------------------------------------------------------===//
189 // Pattern Match Generation
190 //===----------------------------------------------------------------------===//
192 /// EmitLeafMatchCode - Generate matching code for leaf nodes.
193 void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) {
194 assert(N->isLeaf() && "Not a leaf?");
196 // If there are node predicates for this node, generate their checks.
197 for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i)
198 AddMatcher(new CheckPredicateMatcher(N->getPredicateFns()[i]));
200 // Direct match against an integer constant.
201 if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
202 // If this is the root of the dag we're matching, we emit a redundant opcode
203 // check to ensure that this gets folded into the normal top-level
205 if (N == Pattern.getSrcPattern()) {
206 const SDNodeInfo &NI = CGP.getSDNodeInfo(CGP.getSDNodeNamed("imm"));
207 AddMatcher(new CheckOpcodeMatcher(NI));
210 return AddMatcher(new CheckIntegerMatcher(II->getValue()));
213 DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue());
215 errs() << "Unknown leaf kind: " << *DI << "\n";
219 Record *LeafRec = DI->getDef();
220 if (// Handle register references. Nothing to do here, they always match.
221 LeafRec->isSubClassOf("RegisterClass") ||
222 LeafRec->isSubClassOf("PointerLikeRegClass") ||
223 // Place holder for SRCVALUE nodes. Nothing to do here.
224 LeafRec->getName() == "srcvalue")
227 // If we have a physreg reference like (mul gpr:$src, EAX) then we need to
228 // record the register
229 if (LeafRec->isSubClassOf("Register")) {
230 AddMatcher(new RecordMatcher("physreg input "+LeafRec->getName(),
231 NextRecordedOperandNo));
232 PhysRegInputs.push_back(std::make_pair(LeafRec, NextRecordedOperandNo++));
236 if (LeafRec->isSubClassOf("ValueType"))
237 return AddMatcher(new CheckValueTypeMatcher(LeafRec->getName()));
239 if (LeafRec->isSubClassOf("CondCode"))
240 return AddMatcher(new CheckCondCodeMatcher(LeafRec->getName()));
242 if (LeafRec->isSubClassOf("ComplexPattern")) {
243 // We can't model ComplexPattern uses that don't have their name taken yet.
244 // The OPC_CheckComplexPattern operation implicitly records the results.
245 if (N->getName().empty()) {
246 errs() << "We expect complex pattern uses to have names: " << *N << "\n";
250 // Handle complex pattern.
251 const ComplexPattern &CP = CGP.getComplexPattern(LeafRec);
253 // Emit a CheckComplexPat operation, which does the match (aborting if it
254 // fails) and pushes the matched operands onto the recorded nodes list.
255 AddMatcher(new CheckComplexPatMatcher(CP, NextRecordedOperandNo));
257 // Record the right number of operands.
258 NextRecordedOperandNo += CP.getNumOperands();
259 if (CP.hasProperty(SDNPHasChain))
260 ++NextRecordedOperandNo; // Chained node operand.
262 // If the complex pattern has a chain, then we need to keep track of the
263 // fact that we just recorded a chain input. The chain input will be
264 // matched as the last operand of the predicate if it was successful.
265 if (CP.hasProperty(SDNPHasChain)) {
266 // It is the last operand recorded.
267 assert(NextRecordedOperandNo > 1 &&
268 "Should have recorded input/result chains at least!");
269 MatchedChainNodes.push_back(NextRecordedOperandNo-1);
272 // TODO: Complex patterns can't have output flags, if they did, we'd want
277 errs() << "Unknown leaf kind: " << *N << "\n";
281 void MatcherGen::EmitOperatorMatchCode(const TreePatternNode *N,
282 TreePatternNode *NodeNoTypes) {
283 assert(!N->isLeaf() && "Not an operator?");
284 const SDNodeInfo &CInfo = CGP.getSDNodeInfo(N->getOperator());
286 // If this is an 'and R, 1234' where the operation is AND/OR and the RHS is
287 // a constant without a predicate fn that has more that one bit set, handle
288 // this as a special case. This is usually for targets that have special
289 // handling of certain large constants (e.g. alpha with it's 8/16/32-bit
290 // handling stuff). Using these instructions is often far more efficient
291 // than materializing the constant. Unfortunately, both the instcombiner
292 // and the dag combiner can often infer that bits are dead, and thus drop
293 // them from the mask in the dag. For example, it might turn 'AND X, 255'
294 // into 'AND X, 254' if it knows the low bit is set. Emit code that checks
296 if ((N->getOperator()->getName() == "and" ||
297 N->getOperator()->getName() == "or") &&
298 N->getChild(1)->isLeaf() && N->getChild(1)->getPredicateFns().empty() &&
299 N->getPredicateFns().empty()) {
300 if (IntInit *II = dynamic_cast<IntInit*>(N->getChild(1)->getLeafValue())) {
301 if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits.
302 // If this is at the root of the pattern, we emit a redundant
303 // CheckOpcode so that the following checks get factored properly under
304 // a single opcode check.
305 if (N == Pattern.getSrcPattern())
306 AddMatcher(new CheckOpcodeMatcher(CInfo));
308 // Emit the CheckAndImm/CheckOrImm node.
309 if (N->getOperator()->getName() == "and")
310 AddMatcher(new CheckAndImmMatcher(II->getValue()));
312 AddMatcher(new CheckOrImmMatcher(II->getValue()));
314 // Match the LHS of the AND as appropriate.
315 AddMatcher(new MoveChildMatcher(0));
316 EmitMatchCode(N->getChild(0), NodeNoTypes->getChild(0));
317 AddMatcher(new MoveParentMatcher());
323 // Check that the current opcode lines up.
324 AddMatcher(new CheckOpcodeMatcher(CInfo));
326 // If there are node predicates for this node, generate their checks.
327 for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i)
328 AddMatcher(new CheckPredicateMatcher(N->getPredicateFns()[i]));
331 // If this node has memory references (i.e. is a load or store), tell the
332 // interpreter to capture them in the memref array.
333 if (N->NodeHasProperty(SDNPMemOperand, CGP))
334 AddMatcher(new RecordMemRefMatcher());
336 // If this node has a chain, then the chain is operand #0 is the SDNode, and
337 // the child numbers of the node are all offset by one.
339 if (N->NodeHasProperty(SDNPHasChain, CGP)) {
340 // Record the node and remember it in our chained nodes list.
341 AddMatcher(new RecordMatcher("'" + N->getOperator()->getName() +
343 NextRecordedOperandNo));
344 // Remember all of the input chains our pattern will match.
345 MatchedChainNodes.push_back(NextRecordedOperandNo++);
347 // Don't look at the input chain when matching the tree pattern to the
351 // If this node is not the root and the subtree underneath it produces a
352 // chain, then the result of matching the node is also produce a chain.
353 // Beyond that, this means that we're also folding (at least) the root node
354 // into the node that produce the chain (for example, matching
355 // "(add reg, (load ptr))" as a add_with_memory on X86). This is
356 // problematic, if the 'reg' node also uses the load (say, its chain).
361 // | \ DAG's like cheese.
367 // It would be invalid to fold XX and LD. In this case, folding the two
368 // nodes together would induce a cycle in the DAG, making it a 'cyclic DAG'
369 // To prevent this, we emit a dynamic check for legality before allowing
370 // this to be folded.
372 const TreePatternNode *Root = Pattern.getSrcPattern();
373 if (N != Root) { // Not the root of the pattern.
374 // If there is a node between the root and this node, then we definitely
375 // need to emit the check.
376 bool NeedCheck = !Root->hasChild(N);
378 // If it *is* an immediate child of the root, we can still need a check if
379 // the root SDNode has multiple inputs. For us, this means that it is an
380 // intrinsic, has multiple operands, or has other inputs like chain or
383 const SDNodeInfo &PInfo = CGP.getSDNodeInfo(Root->getOperator());
385 Root->getOperator() == CGP.get_intrinsic_void_sdnode() ||
386 Root->getOperator() == CGP.get_intrinsic_w_chain_sdnode() ||
387 Root->getOperator() == CGP.get_intrinsic_wo_chain_sdnode() ||
388 PInfo.getNumOperands() > 1 ||
389 PInfo.hasProperty(SDNPHasChain) ||
390 PInfo.hasProperty(SDNPInFlag) ||
391 PInfo.hasProperty(SDNPOptInFlag);
395 AddMatcher(new CheckFoldableChainNodeMatcher());
399 // If this node has an output flag and isn't the root, remember it.
400 if (N->NodeHasProperty(SDNPOutFlag, CGP) &&
401 N != Pattern.getSrcPattern()) {
402 // TODO: This redundantly records nodes with both flags and chains.
404 // Record the node and remember it in our chained nodes list.
405 AddMatcher(new RecordMatcher("'" + N->getOperator()->getName() +
406 "' flag output node",
407 NextRecordedOperandNo));
408 // Remember all of the nodes with output flags our pattern will match.
409 MatchedFlagResultNodes.push_back(NextRecordedOperandNo++);
412 // If this node is known to have an input flag or if it *might* have an input
413 // flag, capture it as the flag input of the pattern.
414 if (N->NodeHasProperty(SDNPOptInFlag, CGP) ||
415 N->NodeHasProperty(SDNPInFlag, CGP))
416 AddMatcher(new CaptureFlagInputMatcher());
418 for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
419 // Get the code suitable for matching this child. Move to the child, check
420 // it then move back to the parent.
421 AddMatcher(new MoveChildMatcher(OpNo));
422 EmitMatchCode(N->getChild(i), NodeNoTypes->getChild(i));
423 AddMatcher(new MoveParentMatcher());
428 void MatcherGen::EmitMatchCode(const TreePatternNode *N,
429 TreePatternNode *NodeNoTypes) {
430 // If N and NodeNoTypes don't agree on a type, then this is a case where we
431 // need to do a type check. Emit the check, apply the tyep to NodeNoTypes and
432 // reinfer any correlated types.
433 unsigned NodeType = EEVT::isUnknown;
434 if (NodeNoTypes->getExtTypes() != N->getExtTypes()) {
435 NodeType = N->getTypeNum(0);
436 NodeNoTypes->setTypes(N->getExtTypes());
437 InferPossibleTypes();
440 // If this node has a name associated with it, capture it in VariableMap. If
441 // we already saw this in the pattern, emit code to verify dagness.
442 if (!N->getName().empty()) {
443 unsigned &VarMapEntry = VariableMap[N->getName()];
444 if (VarMapEntry == 0) {
445 // If it is a named node, we must emit a 'Record' opcode.
446 AddMatcher(new RecordMatcher("$" + N->getName(), NextRecordedOperandNo));
447 VarMapEntry = ++NextRecordedOperandNo;
449 // If we get here, this is a second reference to a specific name. Since
450 // we already have checked that the first reference is valid, we don't
451 // have to recursively match it, just check that it's the same as the
452 // previously named thing.
453 AddMatcher(new CheckSameMatcher(VarMapEntry-1));
459 EmitLeafMatchCode(N);
461 EmitOperatorMatchCode(N, NodeNoTypes);
463 if (NodeType != EEVT::isUnknown)
464 AddMatcher(new CheckTypeMatcher((MVT::SimpleValueType)NodeType));
468 /// EmitMatcherCode - Generate the code that matches the predicate of this
469 /// pattern for the specified Variant. If the variant is invalid this returns
470 /// true and does not generate code, if it is valid, it returns false.
471 bool MatcherGen::EmitMatcherCode(unsigned Variant) {
472 // If the root of the pattern is a ComplexPattern and if it is specified to
473 // match some number of root opcodes, these are considered to be our variants.
474 // Depending on which variant we're generating code for, emit the root opcode
476 if (const ComplexPattern *CP =
477 Pattern.getSrcPattern()->getComplexPatternInfo(CGP)) {
478 const std::vector<Record*> &OpNodes = CP->getRootNodes();
479 assert(!OpNodes.empty() &&"Complex Pattern must specify what it can match");
480 if (Variant >= OpNodes.size()) return true;
482 AddMatcher(new CheckOpcodeMatcher(CGP.getSDNodeInfo(OpNodes[Variant])));
484 if (Variant != 0) return true;
487 // If the pattern has a predicate on it (e.g. only enabled when a subtarget
488 // feature is around, do the check).
489 // FIXME: This should get emitted after the match code below to encourage
490 // sharing. This can't happen until we get an X86ISD::AddrMode node made by
491 // dag combine, eliminating the horrible side-effect-full stuff from
492 // X86's MatchAddress.
493 if (!Pattern.getPredicateCheck().empty())
494 AddMatcher(new CheckPatternPredicateMatcher(Pattern.getPredicateCheck()));
496 // Emit the matcher for the pattern structure and types.
497 EmitMatchCode(Pattern.getSrcPattern(), PatWithNoTypes);
502 //===----------------------------------------------------------------------===//
503 // Node Result Generation
504 //===----------------------------------------------------------------------===//
506 void MatcherGen::EmitResultOfNamedOperand(const TreePatternNode *N,
507 SmallVectorImpl<unsigned> &ResultOps){
508 assert(!N->getName().empty() && "Operand not named!");
510 unsigned SlotNo = getNamedArgumentSlot(N->getName());
512 // A reference to a complex pattern gets all of the results of the complex
514 if (const ComplexPattern *CP = N->getComplexPatternInfo(CGP)) {
515 // The first slot entry is the node itself, the subsequent entries are the
517 for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i)
518 ResultOps.push_back(SlotNo+i+1);
522 // If this is an 'imm' or 'fpimm' node, make sure to convert it to the target
523 // version of the immediate so that it doesn't get selected due to some other
526 StringRef OperatorName = N->getOperator()->getName();
527 if (OperatorName == "imm" || OperatorName == "fpimm") {
528 AddMatcher(new EmitConvertToTargetMatcher(SlotNo));
529 ResultOps.push_back(NextRecordedOperandNo++);
534 ResultOps.push_back(SlotNo);
537 void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N,
538 SmallVectorImpl<unsigned> &ResultOps) {
539 assert(N->isLeaf() && "Must be a leaf");
541 if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
542 AddMatcher(new EmitIntegerMatcher(II->getValue(),N->getTypeNum(0)));
543 ResultOps.push_back(NextRecordedOperandNo++);
547 // If this is an explicit register reference, handle it.
548 if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
549 if (DI->getDef()->isSubClassOf("Register")) {
550 AddMatcher(new EmitRegisterMatcher(DI->getDef(),
552 ResultOps.push_back(NextRecordedOperandNo++);
556 if (DI->getDef()->getName() == "zero_reg") {
557 AddMatcher(new EmitRegisterMatcher(0, N->getTypeNum(0)));
558 ResultOps.push_back(NextRecordedOperandNo++);
562 // Handle a reference to a register class. This is used
563 // in COPY_TO_SUBREG instructions.
564 if (DI->getDef()->isSubClassOf("RegisterClass")) {
565 std::string Value = getQualifiedName(DI->getDef()) + "RegClassID";
566 AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
567 ResultOps.push_back(NextRecordedOperandNo++);
572 errs() << "unhandled leaf node: \n";
576 /// GetInstPatternNode - Get the pattern for an instruction.
578 const TreePatternNode *MatcherGen::
579 GetInstPatternNode(const DAGInstruction &Inst, const TreePatternNode *N) {
580 const TreePattern *InstPat = Inst.getPattern();
582 // FIXME2?: Assume actual pattern comes before "implicit".
583 TreePatternNode *InstPatNode;
585 InstPatNode = InstPat->getTree(0);
586 else if (/*isRoot*/ N == Pattern.getDstPattern())
587 InstPatNode = Pattern.getSrcPattern();
591 if (InstPatNode && !InstPatNode->isLeaf() &&
592 InstPatNode->getOperator()->getName() == "set")
593 InstPatNode = InstPatNode->getChild(InstPatNode->getNumChildren()-1);
599 EmitResultInstructionAsOperand(const TreePatternNode *N,
600 SmallVectorImpl<unsigned> &OutputOps) {
601 Record *Op = N->getOperator();
602 const CodeGenTarget &CGT = CGP.getTargetInfo();
603 CodeGenInstruction &II = CGT.getInstruction(Op->getName());
604 const DAGInstruction &Inst = CGP.getInstruction(Op);
606 // If we can, get the pattern for the instruction we're generating. We derive
607 // a variety of information from this pattern, such as whether it has a chain.
609 // FIXME2: This is extremely dubious for several reasons, not the least of
610 // which it gives special status to instructions with patterns that Pat<>
611 // nodes can't duplicate.
612 const TreePatternNode *InstPatNode = GetInstPatternNode(Inst, N);
614 // NodeHasChain - Whether the instruction node we're creating takes chains.
615 bool NodeHasChain = InstPatNode &&
616 InstPatNode->TreeHasProperty(SDNPHasChain, CGP);
618 bool isRoot = N == Pattern.getDstPattern();
620 // TreeHasOutFlag - True if this tree has a flag.
621 bool TreeHasInFlag = false, TreeHasOutFlag = false;
623 const TreePatternNode *SrcPat = Pattern.getSrcPattern();
624 TreeHasInFlag = SrcPat->TreeHasProperty(SDNPOptInFlag, CGP) ||
625 SrcPat->TreeHasProperty(SDNPInFlag, CGP);
627 // FIXME2: this is checking the entire pattern, not just the node in
628 // question, doing this just for the root seems like a total hack.
629 TreeHasOutFlag = SrcPat->TreeHasProperty(SDNPOutFlag, CGP);
632 // NumResults - This is the number of results produced by the instruction in
634 unsigned NumResults = Inst.getNumResults();
636 // Loop over all of the operands of the instruction pattern, emitting code
637 // to fill them all in. The node 'N' usually has number children equal to
638 // the number of input operands of the instruction. However, in cases
639 // where there are predicate operands for an instruction, we need to fill
640 // in the 'execute always' values. Match up the node operands to the
641 // instruction operands to do this.
642 SmallVector<unsigned, 8> InstOps;
643 for (unsigned ChildNo = 0, InstOpNo = NumResults, e = II.OperandList.size();
644 InstOpNo != e; ++InstOpNo) {
646 // Determine what to emit for this operand.
647 Record *OperandNode = II.OperandList[InstOpNo].Rec;
648 if ((OperandNode->isSubClassOf("PredicateOperand") ||
649 OperandNode->isSubClassOf("OptionalDefOperand")) &&
650 !CGP.getDefaultOperand(OperandNode).DefaultOps.empty()) {
651 // This is a predicate or optional def operand; emit the
652 // 'default ops' operands.
653 const DAGDefaultOperand &DefaultOp =
654 CGP.getDefaultOperand(II.OperandList[InstOpNo].Rec);
655 for (unsigned i = 0, e = DefaultOp.DefaultOps.size(); i != e; ++i)
656 EmitResultOperand(DefaultOp.DefaultOps[i], InstOps);
660 // Otherwise this is a normal operand or a predicate operand without
661 // 'execute always'; emit it.
662 EmitResultOperand(N->getChild(ChildNo), InstOps);
666 // If this node has an input flag or explicitly specified input physregs, we
667 // need to add chained and flagged copyfromreg nodes and materialize the flag
669 if (isRoot && !PhysRegInputs.empty()) {
670 // Emit all of the CopyToReg nodes for the input physical registers. These
671 // occur in patterns like (mul:i8 AL:i8, GR8:i8:$src).
672 for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i)
673 AddMatcher(new EmitCopyToRegMatcher(PhysRegInputs[i].second,
674 PhysRegInputs[i].first));
675 // Even if the node has no other flag inputs, the resultant node must be
676 // flagged to the CopyFromReg nodes we just generated.
677 TreeHasInFlag = true;
680 // Result order: node results, chain, flags
682 // Determine the result types.
683 SmallVector<MVT::SimpleValueType, 4> ResultVTs;
684 if (NumResults != 0 && N->getTypeNum(0) != MVT::isVoid) {
685 // FIXME2: If the node has multiple results, we should add them. For now,
686 // preserve existing behavior?!
687 ResultVTs.push_back(N->getTypeNum(0));
691 // If this is the root instruction of a pattern that has physical registers in
692 // its result pattern, add output VTs for them. For example, X86 has:
693 // (set AL, (mul ...))
694 // This also handles implicit results like:
696 if (isRoot && Pattern.getDstRegs().size() != 0) {
697 for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i)
698 if (Pattern.getDstRegs()[i]->isSubClassOf("Register"))
699 ResultVTs.push_back(getRegisterValueType(Pattern.getDstRegs()[i], CGT));
702 // FIXME2: Instead of using the isVariadic flag on the instruction, we should
703 // have an SDNP that indicates variadicism. The TargetInstrInfo isVariadic
704 // property should be inferred from this when an instruction has a pattern.
705 int NumFixedArityOperands = -1;
706 if (isRoot && II.isVariadic)
707 NumFixedArityOperands = Pattern.getSrcPattern()->getNumChildren();
709 // If this is the root node and any of the nodes matched nodes in the input
710 // pattern have MemRefs in them, have the interpreter collect them and plop
711 // them onto this node.
713 // FIXME3: This is actively incorrect for result patterns where the root of
714 // the pattern is not the memory reference and is also incorrect when the
715 // result pattern has multiple memory-referencing instructions. For example,
716 // in the X86 backend, this pattern causes the memrefs to get attached to the
717 // CVTSS2SDrr instead of the MOVSSrm:
719 // def : Pat<(extloadf32 addr:$src),
720 // (CVTSS2SDrr (MOVSSrm addr:$src))>;
722 bool NodeHasMemRefs =
723 isRoot && Pattern.getSrcPattern()->TreeHasProperty(SDNPMemOperand, CGP);
725 AddMatcher(new EmitNodeMatcher(II.Namespace+"::"+II.TheDef->getName(),
726 ResultVTs.data(), ResultVTs.size(),
727 InstOps.data(), InstOps.size(),
728 NodeHasChain, TreeHasInFlag, TreeHasOutFlag,
729 NodeHasMemRefs, NumFixedArityOperands,
730 NextRecordedOperandNo));
732 // The non-chain and non-flag results of the newly emitted node get recorded.
733 for (unsigned i = 0, e = ResultVTs.size(); i != e; ++i) {
734 if (ResultVTs[i] == MVT::Other || ResultVTs[i] == MVT::Flag) break;
735 OutputOps.push_back(NextRecordedOperandNo++);
740 EmitResultSDNodeXFormAsOperand(const TreePatternNode *N,
741 SmallVectorImpl<unsigned> &ResultOps) {
742 assert(N->getOperator()->isSubClassOf("SDNodeXForm") && "Not SDNodeXForm?");
745 SmallVector<unsigned, 8> InputOps;
747 // FIXME2: Could easily generalize this to support multiple inputs and outputs
748 // to the SDNodeXForm. For now we just support one input and one output like
749 // the old instruction selector.
750 assert(N->getNumChildren() == 1);
751 EmitResultOperand(N->getChild(0), InputOps);
753 // The input currently must have produced exactly one result.
754 assert(InputOps.size() == 1 && "Unexpected input to SDNodeXForm");
756 AddMatcher(new EmitNodeXFormMatcher(InputOps[0], N->getOperator()));
757 ResultOps.push_back(NextRecordedOperandNo++);
760 void MatcherGen::EmitResultOperand(const TreePatternNode *N,
761 SmallVectorImpl<unsigned> &ResultOps) {
762 // This is something selected from the pattern we matched.
763 if (!N->getName().empty())
764 return EmitResultOfNamedOperand(N, ResultOps);
767 return EmitResultLeafAsOperand(N, ResultOps);
769 Record *OpRec = N->getOperator();
770 if (OpRec->isSubClassOf("Instruction"))
771 return EmitResultInstructionAsOperand(N, ResultOps);
772 if (OpRec->isSubClassOf("SDNodeXForm"))
773 return EmitResultSDNodeXFormAsOperand(N, ResultOps);
774 errs() << "Unknown result node to emit code for: " << *N << '\n';
775 throw std::string("Unknown node in result pattern!");
778 void MatcherGen::EmitResultCode() {
779 // Patterns that match nodes with (potentially multiple) chain inputs have to
780 // merge them together into a token factor. This informs the generated code
781 // what all the chained nodes are.
782 if (!MatchedChainNodes.empty())
783 AddMatcher(new EmitMergeInputChainsMatcher
784 (MatchedChainNodes.data(), MatchedChainNodes.size()));
786 // Codegen the root of the result pattern, capturing the resulting values.
787 SmallVector<unsigned, 8> Ops;
788 EmitResultOperand(Pattern.getDstPattern(), Ops);
790 // At this point, we have however many values the result pattern produces.
791 // However, the input pattern might not need all of these. If there are
792 // excess values at the end (such as condition codes etc) just lop them off.
793 // This doesn't need to worry about flags or chains, just explicit results.
795 // FIXME2: This doesn't work because there is currently no way to get an
796 // accurate count of the # results the source pattern sets. This is because
797 // of the "parallel" construct in X86 land, which looks like this:
799 //def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
800 // (implicit EFLAGS)),
801 // (AND8rr GR8:$src1, GR8:$src2)>;
803 // This idiom means to match the two-result node X86and_flag (which is
804 // declared as returning a single result, because we can't match multi-result
805 // nodes yet). In this case, we would have to know that the input has two
806 // results. However, mul8r is modelled exactly the same way, but without
807 // implicit defs included. The fix is to support multiple results directly
808 // and eliminate 'parallel'.
810 // FIXME2: When this is fixed, we should revert the terrible hack in the
811 // OPC_EmitNode code in the interpreter.
813 const TreePatternNode *Src = Pattern.getSrcPattern();
814 unsigned NumSrcResults = Src->getTypeNum(0) != MVT::isVoid ? 1 : 0;
815 NumSrcResults += Pattern.getDstRegs().size();
816 assert(Ops.size() >= NumSrcResults && "Didn't provide enough results");
817 Ops.resize(NumSrcResults);
820 // If the matched pattern covers nodes which define a flag result, emit a node
821 // that tells the matcher about them so that it can update their results.
822 if (!MatchedFlagResultNodes.empty())
823 AddMatcher(new MarkFlagResultsMatcher(MatchedFlagResultNodes.data(),
824 MatchedFlagResultNodes.size()));
826 AddMatcher(new CompleteMatchMatcher(Ops.data(), Ops.size(), Pattern));
830 /// ConvertPatternToMatcher - Create the matcher for the specified pattern with
831 /// the specified variant. If the variant number is invalid, this returns null.
832 Matcher *llvm::ConvertPatternToMatcher(const PatternToMatch &Pattern,
834 const CodeGenDAGPatterns &CGP) {
835 MatcherGen Gen(Pattern, CGP);
837 // Generate the code for the matcher.
838 if (Gen.EmitMatcherCode(Variant))
841 // FIXME2: Kill extra MoveParent commands at the end of the matcher sequence.
842 // FIXME2: Split result code out to another table, and make the matcher end
843 // with an "Emit <index>" command. This allows result generation stuff to be
844 // shared and factored?
846 // If the match succeeds, then we generate Pattern.
847 Gen.EmitResultCode();
849 // Unconditional match.
850 return Gen.GetMatcher();