1 //===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class parses the Schedule.td file and produces an API that can be used
11 // to reason about whether an instruction can be added to a packet on a VLIW
12 // architecture. The class internally generates a deterministic finite
13 // automaton (DFA) that models all possible mappings of machine instructions
14 // to functional units as instructions are added to a packet.
16 //===----------------------------------------------------------------------===//
18 #include "CodeGenTarget.h"
19 #include "llvm/ADT/DenseSet.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/TableGen/Record.h"
22 #include "llvm/TableGen/TableGenBackend.h"
29 // class DFAPacketizerEmitter: class that generates and prints out the DFA
30 // for resource tracking.
33 class DFAPacketizerEmitter {
35 std::string TargetName;
37 // allInsnClasses is the set of all possible resources consumed by an
40 DenseSet<unsigned> allInsnClasses;
41 RecordKeeper &Records;
44 DFAPacketizerEmitter(RecordKeeper &R);
47 // collectAllInsnClasses: Populate allInsnClasses which is a set of units
48 // used in each stage.
50 void collectAllInsnClasses(const std::string &Name,
55 void run(raw_ostream &OS);
57 } // End anonymous namespace.
61 // State represents the usage of machine resources if the packet contains
62 // a set of instruction classes.
64 // Specifically, currentState is a set of bit-masks.
65 // The nth bit in a bit-mask indicates whether the nth resource is being used
66 // by this state. The set of bit-masks in a state represent the different
67 // possible outcomes of transitioning to this state.
68 // For example: consider a two resource architecture: resource L and resource M
69 // with three instruction classes: L, M, and L_or_M.
70 // From the initial state (currentState = 0x00), if we add instruction class
71 // L_or_M we will transition to a state with currentState = [0x01, 0x10]. This
72 // represents the possible resource states that can result from adding a L_or_M
75 // Another way of thinking about this transition is we are mapping a NDFA with
76 // two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10].
78 // A State instance also contains a collection of transitions from that state:
79 // a map from inputs to new states.
84 static int currentStateNum;
87 std::set<unsigned> stateInfo;
88 typedef std::map<unsigned, State *> TransitionMap;
89 TransitionMap Transitions;
92 State(const State &S);
94 bool operator<(const State &s) const {
95 return stateNum < s.stateNum;
99 // canAddInsnClass - Returns true if an instruction of type InsnClass is a
100 // valid transition from this state, i.e., can an instruction of type InsnClass
101 // be added to the packet represented by this state.
103 // PossibleStates is the set of valid resource states that ensue from valid
106 bool canAddInsnClass(unsigned InsnClass) const;
108 // AddInsnClass - Return all combinations of resource reservation
109 // which are possible from this state (PossibleStates).
111 void AddInsnClass(unsigned InsnClass, std::set<unsigned> &PossibleStates);
113 // addTransition - Add a transition from this state given the input InsnClass
115 void addTransition(unsigned InsnClass, State *To);
117 // hasTransition - Returns true if there is a transition from this state
118 // given the input InsnClass
120 bool hasTransition(unsigned InsnClass);
122 } // End anonymous namespace.
125 // class DFA: deterministic finite automaton for processor resource tracking.
133 // Set of states. Need to keep this sorted to emit the transition table.
134 typedef std::set<State *, less_ptr<State> > StateSet;
143 void addState(State *);
146 // writeTable: Print out a table representing the DFA.
148 void writeTableAndAPI(raw_ostream &OS, const std::string &ClassName);
150 } // End anonymous namespace.
154 // Constructors and destructors for State and DFA
157 stateNum(currentStateNum++), isInitial(false) {}
160 State::State(const State &S) :
161 stateNum(currentStateNum++), isInitial(S.isInitial),
162 stateInfo(S.stateInfo) {}
164 DFA::DFA(): currentState(NULL) {}
167 DeleteContainerPointers(states);
171 // addTransition - Add a transition from this state given the input InsnClass
173 void State::addTransition(unsigned InsnClass, State *To) {
174 assert(!Transitions.count(InsnClass) &&
175 "Cannot have multiple transitions for the same input");
176 Transitions[InsnClass] = To;
180 // hasTransition - Returns true if there is a transition from this state
181 // given the input InsnClass
183 bool State::hasTransition(unsigned InsnClass) {
184 return Transitions.count(InsnClass) > 0;
188 // AddInsnClass - Return all combinations of resource reservation
189 // which are possible from this state (PossibleStates).
191 void State::AddInsnClass(unsigned InsnClass,
192 std::set<unsigned> &PossibleStates) {
194 // Iterate over all resource states in currentState.
197 for (std::set<unsigned>::iterator SI = stateInfo.begin();
198 SI != stateInfo.end(); ++SI) {
199 unsigned thisState = *SI;
202 // Iterate over all possible resources used in InsnClass.
203 // For ex: for InsnClass = 0x11, all resources = {0x01, 0x10}.
206 DenseSet<unsigned> VisitedResourceStates;
207 for (unsigned int j = 0; j < sizeof(InsnClass) * 8; ++j) {
208 if ((0x1 << j) & InsnClass) {
210 // For each possible resource used in InsnClass, generate the
211 // resource state if that resource was used.
213 unsigned ResultingResourceState = thisState | (0x1 << j);
215 // Check if the resulting resource state can be accommodated in this
217 // We compute ResultingResourceState OR thisState.
218 // If the result of the OR is different than thisState, it implies
219 // that there is at least one resource that can be used to schedule
220 // InsnClass in the current packet.
221 // Insert ResultingResourceState into PossibleStates only if we haven't
222 // processed ResultingResourceState before.
224 if ((ResultingResourceState != thisState) &&
225 (VisitedResourceStates.count(ResultingResourceState) == 0)) {
226 VisitedResourceStates.insert(ResultingResourceState);
227 PossibleStates.insert(ResultingResourceState);
237 // canAddInsnClass - Quickly verifies if an instruction of type InsnClass is a
238 // valid transition from this state i.e., can an instruction of type InsnClass
239 // be added to the packet represented by this state.
241 bool State::canAddInsnClass(unsigned InsnClass) const {
242 for (std::set<unsigned>::const_iterator SI = stateInfo.begin();
243 SI != stateInfo.end(); ++SI) {
244 if (~*SI & InsnClass)
251 void DFA::initialize() {
252 assert(currentState && "Missing current state");
253 currentState->isInitial = true;
257 void DFA::addState(State *S) {
258 assert(!states.count(S) && "State already exists");
263 int State::currentStateNum = 0;
265 DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
266 TargetName(CodeGenTarget(R).getName()),
267 allInsnClasses(), Records(R) {}
271 // writeTableAndAPI - Print out a table representing the DFA and the
272 // associated API to create a DFA packetizer.
275 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
277 // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for
281 void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName) {
282 DFA::StateSet::iterator SI = states.begin();
283 // This table provides a map to the beginning of the transitions for State s
284 // in DFAStateInputTable.
285 std::vector<int> StateEntry(states.size());
287 OS << "namespace llvm {\n\n";
288 OS << "const int " << TargetName << "DFAStateInputTable[][2] = {\n";
290 // Tracks the total valid transitions encountered so far. It is used
291 // to construct the StateEntry table.
292 int ValidTransitions = 0;
293 for (unsigned i = 0; i < states.size(); ++i, ++SI) {
294 assert (((*SI)->stateNum == (int) i) && "Mismatch in state numbers");
295 StateEntry[i] = ValidTransitions;
296 for (State::TransitionMap::iterator
297 II = (*SI)->Transitions.begin(), IE = (*SI)->Transitions.end();
299 OS << "{" << II->first << ", "
300 << II->second->stateNum
303 ValidTransitions += (*SI)->Transitions.size();
305 // If there are no valid transitions from this stage, we need a sentinel
307 if (ValidTransitions == StateEntry[i]) {
315 OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
317 // Multiply i by 2 since each entry in DFAStateInputTable is a set of
319 for (unsigned i = 0; i < states.size(); ++i)
320 OS << StateEntry[i] << ", ";
323 OS << "} // namespace\n";
327 // Emit DFA Packetizer tables if the target is a VLIW machine.
329 std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
330 OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
331 OS << "namespace llvm {\n";
332 OS << "DFAPacketizer *" << SubTargetClassName << "::"
333 << "createDFAPacketizer(const InstrItineraryData *IID) const {\n"
334 << " return new DFAPacketizer(IID, " << TargetName
335 << "DFAStateInputTable, " << TargetName << "DFAStateEntryTable);\n}\n\n";
336 OS << "} // End llvm namespace \n";
341 // collectAllInsnClasses - Populate allInsnClasses which is a set of units
342 // used in each stage.
344 void DFAPacketizerEmitter::collectAllInsnClasses(const std::string &Name,
348 // Collect processor itineraries.
349 std::vector<Record*> ProcItinList =
350 Records.getAllDerivedDefinitions("ProcessorItineraries");
352 // If just no itinerary then don't bother.
353 if (ProcItinList.size() < 2)
355 std::map<std::string, unsigned> NameToBitsMap;
357 // Parse functional units for all the itineraries.
358 for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) {
359 Record *Proc = ProcItinList[i];
360 std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
362 // Convert macros to bits for each stage.
363 for (unsigned i = 0, N = FUs.size(); i < N; ++i)
364 NameToBitsMap[FUs[i]->getName()] = (unsigned) (1U << i);
367 const std::vector<Record*> &StageList =
368 ItinData->getValueAsListOfDefs("Stages");
370 // The number of stages.
371 NStages = StageList.size();
374 unsigned UnitBitValue = 0;
376 // Compute the bitwise or of each unit used in this stage.
377 for (unsigned i = 0; i < NStages; ++i) {
378 const Record *Stage = StageList[i];
381 const std::vector<Record*> &UnitList =
382 Stage->getValueAsListOfDefs("Units");
384 for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
385 // Conduct bitwise or.
386 std::string UnitName = UnitList[j]->getName();
387 assert(NameToBitsMap.count(UnitName));
388 UnitBitValue |= NameToBitsMap[UnitName];
391 if (UnitBitValue != 0)
392 allInsnClasses.insert(UnitBitValue);
398 // Run the worklist algorithm to generate the DFA.
400 void DFAPacketizerEmitter::run(raw_ostream &OS) {
402 // Collect processor iteraries.
403 std::vector<Record*> ProcItinList =
404 Records.getAllDerivedDefinitions("ProcessorItineraries");
407 // Collect the instruction classes.
409 for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
410 Record *Proc = ProcItinList[i];
412 // Get processor itinerary name.
413 const std::string &Name = Proc->getName();
416 if (Name == "NoItineraries")
419 // Sanity check for at least one instruction itinerary class.
420 unsigned NItinClasses =
421 Records.getAllDerivedDefinitions("InstrItinClass").size();
422 if (NItinClasses == 0)
425 // Get itinerary data list.
426 std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
428 // Collect instruction classes for all itinerary data.
429 for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
430 Record *ItinData = ItinDataList[j];
432 collectAllInsnClasses(Name, ItinData, NStages, OS);
438 // Run a worklist algorithm to generate the DFA.
441 State *Initial = new State;
442 Initial->isInitial = true;
443 Initial->stateInfo.insert(0x0);
445 SmallVector<State*, 32> WorkList;
446 std::map<std::set<unsigned>, State*> Visited;
448 WorkList.push_back(Initial);
451 // Worklist algorithm to create a DFA for processor resource tracking.
452 // C = {set of InsnClasses}
453 // Begin with initial node in worklist. Initial node does not have
454 // any consumed resources,
455 // ResourceState = 0x0
457 // While worklist != empty
458 // S = first element of worklist
459 // For every instruction class C
460 // if we can accommodate C in S:
461 // S' = state with resource states = {S Union C}
462 // Add a new transition: S x C -> S'
463 // If S' is not in Visited:
464 // Add S' to worklist
467 while (!WorkList.empty()) {
468 State *current = WorkList.pop_back_val();
469 for (DenseSet<unsigned>::iterator CI = allInsnClasses.begin(),
470 CE = allInsnClasses.end(); CI != CE; ++CI) {
471 unsigned InsnClass = *CI;
473 std::set<unsigned> NewStateResources;
475 // If we haven't already created a transition for this input
476 // and the state can accommodate this InsnClass, create a transition.
478 if (!current->hasTransition(InsnClass) &&
479 current->canAddInsnClass(InsnClass)) {
480 State *NewState = NULL;
481 current->AddInsnClass(InsnClass, NewStateResources);
482 assert(NewStateResources.size() && "New states must be generated");
485 // If we have seen this state before, then do not create a new state.
488 std::map<std::set<unsigned>, State*>::iterator VI;
489 if ((VI = Visited.find(NewStateResources)) != Visited.end())
490 NewState = VI->second;
492 NewState = new State;
493 NewState->stateInfo = NewStateResources;
494 D.addState(NewState);
495 Visited[NewStateResources] = NewState;
496 WorkList.push_back(NewState);
499 current->addTransition(InsnClass, NewState);
504 // Print out the table.
505 D.writeTableAndAPI(OS, TargetName);
510 void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
511 emitSourceFileHeader("Target DFA Packetizer Tables", OS);
512 DFAPacketizerEmitter(RK).run(OS);
515 } // End llvm namespace