1 //===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class parses the Schedule.td file and produces an API that can be used
11 // to reason about whether an instruction can be added to a packet on a VLIW
12 // architecture. The class internally generates a deterministic finite
13 // automaton (DFA) that models all possible mappings of machine instructions
14 // to functional units as instructions are added to a packet.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "dfa-emitter"
20 #include "CodeGenTarget.h"
21 #include "llvm/ADT/DenseSet.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/CodeGen/DFAPacketizerDefs.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
27 #include "llvm/Support/Debug.h"
34 // To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
36 // dbgsInsnClass - When debugging, print instruction class stages.
38 void dbgsInsnClass(const std::vector<unsigned> &InsnClass);
40 // dbgsStateInfo - When debugging, print the set of state info.
42 void dbgsStateInfo(const std::set<unsigned> &stateInfo);
44 // dbgsIndent - When debugging, indent by the specified amount.
46 void dbgsIndent(unsigned indent);
49 // class DFAPacketizerEmitter: class that generates and prints out the DFA
50 // for resource tracking.
53 class DFAPacketizerEmitter {
55 std::string TargetName;
57 // allInsnClasses is the set of all possible resources consumed by an
60 std::vector<std::vector<unsigned>> allInsnClasses;
61 RecordKeeper &Records;
64 DFAPacketizerEmitter(RecordKeeper &R);
67 // collectAllFuncUnits - Construct a map of function unit names to bits.
69 int collectAllFuncUnits(std::vector<Record*> &ProcItinList,
70 std::map<std::string, unsigned> &FUNameToBitsMap,
75 // collectAllComboFuncs - Construct a map from a combo function unit bit to
76 // the bits of all included functional units.
78 int collectAllComboFuncs(std::vector<Record*> &ComboFuncList,
79 std::map<std::string, unsigned> &FUNameToBitsMap,
80 std::map<unsigned, unsigned> &ComboBitToBitsMap,
84 // collectOneInsnClass - Populate allInsnClasses with one instruction class.
86 int collectOneInsnClass(const std::string &ProcName,
87 std::vector<Record*> &ProcItinList,
88 std::map<std::string, unsigned> &FUNameToBitsMap,
93 // collectAllInsnClasses - Populate allInsnClasses which is a set of units
94 // used in each stage.
96 int collectAllInsnClasses(const std::string &ProcName,
97 std::vector<Record*> &ProcItinList,
98 std::map<std::string, unsigned> &FUNameToBitsMap,
99 std::vector<Record*> &ItinDataList,
103 void run(raw_ostream &OS);
105 } // End anonymous namespace.
109 // State represents the usage of machine resources if the packet contains
110 // a set of instruction classes.
112 // Specifically, currentState is a set of bit-masks.
113 // The nth bit in a bit-mask indicates whether the nth resource is being used
114 // by this state. The set of bit-masks in a state represent the different
115 // possible outcomes of transitioning to this state.
116 // For example: consider a two resource architecture: resource L and resource M
117 // with three instruction classes: L, M, and L_or_M.
118 // From the initial state (currentState = 0x00), if we add instruction class
119 // L_or_M we will transition to a state with currentState = [0x01, 0x10]. This
120 // represents the possible resource states that can result from adding a L_or_M
123 // Another way of thinking about this transition is we are mapping a NDFA with
124 // two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10].
126 // A State instance also contains a collection of transitions from that state:
127 // a map from inputs to new states.
132 static int currentStateNum;
133 // stateNum is the only member used for equality/ordering, all other members
134 // can be mutated even in const State objects.
136 mutable bool isInitial;
137 mutable std::set<unsigned> stateInfo;
138 typedef std::map<std::vector<unsigned>, const State *> TransitionMap;
139 mutable TransitionMap Transitions;
143 bool operator<(const State &s) const {
144 return stateNum < s.stateNum;
148 // canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
149 // may be a valid transition from this state i.e., can an instruction of type
150 // InsnClass be added to the packet represented by this state.
152 // Note that for multiple stages, this quick check does not take into account
153 // any possible resource competition between the stages themselves. That is
154 // enforced in AddInsnClassStages which checks the cross product of all
155 // stages for resource availability (which is a more involved check).
157 bool canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
158 std::map<unsigned, unsigned> &ComboBitToBitsMap) const;
160 // AddInsnClass - Return all combinations of resource reservation
161 // which are possible from this state (PossibleStates).
163 // PossibleStates is the set of valid resource states that ensue from valid
166 void AddInsnClass(std::vector<unsigned> &InsnClass,
167 std::map<unsigned, unsigned> &ComboBitToBitsMap,
168 std::set<unsigned> &PossibleStates) const;
170 // AddInsnClassStages - Return all combinations of resource reservation
171 // resulting from the cross product of all stages for this InsnClass
172 // which are possible from this state (PossibleStates).
174 void AddInsnClassStages(std::vector<unsigned> &InsnClass,
175 std::map<unsigned, unsigned> &ComboBitToBitsMap,
176 unsigned chkstage, unsigned numstages,
177 unsigned prevState, unsigned origState,
178 DenseSet<unsigned> &VisitedResourceStates,
179 std::set<unsigned> &PossibleStates) const;
181 // addTransition - Add a transition from this state given the input InsnClass
183 void addTransition(std::vector<unsigned> InsnClass, const State *To) const;
185 // hasTransition - Returns true if there is a transition from this state
186 // given the input InsnClass
188 bool hasTransition(std::vector<unsigned> InsnClass) const;
190 } // End anonymous namespace.
193 // class DFA: deterministic finite automaton for processor resource tracking.
200 // Set of states. Need to keep this sorted to emit the transition table.
201 typedef std::set<State> StateSet;
209 const State &newState();
212 // writeTable: Print out a table representing the DFA.
214 void writeTableAndAPI(raw_ostream &OS, const std::string &ClassName,
215 int numInsnClasses = 0,
216 int maxResources = 0, int numCombos = 0, int maxStages = 0);
218 } // End anonymous namespace.
221 // To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
223 // dbgsInsnClass - When debugging, print instruction class stages.
225 void dbgsInsnClass(const std::vector<unsigned> &InsnClass) {
226 DEBUG(dbgs() << "InsnClass: ");
227 for (unsigned i = 0; i < InsnClass.size(); ++i) {
229 DEBUG(dbgs() << ", ");
231 DEBUG(dbgs() << "0x" << utohexstr(InsnClass[i]));
233 DFAInput InsnInput = getDFAInsnInput(InsnClass);
234 DEBUG(dbgs() << " (input: 0x" << utohexstr(InsnInput) << ")");
238 // dbgsStateInfo - When debugging, print the set of state info.
240 void dbgsStateInfo(const std::set<unsigned> &stateInfo) {
241 DEBUG(dbgs() << "StateInfo: ");
243 for (std::set<unsigned>::iterator SI = stateInfo.begin();
244 SI != stateInfo.end(); ++SI, ++i) {
245 unsigned thisState = *SI;
247 DEBUG(dbgs() << ", ");
249 DEBUG(dbgs() << "0x" << utohexstr(thisState));
254 // dbgsIndent - When debugging, indent by the specified amount.
256 void dbgsIndent(unsigned indent) {
257 for (unsigned i = 0; i < indent; ++i) {
258 DEBUG(dbgs() << " ");
264 // Constructors and destructors for State and DFA
267 stateNum(currentStateNum++), isInitial(false) {}
269 DFA::DFA(): currentState(nullptr) {}
272 // addTransition - Add a transition from this state given the input InsnClass
274 void State::addTransition(std::vector<unsigned> InsnClass, const State *To)
276 assert(!Transitions.count(InsnClass) &&
277 "Cannot have multiple transitions for the same input");
278 Transitions[InsnClass] = To;
282 // hasTransition - Returns true if there is a transition from this state
283 // given the input InsnClass
285 bool State::hasTransition(std::vector<unsigned> InsnClass) const {
286 return Transitions.count(InsnClass) > 0;
290 // AddInsnClass - Return all combinations of resource reservation
291 // which are possible from this state (PossibleStates).
293 // PossibleStates is the set of valid resource states that ensue from valid
296 void State::AddInsnClass(std::vector<unsigned> &InsnClass,
297 std::map<unsigned, unsigned> &ComboBitToBitsMap,
298 std::set<unsigned> &PossibleStates) const {
300 // Iterate over all resource states in currentState.
302 unsigned numstages = InsnClass.size();
303 assert((numstages > 0) && "InsnClass has no stages");
305 for (std::set<unsigned>::iterator SI = stateInfo.begin();
306 SI != stateInfo.end(); ++SI) {
307 unsigned thisState = *SI;
309 DenseSet<unsigned> VisitedResourceStates;
311 DEBUG(dbgs() << " thisState: 0x" << utohexstr(thisState) << "\n");
312 AddInsnClassStages(InsnClass, ComboBitToBitsMap,
313 numstages - 1, numstages,
314 thisState, thisState,
315 VisitedResourceStates, PossibleStates);
319 void State::AddInsnClassStages(std::vector<unsigned> &InsnClass,
320 std::map<unsigned, unsigned> &ComboBitToBitsMap,
321 unsigned chkstage, unsigned numstages,
322 unsigned prevState, unsigned origState,
323 DenseSet<unsigned> &VisitedResourceStates,
324 std::set<unsigned> &PossibleStates) const {
326 assert((chkstage < numstages) && "AddInsnClassStages: stage out of range");
327 unsigned thisStage = InsnClass[chkstage];
329 dbgsIndent((1 + numstages - chkstage) << 1);
330 DEBUG(dbgs() << "AddInsnClassStages " << chkstage
331 << " (0x" << utohexstr(thisStage) << ") from ");
332 dbgsInsnClass(InsnClass);
333 DEBUG(dbgs() << "\n");
336 // Iterate over all possible resources used in thisStage.
337 // For ex: for thisStage = 0x11, all resources = {0x01, 0x10}.
339 for (unsigned int j = 0; j < DFA_MAX_RESOURCES; ++j) {
340 unsigned resourceMask = (0x1 << j);
341 if (resourceMask & thisStage) {
342 unsigned combo = ComboBitToBitsMap[resourceMask];
343 if (combo && ((~prevState & combo) != combo)) {
344 DEBUG(dbgs() << "\tSkipped Add 0x" << utohexstr(prevState)
345 << " - combo op 0x" << utohexstr(resourceMask)
346 << " (0x" << utohexstr(combo) <<") cannot be scheduled\n");
350 // For each possible resource used in thisStage, generate the
351 // resource state if that resource was used.
353 unsigned ResultingResourceState = prevState | resourceMask | combo;
354 dbgsIndent((2 + numstages - chkstage) << 1);
355 DEBUG(dbgs() << "0x" << utohexstr(prevState)
356 << " | 0x" << utohexstr(resourceMask));
358 DEBUG(dbgs() << " | 0x" << utohexstr(combo));
360 DEBUG(dbgs() << " = 0x" << utohexstr(ResultingResourceState) << " ");
363 // If this is the final stage for this class
367 // Check if the resulting resource state can be accommodated in this
369 // We compute resource OR prevState (originally started as origState).
370 // If the result of the OR is different than origState, it implies
371 // that there is at least one resource that can be used to schedule
372 // thisStage in the current packet.
373 // Insert ResultingResourceState into PossibleStates only if we haven't
374 // processed ResultingResourceState before.
376 if (ResultingResourceState != prevState) {
377 if (VisitedResourceStates.count(ResultingResourceState) == 0) {
378 VisitedResourceStates.insert(ResultingResourceState);
379 PossibleStates.insert(ResultingResourceState);
380 DEBUG(dbgs() << "\tResultingResourceState: 0x"
381 << utohexstr(ResultingResourceState) << "\n");
383 DEBUG(dbgs() << "\tSkipped Add - state already seen\n");
386 DEBUG(dbgs() << "\tSkipped Add - no final resources available\n");
390 // If the current resource can be accommodated, check the next
391 // stage in InsnClass for available resources.
393 if (ResultingResourceState != prevState) {
394 DEBUG(dbgs() << "\n");
395 AddInsnClassStages(InsnClass, ComboBitToBitsMap,
396 chkstage - 1, numstages,
397 ResultingResourceState, origState,
398 VisitedResourceStates, PossibleStates);
400 DEBUG(dbgs() << "\tSkipped Add - no resources available\n");
409 // canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
410 // may be a valid transition from this state i.e., can an instruction of type
411 // InsnClass be added to the packet represented by this state.
413 // Note that this routine is performing conservative checks that can be
414 // quickly executed acting as a filter before calling AddInsnClassStages.
415 // Any cases allowed through here will be caught later in AddInsnClassStages
416 // which performs the more expensive exact check.
418 bool State::canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
419 std::map<unsigned, unsigned> &ComboBitToBitsMap) const {
420 for (std::set<unsigned>::const_iterator SI = stateInfo.begin();
421 SI != stateInfo.end(); ++SI) {
423 // Check to see if all required resources are available.
424 bool available = true;
426 // Inspect each stage independently.
427 // note: This is a conservative check as we aren't checking for
428 // possible resource competition between the stages themselves
429 // The full cross product is examined later in AddInsnClass.
430 for (unsigned i = 0; i < InsnClass.size(); ++i) {
431 unsigned resources = *SI;
432 if ((~resources & InsnClass[i]) == 0) {
436 // Make sure _all_ resources for a combo function are available.
437 // note: This is a quick conservative check as it won't catch an
438 // unscheduleable combo if this stage is an OR expression
439 // containing a combo.
440 // These cases are caught later in AddInsnClass.
441 unsigned combo = ComboBitToBitsMap[InsnClass[i]];
442 if (combo && ((~resources & combo) != combo)) {
443 DEBUG(dbgs() << "\tSkipped canMaybeAdd 0x" << utohexstr(resources)
444 << " - combo op 0x" << utohexstr(InsnClass[i])
445 << " (0x" << utohexstr(combo) <<") cannot be scheduled\n");
459 const State &DFA::newState() {
460 auto IterPair = states.insert(State());
461 assert(IterPair.second && "State already exists");
462 return *IterPair.first;
465 int State::currentStateNum = 0;
467 DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
468 TargetName(CodeGenTarget(R).getName()),
469 allInsnClasses(), Records(R) {}
473 // writeTableAndAPI - Print out a table representing the DFA and the
474 // associated API to create a DFA packetizer.
477 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
479 // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for
483 void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName,
485 int maxResources, int numCombos, int maxStages) {
487 unsigned numStates = states.size();
489 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
490 DEBUG(dbgs() << "writeTableAndAPI\n");
491 DEBUG(dbgs() << "Total states: " << numStates << "\n");
493 OS << "namespace llvm {\n";
495 OS << "\n// Input format:\n";
496 OS << "#define DFA_MAX_RESTERMS " << DFA_MAX_RESTERMS
497 << "\t// maximum AND'ed resource terms\n";
498 OS << "#define DFA_MAX_RESOURCES " << DFA_MAX_RESOURCES
499 << "\t// maximum resource bits in one term\n";
501 OS << "\n// " << TargetName << "DFAStateInputTable[][2] = "
502 << "pairs of <Input, NextState> for all valid\n";
503 OS << "// transitions.\n";
504 OS << "// " << numStates << "\tstates\n";
505 OS << "// " << numInsnClasses << "\tinstruction classes\n";
506 OS << "// " << maxResources << "\tresources max\n";
507 OS << "// " << numCombos << "\tcombo resources\n";
508 OS << "// " << maxStages << "\tstages max\n";
509 OS << "const " << DFA_TBLTYPE << " "
510 << TargetName << "DFAStateInputTable[][2] = {\n";
512 // This table provides a map to the beginning of the transitions for State s
513 // in DFAStateInputTable.
514 std::vector<int> StateEntry(numStates+1);
515 static const std::string SentinelEntry = "{-1, -1}";
517 // Tracks the total valid transitions encountered so far. It is used
518 // to construct the StateEntry table.
519 int ValidTransitions = 0;
520 DFA::StateSet::iterator SI = states.begin();
521 for (unsigned i = 0; i < numStates; ++i, ++SI) {
522 assert ((SI->stateNum == (int) i) && "Mismatch in state numbers");
523 StateEntry[i] = ValidTransitions;
524 for (State::TransitionMap::iterator
525 II = SI->Transitions.begin(), IE = SI->Transitions.end();
527 OS << "{0x" << utohexstr(getDFAInsnInput(II->first)) << ", "
528 << II->second->stateNum
531 ValidTransitions += SI->Transitions.size();
533 // If there are no valid transitions from this stage, we need a sentinel
535 if (ValidTransitions == StateEntry[i]) {
536 OS << SentinelEntry << ",\t";
540 OS << " // state " << i << ": " << StateEntry[i];
541 if (StateEntry[i] != (ValidTransitions-1)) { // More than one transition.
542 OS << "-" << (ValidTransitions-1);
547 // Print out a sentinel entry at the end of the StateInputTable. This is
548 // needed to iterate over StateInputTable in DFAPacketizer::ReadTable()
549 OS << SentinelEntry << "\t";
550 OS << " // state " << numStates << ": " << ValidTransitions;
554 OS << "// " << TargetName << "DFAStateEntryTable[i] = "
555 << "Index of the first entry in DFAStateInputTable for\n";
557 << "the ith state.\n";
558 OS << "// " << numStates << " states\n";
559 OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
561 // Multiply i by 2 since each entry in DFAStateInputTable is a set of
563 unsigned lastState = 0;
564 for (unsigned i = 0; i < numStates; ++i) {
565 if (i && ((i % 10) == 0)) {
567 OS << " // states " << (i-10) << ":" << lastState << "\n";
569 OS << StateEntry[i] << ", ";
572 // Print out the index to the sentinel entry in StateInputTable
573 OS << ValidTransitions << ", ";
574 OS << " // states " << (lastState+1) << ":" << numStates << "\n";
577 OS << "} // namespace\n";
581 // Emit DFA Packetizer tables if the target is a VLIW machine.
583 std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
584 OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
585 OS << "namespace llvm {\n";
586 OS << "DFAPacketizer *" << SubTargetClassName << "::"
587 << "createDFAPacketizer(const InstrItineraryData *IID) const {\n"
588 << " return new DFAPacketizer(IID, " << TargetName
589 << "DFAStateInputTable, " << TargetName << "DFAStateEntryTable);\n}\n\n";
590 OS << "} // End llvm namespace \n";
595 // collectAllFuncUnits - Construct a map of function unit names to bits.
597 int DFAPacketizerEmitter::collectAllFuncUnits(
598 std::vector<Record*> &ProcItinList,
599 std::map<std::string, unsigned> &FUNameToBitsMap,
602 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
603 DEBUG(dbgs() << "collectAllFuncUnits");
604 DEBUG(dbgs() << " (" << ProcItinList.size() << " itineraries)\n");
607 // Parse functional units for all the itineraries.
608 for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) {
609 Record *Proc = ProcItinList[i];
610 std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
612 DEBUG(dbgs() << " FU:" << i
613 << " (" << FUs.size() << " FUs) "
617 // Convert macros to bits for each stage.
618 unsigned numFUs = FUs.size();
619 for (unsigned j = 0; j < numFUs; ++j) {
620 assert ((j < DFA_MAX_RESOURCES) &&
621 "Exceeded maximum number of representable resources");
622 unsigned FuncResources = (unsigned) (1U << j);
623 FUNameToBitsMap[FUs[j]->getName()] = FuncResources;
624 DEBUG(dbgs() << " " << FUs[j]->getName()
625 << ":0x" << utohexstr(FuncResources));
627 if (((int) numFUs) > maxFUs) {
631 DEBUG(dbgs() << "\n");
637 // collectAllComboFuncs - Construct a map from a combo function unit bit to
638 // the bits of all included functional units.
640 int DFAPacketizerEmitter::collectAllComboFuncs(
641 std::vector<Record*> &ComboFuncList,
642 std::map<std::string, unsigned> &FUNameToBitsMap,
643 std::map<unsigned, unsigned> &ComboBitToBitsMap,
645 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
646 DEBUG(dbgs() << "collectAllComboFuncs");
647 DEBUG(dbgs() << " (" << ComboFuncList.size() << " sets)\n");
650 for (unsigned i = 0, N = ComboFuncList.size(); i < N; ++i) {
651 Record *Func = ComboFuncList[i];
652 std::vector<Record*> FUs = Func->getValueAsListOfDefs("CFD");
654 DEBUG(dbgs() << " CFD:" << i
655 << " (" << FUs.size() << " combo FUs) "
656 << Func->getName() << "\n");
658 // Convert macros to bits for each stage.
659 for (unsigned j = 0, N = FUs.size(); j < N; ++j) {
660 assert ((j < DFA_MAX_RESOURCES) &&
661 "Exceeded maximum number of DFA resources");
662 Record *FuncData = FUs[j];
663 Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc");
664 const std::vector<Record*> &FuncList =
665 FuncData->getValueAsListOfDefs("FuncList");
666 std::string ComboFuncName = ComboFunc->getName();
667 unsigned ComboBit = FUNameToBitsMap[ComboFuncName];
668 unsigned ComboResources = ComboBit;
669 DEBUG(dbgs() << " combo: " << ComboFuncName
670 << ":0x" << utohexstr(ComboResources) << "\n");
671 for (unsigned k = 0, M = FuncList.size(); k < M; ++k) {
672 std::string FuncName = FuncList[k]->getName();
673 unsigned FuncResources = FUNameToBitsMap[FuncName];
674 DEBUG(dbgs() << " " << FuncName
675 << ":0x" << utohexstr(FuncResources) << "\n");
676 ComboResources |= FuncResources;
678 ComboBitToBitsMap[ComboBit] = ComboResources;
680 DEBUG(dbgs() << " => combo bits: " << ComboFuncName << ":0x"
681 << utohexstr(ComboBit) << " = 0x"
682 << utohexstr(ComboResources) << "\n");
690 // collectOneInsnClass - Populate allInsnClasses with one instruction class
692 int DFAPacketizerEmitter::collectOneInsnClass(const std::string &ProcName,
693 std::vector<Record*> &ProcItinList,
694 std::map<std::string, unsigned> &FUNameToBitsMap,
697 const std::vector<Record*> &StageList =
698 ItinData->getValueAsListOfDefs("Stages");
700 // The number of stages.
701 unsigned NStages = StageList.size();
703 DEBUG(dbgs() << " " << ItinData->getValueAsDef("TheClass")->getName()
706 std::vector<unsigned> UnitBits;
708 // Compute the bitwise or of each unit used in this stage.
709 for (unsigned i = 0; i < NStages; ++i) {
710 const Record *Stage = StageList[i];
713 const std::vector<Record*> &UnitList =
714 Stage->getValueAsListOfDefs("Units");
716 DEBUG(dbgs() << " stage:" << i
717 << " [" << UnitList.size() << " units]:");
718 unsigned dbglen = 26; // cursor after stage dbgs
720 // Compute the bitwise or of each unit used in this stage.
721 unsigned UnitBitValue = 0;
722 for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
723 // Conduct bitwise or.
724 std::string UnitName = UnitList[j]->getName();
725 DEBUG(dbgs() << " " << j << ":" << UnitName);
726 dbglen += 3 + UnitName.length();
727 assert(FUNameToBitsMap.count(UnitName));
728 UnitBitValue |= FUNameToBitsMap[UnitName];
731 if (UnitBitValue != 0)
732 UnitBits.push_back(UnitBitValue);
734 while (dbglen <= 64) { // line up bits dbgs
736 DEBUG(dbgs() << "\t");
738 DEBUG(dbgs() << " (bits: 0x" << utohexstr(UnitBitValue) << ")\n");
741 if (UnitBits.size() > 0)
742 allInsnClasses.push_back(UnitBits);
744 DEBUG(dbgs() << " ");
745 dbgsInsnClass(UnitBits);
746 DEBUG(dbgs() << "\n");
752 // collectAllInsnClasses - Populate allInsnClasses which is a set of units
753 // used in each stage.
755 int DFAPacketizerEmitter::collectAllInsnClasses(const std::string &ProcName,
756 std::vector<Record*> &ProcItinList,
757 std::map<std::string, unsigned> &FUNameToBitsMap,
758 std::vector<Record*> &ItinDataList,
761 // Collect all instruction classes.
762 unsigned M = ItinDataList.size();
764 int numInsnClasses = 0;
765 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n"
766 << "collectAllInsnClasses "
768 << " (" << M << " classes)\n");
770 // Collect stages for each instruction class for all itinerary data
771 for (unsigned j = 0; j < M; j++) {
772 Record *ItinData = ItinDataList[j];
773 int NStages = collectOneInsnClass(ProcName, ProcItinList,
774 FUNameToBitsMap, ItinData, OS);
775 if (NStages > maxStages) {
780 return numInsnClasses;
784 // Run the worklist algorithm to generate the DFA.
786 void DFAPacketizerEmitter::run(raw_ostream &OS) {
788 // Collect processor iteraries.
789 std::vector<Record*> ProcItinList =
790 Records.getAllDerivedDefinitions("ProcessorItineraries");
793 // Collect the Functional units.
795 std::map<std::string, unsigned> FUNameToBitsMap;
796 int maxResources = 0;
797 collectAllFuncUnits(ProcItinList,
798 FUNameToBitsMap, maxResources, OS);
801 // Collect the Combo Functional units.
803 std::map<unsigned, unsigned> ComboBitToBitsMap;
804 std::vector<Record*> ComboFuncList =
805 Records.getAllDerivedDefinitions("ComboFuncUnits");
806 int numCombos = collectAllComboFuncs(ComboFuncList,
807 FUNameToBitsMap, ComboBitToBitsMap, OS);
810 // Collect the itineraries.
813 int numInsnClasses = 0;
814 for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
815 Record *Proc = ProcItinList[i];
817 // Get processor itinerary name.
818 const std::string &ProcName = Proc->getName();
821 if (ProcName == "NoItineraries")
824 // Sanity check for at least one instruction itinerary class.
825 unsigned NItinClasses =
826 Records.getAllDerivedDefinitions("InstrItinClass").size();
827 if (NItinClasses == 0)
830 // Get itinerary data list.
831 std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
833 // Collect all instruction classes
834 numInsnClasses += collectAllInsnClasses(ProcName, ProcItinList,
835 FUNameToBitsMap, ItinDataList, maxStages, OS);
839 // Run a worklist algorithm to generate the DFA.
842 const State *Initial = &D.newState();
843 Initial->isInitial = true;
844 Initial->stateInfo.insert(0x0);
845 SmallVector<const State*, 32> WorkList;
846 // std::queue<State*> WorkList;
847 std::map<std::set<unsigned>, const State*> Visited;
849 WorkList.push_back(Initial);
852 // Worklist algorithm to create a DFA for processor resource tracking.
853 // C = {set of InsnClasses}
854 // Begin with initial node in worklist. Initial node does not have
855 // any consumed resources,
856 // ResourceState = 0x0
858 // While worklist != empty
859 // S = first element of worklist
860 // For every instruction class C
861 // if we can accommodate C in S:
862 // S' = state with resource states = {S Union C}
863 // Add a new transition: S x C -> S'
864 // If S' is not in Visited:
865 // Add S' to worklist
868 while (!WorkList.empty()) {
869 const State *current = WorkList.pop_back_val();
870 DEBUG(dbgs() << "---------------------\n");
871 DEBUG(dbgs() << "Processing state: " << current->stateNum << " - ");
872 dbgsStateInfo(current->stateInfo);
873 DEBUG(dbgs() << "\n");
874 for (unsigned i = 0; i < allInsnClasses.size(); i++) {
875 std::vector<unsigned> InsnClass = allInsnClasses[i];
876 DEBUG(dbgs() << i << " ");
877 dbgsInsnClass(InsnClass);
878 DEBUG(dbgs() << "\n");
880 std::set<unsigned> NewStateResources;
882 // If we haven't already created a transition for this input
883 // and the state can accommodate this InsnClass, create a transition.
885 if (!current->hasTransition(InsnClass) &&
886 current->canMaybeAddInsnClass(InsnClass, ComboBitToBitsMap)) {
887 const State *NewState = NULL;
888 current->AddInsnClass(InsnClass, ComboBitToBitsMap, NewStateResources);
889 if (NewStateResources.size() == 0) {
890 DEBUG(dbgs() << " Skipped - no new states generated\n");
894 DEBUG(dbgs() << "\t");
895 dbgsStateInfo(NewStateResources);
896 DEBUG(dbgs() << "\n");
899 // If we have seen this state before, then do not create a new state.
901 auto VI = Visited.find(NewStateResources);
902 if (VI != Visited.end()) {
903 NewState = VI->second;
904 DEBUG(dbgs() << "\tFound existing state: "
905 << NewState->stateNum << " - ");
906 dbgsStateInfo(NewState->stateInfo);
907 DEBUG(dbgs() << "\n");
909 NewState = &D.newState();
910 NewState->stateInfo = NewStateResources;
911 Visited[NewStateResources] = NewState;
912 WorkList.push_back(NewState);
913 DEBUG(dbgs() << "\tAccepted new state: "
914 << NewState->stateNum << " - ");
915 dbgsStateInfo(NewState->stateInfo);
916 DEBUG(dbgs() << "\n");
919 current->addTransition(InsnClass, NewState);
924 // Print out the table.
925 D.writeTableAndAPI(OS, TargetName,
926 numInsnClasses, maxResources, numCombos, maxStages);
931 void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
932 emitSourceFileHeader("Target DFA Packetizer Tables", OS);
933 DFAPacketizerEmitter(RK).run(OS);
936 } // End llvm namespace