1 //===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class parses the Schedule.td file and produces an API that can be used
11 // to reason about whether an instruction can be added to a packet on a VLIW
12 // architecture. The class internally generates a deterministic finite
13 // automaton (DFA) that models all possible mappings of machine instructions
14 // to functional units as instructions are added to a packet.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/TableGen/Record.h"
21 #include "CodeGenTarget.h"
22 #include "DFAPacketizerEmitter.h"
29 // State represents the usage of machine resources if the packet contains
30 // a set of instruction classes.
32 // Specifically, currentState is a set of bit-masks
33 // The nth bit in a bit-mask indicates whether the nth resource is being used
34 // by this state. The set of bit-masks in a state represent the different
35 // possible outcomes of transitioning to this state.
36 // For example: Consider a two resource architecture: Resource L and Resource M
37 // with three instruction classes: L, M, and L_or_M
38 // From the initial state (currentState = 0x00), if we add instruction class
39 // L_or_M we will transition to a state with currentState = [0x01, 0x10]. This
40 // represents the possible resource states that can result from adding a L_or_M
43 // Another way of thinking about this transition is we are mapping a NDFA with
44 // two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10]
50 static int currentStateNum;
53 std::set<unsigned> stateInfo;
56 State(const State& S);
59 // canAddInsnClass - Returns true if an instruction of type InsnClass is a
60 // valid transition from this state i.e., can an instruction of type InsnClass
61 // be added to the packet represented by this state
63 // PossibleStates is the set of valid resource states that ensue from valid
66 bool canAddInsnClass(unsigned InsnClass, std::set<unsigned>& PossibleStates);
68 } // End anonymous namespace
74 static int currentTransitionNum;
80 Transition(State* from_, unsigned input_, State* to_);
82 } // End anonymous namespace
86 // Comparators to keep set of states sorted
90 bool operator()(const State* s1, const State* s2) const;
92 } // End anonymous namespace
96 // class DFA: deterministic finite automaton for processor resource tracking
103 // Set of states. Need to keep this sorted to emit the transition table
104 std::set<State*, ltState> states;
106 // Map from a state to the list of transitions with that state as source
107 std::map<State*, SmallVector<Transition*, 16>, ltState> stateTransitions;
110 // Highest valued Input seen
111 unsigned LargestInput;
117 void addState(State*);
118 void addTransition(Transition*);
121 // getTransition - Return the state when a transition is made from
122 // State From with Input I. If a transition is not found, return NULL
124 State* getTransition(State*, unsigned);
127 // isValidTransition: Predicate that checks if there is a valid transition
128 // from state From on input InsnClass
130 bool isValidTransition(State* From, unsigned InsnClass);
133 // writeTable: Print out a table representing the DFA
135 void writeTableAndAPI(raw_ostream &OS, const std::string& ClassName);
137 } // End anonymous namespace
141 // Constructors for State, Transition, and DFA
144 stateNum(currentStateNum++), isInitial(false) {}
147 State::State(const State& S) :
148 stateNum(currentStateNum++), isInitial(S.isInitial),
149 stateInfo(S.stateInfo) {}
152 Transition::Transition(State* from_, unsigned input_, State* to_) :
153 transitionNum(currentTransitionNum++), from(from_), input(input_),
161 bool ltState::operator()(const State* s1, const State* s2) const {
162 return (s1->stateNum < s2->stateNum);
167 // canAddInsnClass - Returns true if an instruction of type InsnClass is a
168 // valid transition from this state i.e., can an instruction of type InsnClass
169 // be added to the packet represented by this state
171 // PossibleStates is the set of valid resource states that ensue from valid
174 bool State::canAddInsnClass(unsigned InsnClass,
175 std::set<unsigned>& PossibleStates) {
177 // Iterate over all resource states in currentState
179 bool AddedState = false;
181 for (std::set<unsigned>::iterator SI = stateInfo.begin();
182 SI != stateInfo.end(); ++SI) {
183 unsigned thisState = *SI;
186 // Iterate over all possible resources used in InsnClass
187 // For ex: for InsnClass = 0x11, all resources = {0x01, 0x10}
190 DenseSet<unsigned> VisitedResourceStates;
191 for (unsigned int j = 0; j < sizeof(InsnClass) * 8; ++j) {
192 if ((0x1 << j) & InsnClass) {
194 // For each possible resource used in InsnClass, generate the
195 // resource state if that resource was used
197 unsigned ResultingResourceState = thisState | (0x1 << j);
199 // Check if the resulting resource state can be accommodated in this
201 // We compute ResultingResourceState OR thisState
202 // If the result of the OR is different than thisState, it implies
203 // that there is at least one resource that can be used to schedule
204 // InsnClass in the current packet
205 // Insert ResultingResourceState into PossibleStates only if we haven't
206 // processed ResultingResourceState before
208 if ((ResultingResourceState != thisState) &&
209 (VisitedResourceStates.count(ResultingResourceState) == 0)) {
210 VisitedResourceStates.insert(ResultingResourceState);
211 PossibleStates.insert(ResultingResourceState);
222 void DFA::initialize() {
223 currentState->isInitial = true;
227 void DFA::addState(State* S) {
228 assert(!states.count(S) && "State already exists");
233 void DFA::addTransition(Transition* T) {
234 // Update LargestInput
235 if (T->input > LargestInput)
236 LargestInput = T->input;
238 // Add the new transition
239 stateTransitions[T->from].push_back(T);
244 // getTransition - Return the state when a transition is made from
245 // State From with Input I. If a transition is not found, return NULL
247 State* DFA::getTransition(State* From, unsigned I) {
248 // Do we have a transition from state From?
249 if (!stateTransitions.count(From))
252 // Do we have a transition from state From with Input I?
253 for (SmallVector<Transition*, 16>::iterator VI =
254 stateTransitions[From].begin();
255 VI != stateTransitions[From].end(); ++VI)
256 if ((*VI)->input == I)
263 bool DFA::isValidTransition(State* From, unsigned InsnClass) {
264 return (getTransition(From, InsnClass) != NULL);
268 int State::currentStateNum = 0;
269 int Transition::currentTransitionNum = 0;
271 DFAGen::DFAGen(RecordKeeper& R):
272 TargetName(CodeGenTarget(R).getName()),
273 allInsnClasses(), Records(R) {}
277 // writeTableAndAPI - Print out a table representing the DFA and the
278 // associated API to create a DFA packetizer
281 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
283 // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for
287 void DFA::writeTableAndAPI(raw_ostream &OS, const std::string& TargetName) {
288 std::set<State*, ltState>::iterator SI = states.begin();
289 // This table provides a map to the beginning of the transitions for State s
290 // in DFAStateInputTable i.e.,
291 std::vector<int> StateEntry(states.size());
293 OS << "namespace llvm {\n\n";
294 OS << "const int " << TargetName << "DFAStateInputTable[][2] = {\n";
296 // Tracks the total valid transitions encountered so far. It is used
297 // to construct the StateEntry table
298 int ValidTransitions = 0;
299 for (unsigned i = 0; i < states.size(); ++i, ++SI) {
300 StateEntry[i] = ValidTransitions;
301 for (unsigned j = 0; j <= LargestInput; ++j) {
302 assert (((*SI)->stateNum == (int) i) && "Mismatch in state numbers");
303 if (!isValidTransition(*SI, j))
306 OS << "{" << j << ", "
307 << getTransition(*SI, j)->stateNum
312 /* If there are no valid transitions from this stage, we need a sentinel
314 if (ValidTransitions == StateEntry[i])
320 OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
322 // Multiply i by 2 since each entry in DFAStateInputTable is a set of
324 for (unsigned i = 0; i < states.size(); ++i)
325 OS << StateEntry[i] << ", ";
328 OS << "} // namespace\n";
332 // Emit DFA Packetizer tables if the target is a VLIW machine
334 std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
335 OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
336 OS << "namespace llvm {\n";
337 OS << "DFAPacketizer* " << SubTargetClassName << "::"
338 << "createDFAPacketizer(const InstrItineraryData *IID) const {\n"
339 << " return new DFAPacketizer(IID, " << TargetName
340 << "DFAStateInputTable, " << TargetName << "DFAStateEntryTable);\n}\n\n";
341 OS << "} // End llvm namespace \n";
346 // collectAllInsnClasses - Populate allInsnClasses which is a set of units
347 // used in each stage.
349 void DFAGen::collectAllInsnClasses(const std::string &Name,
353 // Collect processor itineraries
354 std::vector<Record*> ProcItinList =
355 Records.getAllDerivedDefinitions("ProcessorItineraries");
357 // If just no itinerary then don't bother
358 if (ProcItinList.size() < 2)
360 std::map<std::string, unsigned> NameToBitsMap;
362 // Parse functional units for all the itineraries.
363 for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) {
364 Record *Proc = ProcItinList[i];
365 std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
367 // Convert macros to bits for each stage
368 for (unsigned i = 0, N = FUs.size(); i < N; ++i)
369 NameToBitsMap[FUs[i]->getName()] = (unsigned) (1U << i);
372 const std::vector<Record*> &StageList =
373 ItinData->getValueAsListOfDefs("Stages");
375 // The number of stages
376 NStages = StageList.size();
379 unsigned UnitBitValue = 0;
381 // Compute the bitwise or of each unit used in this stage
382 for (unsigned i = 0; i < NStages; ++i) {
383 const Record *Stage = StageList[i];
386 const std::vector<Record*> &UnitList =
387 Stage->getValueAsListOfDefs("Units");
389 for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
390 // Conduct bitwise or
391 std::string UnitName = UnitList[j]->getName();
392 assert(NameToBitsMap.count(UnitName));
393 UnitBitValue |= NameToBitsMap[UnitName];
396 if (UnitBitValue != 0)
397 allInsnClasses.insert(UnitBitValue);
403 // Run the worklist algorithm to generate the DFA
405 void DFAGen::run(raw_ostream &OS) {
406 EmitSourceFileHeader("Target DFA Packetizer Tables", OS);
408 // Collect processor iteraries
409 std::vector<Record*> ProcItinList =
410 Records.getAllDerivedDefinitions("ProcessorItineraries");
413 // Collect the instruction classes
415 for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
416 Record *Proc = ProcItinList[i];
418 // Get processor itinerary name
419 const std::string &Name = Proc->getName();
422 if (Name == "NoItineraries")
425 // Sanity check for at least one instruction itinerary class
426 unsigned NItinClasses =
427 Records.getAllDerivedDefinitions("InstrItinClass").size();
428 if (NItinClasses == 0)
431 // Get itinerary data list
432 std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
434 // Collect instruction classes for all itinerary data
435 for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
436 Record *ItinData = ItinDataList[j];
438 collectAllInsnClasses(Name, ItinData, NStages, OS);
444 // Run a worklist algorithm to generate the DFA
447 State* Initial = new State;
448 Initial->isInitial = true;
449 Initial->stateInfo.insert(0x0);
451 SmallVector<State*, 32> WorkList;
452 std::map<std::set<unsigned>, State*> Visited;
454 WorkList.push_back(Initial);
457 // Worklist algorithm to create a DFA for processor resource tracking
458 // C = {set of InsnClasses}
459 // Begin with initial node in worklist. Initial node does not have
460 // any consumed resources,
461 // ResourceState = 0x0
463 // While worklist != empty
464 // S = first element of worklist
465 // For every instruction class C
466 // if we can accommodate C in S:
467 // S' = state with resource states = {S Union C}
468 // Add a new transition: S x C -> S'
469 // If S' is not in Visited:
470 // Add S' to worklist
473 while (!WorkList.empty()) {
474 State* current = WorkList.pop_back_val();
475 for (DenseSet<unsigned>::iterator CI = allInsnClasses.begin(),
476 CE = allInsnClasses.end(); CI != CE; ++CI) {
477 unsigned InsnClass = *CI;
479 std::set<unsigned> NewStateResources;
481 // If we haven't already created a transition for this input
482 // and the state can accommodate this InsnClass, create a transition
484 if (!D.getTransition(current, InsnClass) &&
485 current->canAddInsnClass(InsnClass, NewStateResources)) {
486 State* NewState = NULL;
489 // If we have seen this state before, then do not create a new state
492 std::map<std::set<unsigned>, State*>::iterator VI;
493 if ((VI = Visited.find(NewStateResources)) != Visited.end())
494 NewState = VI->second;
496 NewState = new State;
497 NewState->stateInfo = NewStateResources;
498 D.addState(NewState);
499 Visited[NewStateResources] = NewState;
500 WorkList.push_back(NewState);
503 Transition* NewTransition = new Transition(current, InsnClass,
505 D.addTransition(NewTransition);
510 // Print out the table
511 D.writeTableAndAPI(OS, TargetName);