1 //===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "DisassemblerEmitter.h"
11 #include "CodeGenTarget.h"
13 #include "X86DisassemblerTables.h"
14 #include "X86RecognizableInstr.h"
16 using namespace llvm::X86Disassembler;
18 /// DisassemblerEmitter - Contains disassembler table emitters for various
21 /// X86 Disassembler Emitter
23 /// *** IF YOU'RE HERE TO RESOLVE A "Primary decode conflict", LOOK DOWN NEAR
24 /// THE END OF THIS COMMENT!
26 /// The X86 disassembler emitter is part of the X86 Disassembler, which is
27 /// documented in lib/Target/X86/X86Disassembler.h.
29 /// The emitter produces the tables that the disassembler uses to translate
30 /// instructions. The emitter generates the following tables:
32 /// - One table (CONTEXTS_SYM) that contains a mapping of attribute masks to
33 /// instruction contexts. Although for each attribute there are cases where
34 /// that attribute determines decoding, in the majority of cases decoding is
35 /// the same whether or not an attribute is present. For example, a 64-bit
36 /// instruction with an OPSIZE prefix and an XS prefix decodes the same way in
37 /// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix
38 /// may have effects on its execution, but does not change the instruction
39 /// returned.) This allows considerable space savings in other tables.
40 /// - Four tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, and
41 /// THREEBYTE3A_SYM) contain the hierarchy that the decoder traverses while
42 /// decoding an instruction. At the lowest level of this hierarchy are
43 /// instruction UIDs, 16-bit integers that can be used to uniquely identify
44 /// the instruction and correspond exactly to its position in the list of
45 /// CodeGenInstructions for the target.
46 /// - One table (INSTRUCTIONS_SYM) contains information about the operands of
47 /// each instruction and how to decode them.
49 /// During table generation, there may be conflicts between instructions that
50 /// occupy the same space in the decode tables. These conflicts are resolved as
51 /// follows in setTableFields() (X86DisassemblerTables.cpp)
53 /// - If the current context is the native context for one of the instructions
54 /// (that is, the attributes specified for it in the LLVM tables specify
55 /// precisely the current context), then it has priority.
56 /// - If the current context isn't native for either of the instructions, then
57 /// the higher-priority context wins (that is, the one that is more specific).
58 /// That hierarchy is determined by outranks() (X86DisassemblerTables.cpp)
59 /// - If the current context is native for both instructions, then the table
60 /// emitter reports a conflict and dies.
62 /// *** RESOLUTION FOR "Primary decode conflict"S
64 /// If two instructions collide, typically the solution is (in order of
67 /// (1) to filter out one of the instructions by editing filter()
68 /// (X86RecognizableInstr.cpp). This is the most common resolution, but
69 /// check the Intel manuals first to make sure that (2) and (3) are not the
71 /// (2) to fix the tables (X86.td and its subsidiaries) so the opcodes are
72 /// accurate. Sometimes they are not.
73 /// (3) to fix the tables to reflect the actual context (for example, required
74 /// prefixes), and possibly to add a new context by editing
75 /// lib/Target/X86/X86DisassemblerDecoderCommon.h. This is unlikely to be
78 /// DisassemblerEmitter.cpp contains the implementation for the emitter,
79 /// which simply pulls out instructions from the CodeGenTarget and pushes them
80 /// into X86DisassemblerTables.
81 /// X86DisassemblerTables.h contains the interface for the instruction tables,
82 /// which manage and emit the structures discussed above.
83 /// X86DisassemblerTables.cpp contains the implementation for the instruction
85 /// X86ModRMFilters.h contains filters that can be used to determine which
86 /// ModR/M values are valid for a particular instruction. These are used to
87 /// populate ModRMDecisions.
88 /// X86RecognizableInstr.h contains the interface for a single instruction,
89 /// which knows how to translate itself from a CodeGenInstruction and provide
90 /// the information necessary for integration into the tables.
91 /// X86RecognizableInstr.cpp contains the implementation for a single
94 void DisassemblerEmitter::run(raw_ostream &OS) {
97 OS << "/*===- TableGen'erated file "
98 << "---------------------------------------*- C -*-===*\n"
100 << " * " << Target.getName() << " Disassembler\n"
102 << " * Automatically generated file, do not edit!\n"
104 << " *===---------------------------------------------------------------"
107 // X86 uses a custom disassembler.
108 if (Target.getName() == "X86") {
109 DisassemblerTables Tables;
111 std::vector<const CodeGenInstruction*> numberedInstructions;
112 Target.getInstructionsByEnumValue(numberedInstructions);
114 for (unsigned i = 0, e = numberedInstructions.size(); i != e; ++i)
115 RecognizableInstr::processInstr(Tables, *numberedInstructions[i], i);
117 // FIXME: As long as we are using exceptions, might as well drop this to the
118 // actual conflict site.
119 if (Tables.hasConflicts())
120 throw TGError(Target.getTargetRecord()->getLoc(),
121 "Primary decode conflict");
127 throw TGError(Target.getTargetRecord()->getLoc(),
128 "Unable to generate disassembler for this target");