1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of each
11 // instruction in a format that the enhanced disassembler can use to tokenize
12 // and parse instructions.
14 //===----------------------------------------------------------------------===//
16 #include "EDEmitter.h"
18 #include "AsmWriterInst.h"
19 #include "CodeGenTarget.h"
21 #include "llvm/TableGen/Record.h"
22 #include "llvm/MC/EDInstInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/Format.h"
25 #include "llvm/Support/raw_ostream.h"
32 ///////////////////////////////////////////////////////////
33 // Support classes for emitting nested C data structures //
34 ///////////////////////////////////////////////////////////
41 std::vector<std::string> Entries;
43 EnumEmitter(const char *N) : Name(N) {
45 int addEntry(const char *e) {
46 Entries.push_back(std::string(e));
47 return Entries.size() - 1;
49 void emit(raw_ostream &o, unsigned int &i) {
50 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
53 unsigned int index = 0;
54 unsigned int numEntries = Entries.size();
55 for (index = 0; index < numEntries; ++index) {
56 o.indent(i) << Entries[index];
57 if (index < (numEntries - 1))
63 o.indent(i) << "};" << "\n";
66 void emitAsFlags(raw_ostream &o, unsigned int &i) {
67 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
70 unsigned int index = 0;
71 unsigned int numEntries = Entries.size();
72 unsigned int flag = 1;
73 for (index = 0; index < numEntries; ++index) {
74 o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
75 if (index < (numEntries - 1))
82 o.indent(i) << "};" << "\n";
86 class ConstantEmitter {
88 virtual ~ConstantEmitter() { }
89 virtual void emit(raw_ostream &o, unsigned int &i) = 0;
92 class LiteralConstantEmitter : public ConstantEmitter {
100 LiteralConstantEmitter(int number = 0) :
104 void set(const char *string) {
109 bool is(const char *string) {
110 return !strcmp(String, string);
112 void emit(raw_ostream &o, unsigned int &i) {
120 class CompoundConstantEmitter : public ConstantEmitter {
122 unsigned int Padding;
123 std::vector<ConstantEmitter *> Entries;
125 CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
127 CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
128 Entries.push_back(e);
132 ~CompoundConstantEmitter() {
133 while (Entries.size()) {
134 ConstantEmitter *entry = Entries.back();
139 void emit(raw_ostream &o, unsigned int &i) {
144 unsigned int numEntries = Entries.size();
146 unsigned int numToPrint;
149 if (numEntries > Padding) {
150 fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
151 llvm_unreachable("More entries than padding");
153 numToPrint = Padding;
155 numToPrint = numEntries;
158 for (index = 0; index < numToPrint; ++index) {
160 if (index < numEntries)
161 Entries[index]->emit(o, i);
165 if (index < (numToPrint - 1))
175 class FlagsConstantEmitter : public ConstantEmitter {
177 std::vector<std::string> Flags;
179 FlagsConstantEmitter() {
181 FlagsConstantEmitter &addEntry(const char *f) {
182 Flags.push_back(std::string(f));
185 void emit(raw_ostream &o, unsigned int &i) {
187 unsigned int numFlags = Flags.size();
191 for (index = 0; index < numFlags; ++index) {
192 o << Flags[index].c_str();
193 if (index < (numFlags - 1))
200 EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
203 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its
204 /// AsmWriterInst for the desired assembly syntax, giving an ordered list of
205 /// operands in the order they appear in the printed instruction. Then, for
206 /// each entry in that list, determines the index of the same operand in the
207 /// CodeGenInstruction, and emits the resulting mapping into an array, filling
208 /// in unused slots with -1.
210 /// @arg operandOrder - The array that will be populated with the operand
211 /// mapping. Each entry will contain -1 (invalid index
212 /// into the operands present in the AsmString) or a number
213 /// representing an index in the operand descriptor array.
214 /// @arg inst - The instruction to use when looking up the operands
215 /// @arg syntax - The syntax to use, according to LLVM's enumeration
216 void populateOperandOrder(CompoundConstantEmitter *operandOrder,
217 const CodeGenInstruction &inst,
219 unsigned int numArgs = 0;
221 AsmWriterInst awInst(inst, syntax, -1, -1);
223 std::vector<AsmWriterOperand>::iterator operandIterator;
225 for (operandIterator = awInst.Operands.begin();
226 operandIterator != awInst.Operands.end();
228 if (operandIterator->OperandType ==
229 AsmWriterOperand::isMachineInstrOperand) {
230 operandOrder->addEntry(
231 new LiteralConstantEmitter(operandIterator->CGIOpNo));
237 /////////////////////////////////////////////////////
238 // Support functions for handling X86 instructions //
239 /////////////////////////////////////////////////////
241 #define SET(flag) { type->set(flag); return 0; }
243 #define REG(str) if (name == str) SET("kOperandTypeRegister");
244 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
245 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
246 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
247 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
249 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is
250 /// actually its type) and translates it into an operand type
252 /// @arg flags - The type object to set
253 /// @arg name - The name of the operand
254 static int X86TypeFromOpName(LiteralConstantEmitter *type,
255 const std::string &name) {
322 PCR("i64i32imm_pcrel");
329 PCR("uncondbrtarget");
332 // all I, ARM mode only, conditional/unconditional
346 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
347 /// the appropriate flags to their descriptors
349 /// @operandFlags - A reference the array of operand flag objects
350 /// @inst - The instruction to use as a source of information
351 static void X86PopulateOperands(
352 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
353 const CodeGenInstruction &inst) {
354 if (!inst.TheDef->isSubClassOf("X86Inst"))
358 unsigned int numOperands = inst.Operands.size();
360 for (index = 0; index < numOperands; ++index) {
361 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
362 Record &rec = *operandInfo.Rec;
364 if (X86TypeFromOpName(operandTypes[index], rec.getName()) &&
365 !rec.isSubClassOf("PointerLikeRegClass")) {
366 errs() << "Operand type: " << rec.getName().c_str() << "\n";
367 errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
368 errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n";
369 llvm_unreachable("Unhandled type");
374 /// decorate1 - Decorates a named operand with a new flag
376 /// @operandFlags - The array of operand flag objects, which don't have names
377 /// @inst - The CodeGenInstruction, which provides a way to translate
378 /// between names and operand indices
379 /// @opName - The name of the operand
380 /// @flag - The name of the flag to add
381 static inline void decorate1(
382 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
383 const CodeGenInstruction &inst,
385 const char *opFlag) {
388 opIndex = inst.Operands.getOperandNamed(std::string(opName));
390 operandFlags[opIndex]->addEntry(opFlag);
393 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
395 #define MOV(source, target) { \
396 instType.set("kInstructionTypeMove"); \
397 DECORATE1(source, "kOperandFlagSource"); \
398 DECORATE1(target, "kOperandFlagTarget"); \
401 #define BRANCH(target) { \
402 instType.set("kInstructionTypeBranch"); \
403 DECORATE1(target, "kOperandFlagTarget"); \
406 #define PUSH(source) { \
407 instType.set("kInstructionTypePush"); \
408 DECORATE1(source, "kOperandFlagSource"); \
411 #define POP(target) { \
412 instType.set("kInstructionTypePop"); \
413 DECORATE1(target, "kOperandFlagTarget"); \
416 #define CALL(target) { \
417 instType.set("kInstructionTypeCall"); \
418 DECORATE1(target, "kOperandFlagTarget"); \
422 instType.set("kInstructionTypeReturn"); \
425 /// X86ExtractSemantics - Performs various checks on the name of an X86
426 /// instruction to determine what sort of an instruction it is and then adds
427 /// the appropriate flags to the instruction and its operands
429 /// @arg instType - A reference to the type for the instruction as a whole
430 /// @arg operandFlags - A reference to the array of operand flag object pointers
431 /// @arg inst - A reference to the original instruction
432 static void X86ExtractSemantics(
433 LiteralConstantEmitter &instType,
434 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
435 const CodeGenInstruction &inst) {
436 const std::string &name = inst.TheDef->getName();
438 if (name.find("MOV") != name.npos) {
439 if (name.find("MOV_V") != name.npos) {
440 // ignore (this is a pseudoinstruction)
441 } else if (name.find("MASK") != name.npos) {
442 // ignore (this is a masking move)
443 } else if (name.find("r0") != name.npos) {
444 // ignore (this is a pseudoinstruction)
445 } else if (name.find("PS") != name.npos ||
446 name.find("PD") != name.npos) {
447 // ignore (this is a shuffling move)
448 } else if (name.find("MOVS") != name.npos) {
449 // ignore (this is a string move)
450 } else if (name.find("_F") != name.npos) {
451 // TODO handle _F moves to ST(0)
452 } else if (name.find("a") != name.npos) {
453 // TODO handle moves to/from %ax
454 } else if (name.find("CMOV") != name.npos) {
456 } else if (name.find("PC") != name.npos) {
463 if (name.find("JMP") != name.npos ||
464 name.find("J") == 0) {
465 if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
472 if (name.find("PUSH") != name.npos) {
473 if (name.find("CS") != name.npos ||
474 name.find("DS") != name.npos ||
475 name.find("ES") != name.npos ||
476 name.find("FS") != name.npos ||
477 name.find("GS") != name.npos ||
478 name.find("SS") != name.npos) {
479 instType.set("kInstructionTypePush");
480 // TODO add support for fixed operands
481 } else if (name.find("F") != name.npos) {
482 // ignore (this pushes onto the FP stack)
483 } else if (name.find("A") != name.npos) {
484 // ignore (pushes all GP registoers onto the stack)
485 } else if (name[name.length() - 1] == 'm') {
487 } else if (name.find("i") != name.npos) {
494 if (name.find("POP") != name.npos) {
495 if (name.find("POPCNT") != name.npos) {
496 // ignore (not a real pop)
497 } else if (name.find("CS") != name.npos ||
498 name.find("DS") != name.npos ||
499 name.find("ES") != name.npos ||
500 name.find("FS") != name.npos ||
501 name.find("GS") != name.npos ||
502 name.find("SS") != name.npos) {
503 instType.set("kInstructionTypePop");
504 // TODO add support for fixed operands
505 } else if (name.find("F") != name.npos) {
506 // ignore (this pops from the FP stack)
507 } else if (name.find("A") != name.npos) {
508 // ignore (pushes all GP registoers onto the stack)
509 } else if (name[name.length() - 1] == 'm') {
516 if (name.find("CALL") != name.npos) {
517 if (name.find("ADJ") != name.npos) {
518 // ignore (not a call)
519 } else if (name.find("SYSCALL") != name.npos) {
520 // ignore (doesn't go anywhere we know about)
521 } else if (name.find("VMCALL") != name.npos) {
522 // ignore (rather different semantics than a regular call)
523 } else if (name.find("VMMCALL") != name.npos) {
524 // ignore (rather different semantics than a regular call)
525 } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
532 if (name.find("RET") != name.npos) {
544 /////////////////////////////////////////////////////
545 // Support functions for handling ARM instructions //
546 /////////////////////////////////////////////////////
548 #define SET(flag) { type->set(flag); return 0; }
550 #define REG(str) if (name == str) SET("kOperandTypeRegister");
551 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
553 #define MISC(str, type) if (name == str) SET(type);
555 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
556 /// actually its type) and translates it into an operand type
558 /// @arg type - The type object to set
559 /// @arg name - The name of the operand
560 static int ARMFlagFromOpName(LiteralConstantEmitter *type,
561 const std::string &name) {
580 REG("VecListDPairSpaced");
581 REG("VecListThreeD");
583 REG("VecListOneDAllLanes");
584 REG("VecListDPairAllLanes");
585 REG("VecListDPairSpacedAllLanes");
590 IMM("i32imm_hilo16");
591 IMM("bf_inv_mask_imm");
594 IMM("jtblock_operand");
598 IMM("coproc_option_imm");
601 IMM("cpinst_operand");
633 IMM("imm0_65535_expr");
637 IMM("jt2block_operand");
638 IMM("t_imm0_1020s4");
646 IMM("neon_vcvt_imm32");
653 IMM("postidx_imm8s4");
657 IMM("VectorIndex16");
658 IMM("VectorIndex32");
660 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
661 MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?
662 MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ?
663 MISC("t_bcctarget", "kOperandTypeARMBranchTarget"); // ?
664 MISC("t_cbtarget", "kOperandTypeARMBranchTarget"); // ?
665 MISC("bltarget", "kOperandTypeARMBranchTarget"); // ?
667 MISC("br_target", "kOperandTypeARMBranchTarget"); // ?
668 MISC("bl_target", "kOperandTypeARMBranchTarget"); // ?
669 MISC("blx_target", "kOperandTypeARMBranchTarget"); // ?
671 MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ?
672 MISC("t_blxtarget", "kOperandTypeARMBranchTarget"); // ?
673 MISC("so_reg_imm", "kOperandTypeARMSoRegReg"); // R, R, I
674 MISC("so_reg_reg", "kOperandTypeARMSoRegImm"); // R, R, I
675 MISC("shift_so_reg_reg", "kOperandTypeARMSoRegReg"); // R, R, I
676 MISC("shift_so_reg_imm", "kOperandTypeARMSoRegImm"); // R, R, I
677 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
678 MISC("so_imm", "kOperandTypeARMSoImm"); // I
679 MISC("rot_imm", "kOperandTypeARMRotImm"); // I
680 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I
681 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
682 MISC("pred", "kOperandTypeARMPredicate"); // I, R
683 MISC("it_pred", "kOperandTypeARMPredicate"); // I
684 MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I
685 MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I
686 MISC("postidx_reg", "kOperandTypeARMAddrMode3Offset"); // R, I
687 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
688 MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset"); // R, I
689 MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset"); // R, I
690 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
691 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
692 MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I
693 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
694 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
695 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
696 MISC("addrmode6dup", "kOperandTypeARMAddrMode6"); // R, R, I, I
697 MISC("addrmode6oneL32", "kOperandTypeARMAddrMode6"); // R, R, I, I
698 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
699 MISC("addr_offset_none", "kOperandTypeARMAddrMode7"); // R
700 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
701 MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList"); // I, R, ...
702 MISC("spr_reglist", "kOperandTypeARMSPRRegisterList"); // I, R, ...
703 MISC("it_mask", "kOperandTypeThumbITMask"); // I
704 MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg"); // R
705 MISC("t2addrmode_posimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
706 MISC("t2addrmode_negimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
707 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
708 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
709 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
710 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
711 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
712 MISC("t2addrmode_imm0_1020s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
713 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
715 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I
716 MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS1"); // R, R
717 MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS2"); // R, R
718 MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS4"); // R, R
719 MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS1"); // R, I
720 MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS2"); // R, I
721 MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS4"); // R, I
722 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
723 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
724 MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I
725 MISC("addrmode_tbb", "kOperandTypeThumbAddrModeRR"); // R, R
726 MISC("addrmode_tbh", "kOperandTypeThumbAddrModeRR"); // R, R
737 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
738 /// the appropriate flags to their descriptors
740 /// @operandFlags - A reference the array of operand flag objects
741 /// @inst - The instruction to use as a source of information
742 static void ARMPopulateOperands(
743 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
744 const CodeGenInstruction &inst) {
745 if (!inst.TheDef->isSubClassOf("InstARM") &&
746 !inst.TheDef->isSubClassOf("InstThumb"))
750 unsigned int numOperands = inst.Operands.size();
752 if (numOperands > EDIS_MAX_OPERANDS) {
753 errs() << "numOperands == " << numOperands << " > " <<
754 EDIS_MAX_OPERANDS << '\n';
755 llvm_unreachable("Too many operands");
758 for (index = 0; index < numOperands; ++index) {
759 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
760 Record &rec = *operandInfo.Rec;
762 if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
763 errs() << "Operand type: " << rec.getName() << '\n';
764 errs() << "Operand name: " << operandInfo.Name << '\n';
765 errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
766 throw("Unhandled type in EDEmitter");
771 #define BRANCH(target) { \
772 instType.set("kInstructionTypeBranch"); \
773 DECORATE1(target, "kOperandFlagTarget"); \
776 /// ARMExtractSemantics - Performs various checks on the name of an ARM
777 /// instruction to determine what sort of an instruction it is and then adds
778 /// the appropriate flags to the instruction and its operands
780 /// @arg instType - A reference to the type for the instruction as a whole
781 /// @arg operandTypes - A reference to the array of operand type object pointers
782 /// @arg operandFlags - A reference to the array of operand flag object pointers
783 /// @arg inst - A reference to the original instruction
784 static void ARMExtractSemantics(
785 LiteralConstantEmitter &instType,
786 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
787 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
788 const CodeGenInstruction &inst) {
789 const std::string &name = inst.TheDef->getName();
791 if (name == "tBcc" ||
800 if (name == "tBLr9" ||
801 name == "BLr9_pred" ||
802 name == "tBLXi_r9" ||
803 name == "tBLXr_r9" ||
810 opIndex = inst.Operands.getOperandNamed("func");
811 if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
812 operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
818 /// populateInstInfo - Fills an array of InstInfos with information about each
819 /// instruction in a target
821 /// @arg infoArray - The array of InstInfo objects to populate
822 /// @arg target - The CodeGenTarget to use as a source of instructions
823 static void populateInstInfo(CompoundConstantEmitter &infoArray,
824 CodeGenTarget &target) {
825 const std::vector<const CodeGenInstruction*> &numberedInstructions =
826 target.getInstructionsByEnumValue();
829 unsigned int numInstructions = numberedInstructions.size();
831 for (index = 0; index < numInstructions; ++index) {
832 const CodeGenInstruction& inst = *numberedInstructions[index];
834 CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
835 infoArray.addEntry(infoStruct);
837 LiteralConstantEmitter *instType = new LiteralConstantEmitter;
838 infoStruct->addEntry(instType);
840 LiteralConstantEmitter *numOperandsEmitter =
841 new LiteralConstantEmitter(inst.Operands.size());
842 infoStruct->addEntry(numOperandsEmitter);
844 CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
845 infoStruct->addEntry(operandTypeArray);
847 LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
849 CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
850 infoStruct->addEntry(operandFlagArray);
852 FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
854 for (unsigned operandIndex = 0;
855 operandIndex < EDIS_MAX_OPERANDS;
857 operandTypes[operandIndex] = new LiteralConstantEmitter;
858 operandTypeArray->addEntry(operandTypes[operandIndex]);
860 operandFlags[operandIndex] = new FlagsConstantEmitter;
861 operandFlagArray->addEntry(operandFlags[operandIndex]);
864 unsigned numSyntaxes = 0;
866 // We don't need to do anything for pseudo-instructions, as we'll never
867 // see them here. We'll only see real instructions.
868 // We still need to emit null initializers for everything.
869 if (!inst.isPseudo) {
870 if (target.getName() == "X86") {
871 X86PopulateOperands(operandTypes, inst);
872 X86ExtractSemantics(*instType, operandFlags, inst);
875 else if (target.getName() == "ARM") {
876 ARMPopulateOperands(operandTypes, inst);
877 ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
882 CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
884 infoStruct->addEntry(operandOrderArray);
886 for (unsigned syntaxIndex = 0;
887 syntaxIndex < EDIS_MAX_SYNTAXES;
889 CompoundConstantEmitter *operandOrder =
890 new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
892 operandOrderArray->addEntry(operandOrder);
894 if (syntaxIndex < numSyntaxes) {
895 populateOperandOrder(operandOrder, inst, syntaxIndex);
903 static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
904 EnumEmitter operandTypes("OperandTypes");
905 operandTypes.addEntry("kOperandTypeNone");
906 operandTypes.addEntry("kOperandTypeImmediate");
907 operandTypes.addEntry("kOperandTypeRegister");
908 operandTypes.addEntry("kOperandTypeX86Memory");
909 operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
910 operandTypes.addEntry("kOperandTypeX86PCRelative");
911 operandTypes.addEntry("kOperandTypeARMBranchTarget");
912 operandTypes.addEntry("kOperandTypeARMSoRegReg");
913 operandTypes.addEntry("kOperandTypeARMSoRegImm");
914 operandTypes.addEntry("kOperandTypeARMSoImm");
915 operandTypes.addEntry("kOperandTypeARMRotImm");
916 operandTypes.addEntry("kOperandTypeARMSoImm2Part");
917 operandTypes.addEntry("kOperandTypeARMPredicate");
918 operandTypes.addEntry("kOperandTypeAddrModeImm12");
919 operandTypes.addEntry("kOperandTypeLdStSOReg");
920 operandTypes.addEntry("kOperandTypeARMAddrMode2");
921 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
922 operandTypes.addEntry("kOperandTypeARMAddrMode3");
923 operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
924 operandTypes.addEntry("kOperandTypeARMLdStmMode");
925 operandTypes.addEntry("kOperandTypeARMAddrMode5");
926 operandTypes.addEntry("kOperandTypeARMAddrMode6");
927 operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
928 operandTypes.addEntry("kOperandTypeARMAddrMode7");
929 operandTypes.addEntry("kOperandTypeARMAddrModePC");
930 operandTypes.addEntry("kOperandTypeARMRegisterList");
931 operandTypes.addEntry("kOperandTypeARMDPRRegisterList");
932 operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
933 operandTypes.addEntry("kOperandTypeARMTBAddrMode");
934 operandTypes.addEntry("kOperandTypeThumbITMask");
935 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS1");
936 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS2");
937 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS4");
938 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS1");
939 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS2");
940 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS4");
941 operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
942 operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
943 operandTypes.addEntry("kOperandTypeThumbAddrModePC");
944 operandTypes.addEntry("kOperandTypeThumb2AddrModeReg");
945 operandTypes.addEntry("kOperandTypeThumb2SoReg");
946 operandTypes.addEntry("kOperandTypeThumb2SoImm");
947 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
948 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
949 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
950 operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
951 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
952 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
953 operandTypes.emit(o, i);
957 EnumEmitter operandFlags("OperandFlags");
958 operandFlags.addEntry("kOperandFlagSource");
959 operandFlags.addEntry("kOperandFlagTarget");
960 operandFlags.emitAsFlags(o, i);
964 EnumEmitter instructionTypes("InstructionTypes");
965 instructionTypes.addEntry("kInstructionTypeNone");
966 instructionTypes.addEntry("kInstructionTypeMove");
967 instructionTypes.addEntry("kInstructionTypeBranch");
968 instructionTypes.addEntry("kInstructionTypePush");
969 instructionTypes.addEntry("kInstructionTypePop");
970 instructionTypes.addEntry("kInstructionTypeCall");
971 instructionTypes.addEntry("kInstructionTypeReturn");
972 instructionTypes.emit(o, i);
977 void EDEmitter::run(raw_ostream &o) {
980 CompoundConstantEmitter infoArray;
981 CodeGenTarget target(Records);
983 populateInstInfo(infoArray, target);
985 emitCommonEnums(o, i);
987 o << "static const llvm::EDInstInfo instInfo" << target.getName() << "[] = ";
988 infoArray.emit(o, i);