1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of each
11 // instruction in a format that the enhanced disassembler can use to tokenize
12 // and parse instructions.
14 //===----------------------------------------------------------------------===//
16 #include "EDEmitter.h"
18 #include "AsmWriterInst.h"
19 #include "CodeGenTarget.h"
21 #include "llvm/TableGen/Record.h"
22 #include "llvm/MC/EDInstInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/Format.h"
25 #include "llvm/Support/raw_ostream.h"
32 ///////////////////////////////////////////////////////////
33 // Support classes for emitting nested C data structures //
34 ///////////////////////////////////////////////////////////
41 std::vector<std::string> Entries;
43 EnumEmitter(const char *N) : Name(N) {
45 int addEntry(const char *e) {
46 Entries.push_back(std::string(e));
47 return Entries.size() - 1;
49 void emit(raw_ostream &o, unsigned int &i) {
50 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
53 unsigned int index = 0;
54 unsigned int numEntries = Entries.size();
55 for (index = 0; index < numEntries; ++index) {
56 o.indent(i) << Entries[index];
57 if (index < (numEntries - 1))
63 o.indent(i) << "};" << "\n";
66 void emitAsFlags(raw_ostream &o, unsigned int &i) {
67 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
70 unsigned int index = 0;
71 unsigned int numEntries = Entries.size();
72 unsigned int flag = 1;
73 for (index = 0; index < numEntries; ++index) {
74 o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
75 if (index < (numEntries - 1))
82 o.indent(i) << "};" << "\n";
86 class ConstantEmitter {
88 virtual ~ConstantEmitter() { }
89 virtual void emit(raw_ostream &o, unsigned int &i) = 0;
92 class LiteralConstantEmitter : public ConstantEmitter {
100 LiteralConstantEmitter(int number = 0) :
104 void set(const char *string) {
109 bool is(const char *string) {
110 return !strcmp(String, string);
112 void emit(raw_ostream &o, unsigned int &i) {
120 class CompoundConstantEmitter : public ConstantEmitter {
122 unsigned int Padding;
123 std::vector<ConstantEmitter *> Entries;
125 CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
127 CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
128 Entries.push_back(e);
132 ~CompoundConstantEmitter() {
133 while (Entries.size()) {
134 ConstantEmitter *entry = Entries.back();
139 void emit(raw_ostream &o, unsigned int &i) {
144 unsigned int numEntries = Entries.size();
146 unsigned int numToPrint;
149 if (numEntries > Padding) {
150 fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
151 llvm_unreachable("More entries than padding");
153 numToPrint = Padding;
155 numToPrint = numEntries;
158 for (index = 0; index < numToPrint; ++index) {
160 if (index < numEntries)
161 Entries[index]->emit(o, i);
165 if (index < (numToPrint - 1))
175 class FlagsConstantEmitter : public ConstantEmitter {
177 std::vector<std::string> Flags;
179 FlagsConstantEmitter() {
181 FlagsConstantEmitter &addEntry(const char *f) {
182 Flags.push_back(std::string(f));
185 void emit(raw_ostream &o, unsigned int &i) {
187 unsigned int numFlags = Flags.size();
191 for (index = 0; index < numFlags; ++index) {
192 o << Flags[index].c_str();
193 if (index < (numFlags - 1))
200 EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
203 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its
204 /// AsmWriterInst for the desired assembly syntax, giving an ordered list of
205 /// operands in the order they appear in the printed instruction. Then, for
206 /// each entry in that list, determines the index of the same operand in the
207 /// CodeGenInstruction, and emits the resulting mapping into an array, filling
208 /// in unused slots with -1.
210 /// @arg operandOrder - The array that will be populated with the operand
211 /// mapping. Each entry will contain -1 (invalid index
212 /// into the operands present in the AsmString) or a number
213 /// representing an index in the operand descriptor array.
214 /// @arg inst - The instruction to use when looking up the operands
215 /// @arg syntax - The syntax to use, according to LLVM's enumeration
216 void populateOperandOrder(CompoundConstantEmitter *operandOrder,
217 const CodeGenInstruction &inst,
219 unsigned int numArgs = 0;
221 AsmWriterInst awInst(inst, syntax, -1, -1);
223 std::vector<AsmWriterOperand>::iterator operandIterator;
225 for (operandIterator = awInst.Operands.begin();
226 operandIterator != awInst.Operands.end();
228 if (operandIterator->OperandType ==
229 AsmWriterOperand::isMachineInstrOperand) {
230 operandOrder->addEntry(
231 new LiteralConstantEmitter(operandIterator->CGIOpNo));
237 /////////////////////////////////////////////////////
238 // Support functions for handling X86 instructions //
239 /////////////////////////////////////////////////////
241 #define SET(flag) { type->set(flag); return 0; }
243 #define REG(str) if (name == str) SET("kOperandTypeRegister");
244 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
245 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
246 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
247 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
249 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is
250 /// actually its type) and translates it into an operand type
252 /// @arg flags - The type object to set
253 /// @arg name - The name of the operand
254 static int X86TypeFromOpName(LiteralConstantEmitter *type,
255 const std::string &name) {
321 PCR("i64i32imm_pcrel");
328 PCR("uncondbrtarget");
331 // all I, ARM mode only, conditional/unconditional
345 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
346 /// the appropriate flags to their descriptors
348 /// @operandFlags - A reference the array of operand flag objects
349 /// @inst - The instruction to use as a source of information
350 static void X86PopulateOperands(
351 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
352 const CodeGenInstruction &inst) {
353 if (!inst.TheDef->isSubClassOf("X86Inst"))
357 unsigned int numOperands = inst.Operands.size();
359 for (index = 0; index < numOperands; ++index) {
360 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
361 Record &rec = *operandInfo.Rec;
363 if (X86TypeFromOpName(operandTypes[index], rec.getName()) &&
364 !rec.isSubClassOf("PointerLikeRegClass")) {
365 errs() << "Operand type: " << rec.getName().c_str() << "\n";
366 errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
367 errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n";
368 llvm_unreachable("Unhandled type");
373 /// decorate1 - Decorates a named operand with a new flag
375 /// @operandFlags - The array of operand flag objects, which don't have names
376 /// @inst - The CodeGenInstruction, which provides a way to translate
377 /// between names and operand indices
378 /// @opName - The name of the operand
379 /// @flag - The name of the flag to add
380 static inline void decorate1(
381 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
382 const CodeGenInstruction &inst,
384 const char *opFlag) {
387 opIndex = inst.Operands.getOperandNamed(std::string(opName));
389 operandFlags[opIndex]->addEntry(opFlag);
392 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
394 #define MOV(source, target) { \
395 instType.set("kInstructionTypeMove"); \
396 DECORATE1(source, "kOperandFlagSource"); \
397 DECORATE1(target, "kOperandFlagTarget"); \
400 #define BRANCH(target) { \
401 instType.set("kInstructionTypeBranch"); \
402 DECORATE1(target, "kOperandFlagTarget"); \
405 #define PUSH(source) { \
406 instType.set("kInstructionTypePush"); \
407 DECORATE1(source, "kOperandFlagSource"); \
410 #define POP(target) { \
411 instType.set("kInstructionTypePop"); \
412 DECORATE1(target, "kOperandFlagTarget"); \
415 #define CALL(target) { \
416 instType.set("kInstructionTypeCall"); \
417 DECORATE1(target, "kOperandFlagTarget"); \
421 instType.set("kInstructionTypeReturn"); \
424 /// X86ExtractSemantics - Performs various checks on the name of an X86
425 /// instruction to determine what sort of an instruction it is and then adds
426 /// the appropriate flags to the instruction and its operands
428 /// @arg instType - A reference to the type for the instruction as a whole
429 /// @arg operandFlags - A reference to the array of operand flag object pointers
430 /// @arg inst - A reference to the original instruction
431 static void X86ExtractSemantics(
432 LiteralConstantEmitter &instType,
433 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
434 const CodeGenInstruction &inst) {
435 const std::string &name = inst.TheDef->getName();
437 if (name.find("MOV") != name.npos) {
438 if (name.find("MOV_V") != name.npos) {
439 // ignore (this is a pseudoinstruction)
440 } else if (name.find("MASK") != name.npos) {
441 // ignore (this is a masking move)
442 } else if (name.find("r0") != name.npos) {
443 // ignore (this is a pseudoinstruction)
444 } else if (name.find("PS") != name.npos ||
445 name.find("PD") != name.npos) {
446 // ignore (this is a shuffling move)
447 } else if (name.find("MOVS") != name.npos) {
448 // ignore (this is a string move)
449 } else if (name.find("_F") != name.npos) {
450 // TODO handle _F moves to ST(0)
451 } else if (name.find("a") != name.npos) {
452 // TODO handle moves to/from %ax
453 } else if (name.find("CMOV") != name.npos) {
455 } else if (name.find("PC") != name.npos) {
462 if (name.find("JMP") != name.npos ||
463 name.find("J") == 0) {
464 if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
471 if (name.find("PUSH") != name.npos) {
472 if (name.find("CS") != name.npos ||
473 name.find("DS") != name.npos ||
474 name.find("ES") != name.npos ||
475 name.find("FS") != name.npos ||
476 name.find("GS") != name.npos ||
477 name.find("SS") != name.npos) {
478 instType.set("kInstructionTypePush");
479 // TODO add support for fixed operands
480 } else if (name.find("F") != name.npos) {
481 // ignore (this pushes onto the FP stack)
482 } else if (name.find("A") != name.npos) {
483 // ignore (pushes all GP registoers onto the stack)
484 } else if (name[name.length() - 1] == 'm') {
486 } else if (name.find("i") != name.npos) {
493 if (name.find("POP") != name.npos) {
494 if (name.find("POPCNT") != name.npos) {
495 // ignore (not a real pop)
496 } else if (name.find("CS") != name.npos ||
497 name.find("DS") != name.npos ||
498 name.find("ES") != name.npos ||
499 name.find("FS") != name.npos ||
500 name.find("GS") != name.npos ||
501 name.find("SS") != name.npos) {
502 instType.set("kInstructionTypePop");
503 // TODO add support for fixed operands
504 } else if (name.find("F") != name.npos) {
505 // ignore (this pops from the FP stack)
506 } else if (name.find("A") != name.npos) {
507 // ignore (pushes all GP registoers onto the stack)
508 } else if (name[name.length() - 1] == 'm') {
515 if (name.find("CALL") != name.npos) {
516 if (name.find("ADJ") != name.npos) {
517 // ignore (not a call)
518 } else if (name.find("SYSCALL") != name.npos) {
519 // ignore (doesn't go anywhere we know about)
520 } else if (name.find("VMCALL") != name.npos) {
521 // ignore (rather different semantics than a regular call)
522 } else if (name.find("VMMCALL") != name.npos) {
523 // ignore (rather different semantics than a regular call)
524 } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
531 if (name.find("RET") != name.npos) {
543 /////////////////////////////////////////////////////
544 // Support functions for handling ARM instructions //
545 /////////////////////////////////////////////////////
547 #define SET(flag) { type->set(flag); return 0; }
549 #define REG(str) if (name == str) SET("kOperandTypeRegister");
550 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
552 #define MISC(str, type) if (name == str) SET(type);
554 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
555 /// actually its type) and translates it into an operand type
557 /// @arg type - The type object to set
558 /// @arg name - The name of the operand
559 static int ARMFlagFromOpName(LiteralConstantEmitter *type,
560 const std::string &name) {
579 REG("VecListDPairSpaced");
580 REG("VecListThreeD");
582 REG("VecListOneDAllLanes");
583 REG("VecListDPairAllLanes");
584 REG("VecListDPairSpacedAllLanes");
589 IMM("i32imm_hilo16");
590 IMM("bf_inv_mask_imm");
593 IMM("jtblock_operand");
597 IMM("coproc_option_imm");
600 IMM("cpinst_operand");
632 IMM("imm0_65535_expr");
636 IMM("jt2block_operand");
637 IMM("t_imm0_1020s4");
645 IMM("neon_vcvt_imm32");
652 IMM("postidx_imm8s4");
656 IMM("VectorIndex16");
657 IMM("VectorIndex32");
659 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
660 MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?
661 MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ?
662 MISC("t_bcctarget", "kOperandTypeARMBranchTarget"); // ?
663 MISC("t_cbtarget", "kOperandTypeARMBranchTarget"); // ?
664 MISC("bltarget", "kOperandTypeARMBranchTarget"); // ?
666 MISC("br_target", "kOperandTypeARMBranchTarget"); // ?
667 MISC("bl_target", "kOperandTypeARMBranchTarget"); // ?
668 MISC("blx_target", "kOperandTypeARMBranchTarget"); // ?
670 MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ?
671 MISC("t_blxtarget", "kOperandTypeARMBranchTarget"); // ?
672 MISC("so_reg_imm", "kOperandTypeARMSoRegReg"); // R, R, I
673 MISC("so_reg_reg", "kOperandTypeARMSoRegImm"); // R, R, I
674 MISC("shift_so_reg_reg", "kOperandTypeARMSoRegReg"); // R, R, I
675 MISC("shift_so_reg_imm", "kOperandTypeARMSoRegImm"); // R, R, I
676 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
677 MISC("so_imm", "kOperandTypeARMSoImm"); // I
678 MISC("rot_imm", "kOperandTypeARMRotImm"); // I
679 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I
680 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
681 MISC("pred", "kOperandTypeARMPredicate"); // I, R
682 MISC("it_pred", "kOperandTypeARMPredicate"); // I
683 MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I
684 MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I
685 MISC("postidx_reg", "kOperandTypeARMAddrMode3Offset"); // R, I
686 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
687 MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset"); // R, I
688 MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset"); // R, I
689 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
690 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
691 MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I
692 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
693 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
694 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
695 MISC("addrmode6dup", "kOperandTypeARMAddrMode6"); // R, R, I, I
696 MISC("addrmode6oneL32", "kOperandTypeARMAddrMode6"); // R, R, I, I
697 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
698 MISC("addr_offset_none", "kOperandTypeARMAddrMode7"); // R
699 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
700 MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList"); // I, R, ...
701 MISC("spr_reglist", "kOperandTypeARMSPRRegisterList"); // I, R, ...
702 MISC("it_mask", "kOperandTypeThumbITMask"); // I
703 MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg"); // R
704 MISC("t2addrmode_posimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
705 MISC("t2addrmode_negimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
706 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
707 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
708 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
709 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
710 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
711 MISC("t2addrmode_imm0_1020s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
712 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
714 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I
715 MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS1"); // R, R
716 MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS2"); // R, R
717 MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS4"); // R, R
718 MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS1"); // R, I
719 MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS2"); // R, I
720 MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS4"); // R, I
721 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
722 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
723 MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I
724 MISC("addrmode_tbb", "kOperandTypeThumbAddrModeRR"); // R, R
725 MISC("addrmode_tbh", "kOperandTypeThumbAddrModeRR"); // R, R
736 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
737 /// the appropriate flags to their descriptors
739 /// @operandFlags - A reference the array of operand flag objects
740 /// @inst - The instruction to use as a source of information
741 static void ARMPopulateOperands(
742 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
743 const CodeGenInstruction &inst) {
744 if (!inst.TheDef->isSubClassOf("InstARM") &&
745 !inst.TheDef->isSubClassOf("InstThumb"))
749 unsigned int numOperands = inst.Operands.size();
751 if (numOperands > EDIS_MAX_OPERANDS) {
752 errs() << "numOperands == " << numOperands << " > " <<
753 EDIS_MAX_OPERANDS << '\n';
754 llvm_unreachable("Too many operands");
757 for (index = 0; index < numOperands; ++index) {
758 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
759 Record &rec = *operandInfo.Rec;
761 if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
762 errs() << "Operand type: " << rec.getName() << '\n';
763 errs() << "Operand name: " << operandInfo.Name << '\n';
764 errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
765 throw("Unhandled type in EDEmitter");
770 #define BRANCH(target) { \
771 instType.set("kInstructionTypeBranch"); \
772 DECORATE1(target, "kOperandFlagTarget"); \
775 /// ARMExtractSemantics - Performs various checks on the name of an ARM
776 /// instruction to determine what sort of an instruction it is and then adds
777 /// the appropriate flags to the instruction and its operands
779 /// @arg instType - A reference to the type for the instruction as a whole
780 /// @arg operandTypes - A reference to the array of operand type object pointers
781 /// @arg operandFlags - A reference to the array of operand flag object pointers
782 /// @arg inst - A reference to the original instruction
783 static void ARMExtractSemantics(
784 LiteralConstantEmitter &instType,
785 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
786 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
787 const CodeGenInstruction &inst) {
788 const std::string &name = inst.TheDef->getName();
790 if (name == "tBcc" ||
799 if (name == "tBLr9" ||
800 name == "BLr9_pred" ||
801 name == "tBLXi_r9" ||
802 name == "tBLXr_r9" ||
809 opIndex = inst.Operands.getOperandNamed("func");
810 if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
811 operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
817 /// populateInstInfo - Fills an array of InstInfos with information about each
818 /// instruction in a target
820 /// @arg infoArray - The array of InstInfo objects to populate
821 /// @arg target - The CodeGenTarget to use as a source of instructions
822 static void populateInstInfo(CompoundConstantEmitter &infoArray,
823 CodeGenTarget &target) {
824 const std::vector<const CodeGenInstruction*> &numberedInstructions =
825 target.getInstructionsByEnumValue();
828 unsigned int numInstructions = numberedInstructions.size();
830 for (index = 0; index < numInstructions; ++index) {
831 const CodeGenInstruction& inst = *numberedInstructions[index];
833 CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
834 infoArray.addEntry(infoStruct);
836 LiteralConstantEmitter *instType = new LiteralConstantEmitter;
837 infoStruct->addEntry(instType);
839 LiteralConstantEmitter *numOperandsEmitter =
840 new LiteralConstantEmitter(inst.Operands.size());
841 infoStruct->addEntry(numOperandsEmitter);
843 CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
844 infoStruct->addEntry(operandTypeArray);
846 LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
848 CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
849 infoStruct->addEntry(operandFlagArray);
851 FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
853 for (unsigned operandIndex = 0;
854 operandIndex < EDIS_MAX_OPERANDS;
856 operandTypes[operandIndex] = new LiteralConstantEmitter;
857 operandTypeArray->addEntry(operandTypes[operandIndex]);
859 operandFlags[operandIndex] = new FlagsConstantEmitter;
860 operandFlagArray->addEntry(operandFlags[operandIndex]);
863 unsigned numSyntaxes = 0;
865 // We don't need to do anything for pseudo-instructions, as we'll never
866 // see them here. We'll only see real instructions.
867 // We still need to emit null initializers for everything.
868 if (!inst.isPseudo) {
869 if (target.getName() == "X86") {
870 X86PopulateOperands(operandTypes, inst);
871 X86ExtractSemantics(*instType, operandFlags, inst);
874 else if (target.getName() == "ARM") {
875 ARMPopulateOperands(operandTypes, inst);
876 ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
881 CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
883 infoStruct->addEntry(operandOrderArray);
885 for (unsigned syntaxIndex = 0;
886 syntaxIndex < EDIS_MAX_SYNTAXES;
888 CompoundConstantEmitter *operandOrder =
889 new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
891 operandOrderArray->addEntry(operandOrder);
893 if (syntaxIndex < numSyntaxes) {
894 populateOperandOrder(operandOrder, inst, syntaxIndex);
902 static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
903 EnumEmitter operandTypes("OperandTypes");
904 operandTypes.addEntry("kOperandTypeNone");
905 operandTypes.addEntry("kOperandTypeImmediate");
906 operandTypes.addEntry("kOperandTypeRegister");
907 operandTypes.addEntry("kOperandTypeX86Memory");
908 operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
909 operandTypes.addEntry("kOperandTypeX86PCRelative");
910 operandTypes.addEntry("kOperandTypeARMBranchTarget");
911 operandTypes.addEntry("kOperandTypeARMSoRegReg");
912 operandTypes.addEntry("kOperandTypeARMSoRegImm");
913 operandTypes.addEntry("kOperandTypeARMSoImm");
914 operandTypes.addEntry("kOperandTypeARMRotImm");
915 operandTypes.addEntry("kOperandTypeARMSoImm2Part");
916 operandTypes.addEntry("kOperandTypeARMPredicate");
917 operandTypes.addEntry("kOperandTypeAddrModeImm12");
918 operandTypes.addEntry("kOperandTypeLdStSOReg");
919 operandTypes.addEntry("kOperandTypeARMAddrMode2");
920 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
921 operandTypes.addEntry("kOperandTypeARMAddrMode3");
922 operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
923 operandTypes.addEntry("kOperandTypeARMLdStmMode");
924 operandTypes.addEntry("kOperandTypeARMAddrMode5");
925 operandTypes.addEntry("kOperandTypeARMAddrMode6");
926 operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
927 operandTypes.addEntry("kOperandTypeARMAddrMode7");
928 operandTypes.addEntry("kOperandTypeARMAddrModePC");
929 operandTypes.addEntry("kOperandTypeARMRegisterList");
930 operandTypes.addEntry("kOperandTypeARMDPRRegisterList");
931 operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
932 operandTypes.addEntry("kOperandTypeARMTBAddrMode");
933 operandTypes.addEntry("kOperandTypeThumbITMask");
934 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS1");
935 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS2");
936 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS4");
937 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS1");
938 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS2");
939 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS4");
940 operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
941 operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
942 operandTypes.addEntry("kOperandTypeThumbAddrModePC");
943 operandTypes.addEntry("kOperandTypeThumb2AddrModeReg");
944 operandTypes.addEntry("kOperandTypeThumb2SoReg");
945 operandTypes.addEntry("kOperandTypeThumb2SoImm");
946 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
947 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
948 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
949 operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
950 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
951 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
952 operandTypes.emit(o, i);
956 EnumEmitter operandFlags("OperandFlags");
957 operandFlags.addEntry("kOperandFlagSource");
958 operandFlags.addEntry("kOperandFlagTarget");
959 operandFlags.emitAsFlags(o, i);
963 EnumEmitter instructionTypes("InstructionTypes");
964 instructionTypes.addEntry("kInstructionTypeNone");
965 instructionTypes.addEntry("kInstructionTypeMove");
966 instructionTypes.addEntry("kInstructionTypeBranch");
967 instructionTypes.addEntry("kInstructionTypePush");
968 instructionTypes.addEntry("kInstructionTypePop");
969 instructionTypes.addEntry("kInstructionTypeCall");
970 instructionTypes.addEntry("kInstructionTypeReturn");
971 instructionTypes.emit(o, i);
976 void EDEmitter::run(raw_ostream &o) {
979 CompoundConstantEmitter infoArray;
980 CodeGenTarget target(Records);
982 populateInstInfo(infoArray, target);
984 emitCommonEnums(o, i);
986 o << "static const llvm::EDInstInfo instInfo" << target.getName() << "[] = ";
987 infoArray.emit(o, i);