1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of each
11 // instruction in a format that the enhanced disassembler can use to tokenize
12 // and parse instructions.
14 //===----------------------------------------------------------------------===//
16 #include "AsmWriterInst.h"
17 #include "CodeGenTarget.h"
18 #include "llvm/MC/EDInstInfo.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/Format.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/TableGen/Error.h"
23 #include "llvm/TableGen/Record.h"
24 #include "llvm/TableGen/TableGenBackend.h"
30 // TODO: There's a suspiciously large amount of "table" data in this
31 // backend which should probably be in the TableGen file itself.
33 ///////////////////////////////////////////////////////////
34 // Support classes for emitting nested C data structures //
35 ///////////////////////////////////////////////////////////
37 // TODO: These classes are probably generally useful to other backends;
38 // add them to TableGen's "helper" API's.
44 std::vector<std::string> Entries;
46 EnumEmitter(const char *N) : Name(N) {
48 int addEntry(const char *e) {
49 Entries.push_back(std::string(e));
50 return Entries.size() - 1;
52 void emit(raw_ostream &o, unsigned int &i) {
53 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
56 unsigned int index = 0;
57 unsigned int numEntries = Entries.size();
58 for (index = 0; index < numEntries; ++index) {
59 o.indent(i) << Entries[index];
60 if (index < (numEntries - 1))
66 o.indent(i) << "};" << "\n";
69 void emitAsFlags(raw_ostream &o, unsigned int &i) {
70 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
73 unsigned int index = 0;
74 unsigned int numEntries = Entries.size();
75 unsigned int flag = 1;
76 for (index = 0; index < numEntries; ++index) {
77 o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
78 if (index < (numEntries - 1))
85 o.indent(i) << "};" << "\n";
88 } // End anonymous namespace
91 class ConstantEmitter {
93 virtual ~ConstantEmitter() { }
94 virtual void emit(raw_ostream &o, unsigned int &i) = 0;
96 } // End anonymous namespace
99 class LiteralConstantEmitter : public ConstantEmitter {
107 LiteralConstantEmitter(int number = 0) :
111 void set(const char *string) {
116 bool is(const char *string) {
117 return !strcmp(String, string);
119 void emit(raw_ostream &o, unsigned int &i) {
126 } // End anonymous namespace
129 class CompoundConstantEmitter : public ConstantEmitter {
131 unsigned int Padding;
132 std::vector<ConstantEmitter *> Entries;
134 CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
136 CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
137 Entries.push_back(e);
141 ~CompoundConstantEmitter() {
142 while (Entries.size()) {
143 ConstantEmitter *entry = Entries.back();
148 void emit(raw_ostream &o, unsigned int &i) {
153 unsigned int numEntries = Entries.size();
155 unsigned int numToPrint;
158 if (numEntries > Padding) {
159 fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
160 llvm_unreachable("More entries than padding");
162 numToPrint = Padding;
164 numToPrint = numEntries;
167 for (index = 0; index < numToPrint; ++index) {
169 if (index < numEntries)
170 Entries[index]->emit(o, i);
174 if (index < (numToPrint - 1))
183 } // End anonymous namespace
186 class FlagsConstantEmitter : public ConstantEmitter {
188 std::vector<std::string> Flags;
190 FlagsConstantEmitter() {
192 FlagsConstantEmitter &addEntry(const char *f) {
193 Flags.push_back(std::string(f));
196 void emit(raw_ostream &o, unsigned int &i) {
198 unsigned int numFlags = Flags.size();
202 for (index = 0; index < numFlags; ++index) {
203 o << Flags[index].c_str();
204 if (index < (numFlags - 1))
209 } // End anonymous namespace
211 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its
212 /// AsmWriterInst for the desired assembly syntax, giving an ordered list of
213 /// operands in the order they appear in the printed instruction. Then, for
214 /// each entry in that list, determines the index of the same operand in the
215 /// CodeGenInstruction, and emits the resulting mapping into an array, filling
216 /// in unused slots with -1.
218 /// @arg operandOrder - The array that will be populated with the operand
219 /// mapping. Each entry will contain -1 (invalid index
220 /// into the operands present in the AsmString) or a number
221 /// representing an index in the operand descriptor array.
222 /// @arg inst - The instruction to use when looking up the operands
223 /// @arg syntax - The syntax to use, according to LLVM's enumeration
224 static void populateOperandOrder(CompoundConstantEmitter *operandOrder,
225 const CodeGenInstruction &inst,
227 unsigned int numArgs = 0;
229 AsmWriterInst awInst(inst, syntax, -1, -1);
231 std::vector<AsmWriterOperand>::iterator operandIterator;
233 for (operandIterator = awInst.Operands.begin();
234 operandIterator != awInst.Operands.end();
236 if (operandIterator->OperandType ==
237 AsmWriterOperand::isMachineInstrOperand) {
238 operandOrder->addEntry(
239 new LiteralConstantEmitter(operandIterator->CGIOpNo));
245 /////////////////////////////////////////////////////
246 // Support functions for handling X86 instructions //
247 /////////////////////////////////////////////////////
249 #define SET(flag) { type->set(flag); return 0; }
251 #define REG(str) if (name == str) SET("kOperandTypeRegister");
252 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
253 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
254 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
255 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
257 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is
258 /// actually its type) and translates it into an operand type
260 /// @arg flags - The type object to set
261 /// @arg name - The name of the operand
262 static int X86TypeFromOpName(LiteralConstantEmitter *type,
263 const std::string &name) {
335 PCR("i64i32imm_pcrel");
342 PCR("uncondbrtarget");
345 // all I, ARM mode only, conditional/unconditional
359 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
360 /// the appropriate flags to their descriptors
362 /// \param operandTypes A reference the array of operand type objects
363 /// \param inst The instruction to use as a source of information
364 static void X86PopulateOperands(
365 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
366 const CodeGenInstruction &inst) {
367 if (!inst.TheDef->isSubClassOf("X86Inst"))
371 unsigned int numOperands = inst.Operands.size();
373 for (index = 0; index < numOperands; ++index) {
374 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
375 Record &rec = *operandInfo.Rec;
377 if (X86TypeFromOpName(operandTypes[index], rec.getName()) &&
378 !rec.isSubClassOf("PointerLikeRegClass")) {
379 errs() << "Operand type: " << rec.getName().c_str() << "\n";
380 errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
381 errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n";
382 llvm_unreachable("Unhandled type");
387 /// decorate1 - Decorates a named operand with a new flag
389 /// \param operandFlags The array of operand flag objects, which don't have
391 /// \param inst The CodeGenInstruction, which provides a way to
392 // translate between names and operand indices
393 /// \param opName The name of the operand
394 /// \param opFlag The name of the flag to add
395 static inline void decorate1(
396 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
397 const CodeGenInstruction &inst,
399 const char *opFlag) {
402 opIndex = inst.Operands.getOperandNamed(std::string(opName));
404 operandFlags[opIndex]->addEntry(opFlag);
407 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
409 #define MOV(source, target) { \
410 instType.set("kInstructionTypeMove"); \
411 DECORATE1(source, "kOperandFlagSource"); \
412 DECORATE1(target, "kOperandFlagTarget"); \
415 #define BRANCH(target) { \
416 instType.set("kInstructionTypeBranch"); \
417 DECORATE1(target, "kOperandFlagTarget"); \
420 #define PUSH(source) { \
421 instType.set("kInstructionTypePush"); \
422 DECORATE1(source, "kOperandFlagSource"); \
425 #define POP(target) { \
426 instType.set("kInstructionTypePop"); \
427 DECORATE1(target, "kOperandFlagTarget"); \
430 #define CALL(target) { \
431 instType.set("kInstructionTypeCall"); \
432 DECORATE1(target, "kOperandFlagTarget"); \
436 instType.set("kInstructionTypeReturn"); \
439 /// X86ExtractSemantics - Performs various checks on the name of an X86
440 /// instruction to determine what sort of an instruction it is and then adds
441 /// the appropriate flags to the instruction and its operands
443 /// \param instType A reference to the type for the instruction as a whole
444 /// \param operandFlags A reference to the array of operand flag object pointers
445 /// \param inst A reference to the original instruction
446 static void X86ExtractSemantics(
447 LiteralConstantEmitter &instType,
448 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
449 const CodeGenInstruction &inst) {
450 const std::string &name = inst.TheDef->getName();
452 if (name.find("MOV") != name.npos) {
453 if (name.find("MOV_V") != name.npos) {
454 // ignore (this is a pseudoinstruction)
455 } else if (name.find("MASK") != name.npos) {
456 // ignore (this is a masking move)
457 } else if (name.find("r0") != name.npos) {
458 // ignore (this is a pseudoinstruction)
459 } else if (name.find("PS") != name.npos ||
460 name.find("PD") != name.npos) {
461 // ignore (this is a shuffling move)
462 } else if (name.find("MOVS") != name.npos) {
463 // ignore (this is a string move)
464 } else if (name.find("_F") != name.npos) {
465 // TODO handle _F moves to ST(0)
466 } else if (name.find("a") != name.npos) {
467 // TODO handle moves to/from %ax
468 } else if (name.find("CMOV") != name.npos) {
470 } else if (name.find("PC") != name.npos) {
477 if (name.find("JMP") != name.npos ||
478 name.find("J") == 0) {
479 if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
486 if (name.find("PUSH") != name.npos) {
487 if (name.find("CS") != name.npos ||
488 name.find("DS") != name.npos ||
489 name.find("ES") != name.npos ||
490 name.find("FS") != name.npos ||
491 name.find("GS") != name.npos ||
492 name.find("SS") != name.npos) {
493 instType.set("kInstructionTypePush");
494 // TODO add support for fixed operands
495 } else if (name.find("F") != name.npos) {
496 // ignore (this pushes onto the FP stack)
497 } else if (name.find("A") != name.npos) {
498 // ignore (pushes all GP registoers onto the stack)
499 } else if (name[name.length() - 1] == 'm') {
501 } else if (name.find("i") != name.npos) {
508 if (name.find("POP") != name.npos) {
509 if (name.find("POPCNT") != name.npos) {
510 // ignore (not a real pop)
511 } else if (name.find("CS") != name.npos ||
512 name.find("DS") != name.npos ||
513 name.find("ES") != name.npos ||
514 name.find("FS") != name.npos ||
515 name.find("GS") != name.npos ||
516 name.find("SS") != name.npos) {
517 instType.set("kInstructionTypePop");
518 // TODO add support for fixed operands
519 } else if (name.find("F") != name.npos) {
520 // ignore (this pops from the FP stack)
521 } else if (name.find("A") != name.npos) {
522 // ignore (pushes all GP registoers onto the stack)
523 } else if (name[name.length() - 1] == 'm') {
530 if (name.find("CALL") != name.npos) {
531 if (name.find("ADJ") != name.npos) {
532 // ignore (not a call)
533 } else if (name.find("SYSCALL") != name.npos) {
534 // ignore (doesn't go anywhere we know about)
535 } else if (name.find("VMCALL") != name.npos) {
536 // ignore (rather different semantics than a regular call)
537 } else if (name.find("VMMCALL") != name.npos) {
538 // ignore (rather different semantics than a regular call)
539 } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
546 if (name.find("RET") != name.npos) {
558 /////////////////////////////////////////////////////
559 // Support functions for handling ARM instructions //
560 /////////////////////////////////////////////////////
562 #define SET(flag) { type->set(flag); return 0; }
564 #define REG(str) if (name == str) SET("kOperandTypeRegister");
565 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
567 #define MISC(str, type) if (name == str) SET(type);
569 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
570 /// actually its type) and translates it into an operand type
572 /// \param type The type object to set
573 /// \param name The name of the operand
574 static int ARMFlagFromOpName(LiteralConstantEmitter *type,
575 const std::string &name) {
595 REG("VecListDPairSpaced");
596 REG("VecListThreeD");
598 REG("VecListOneDAllLanes");
599 REG("VecListDPairAllLanes");
600 REG("VecListDPairSpacedAllLanes");
605 IMM("i32imm_hilo16");
606 IMM("bf_inv_mask_imm");
609 IMM("jtblock_operand");
614 IMM("coproc_option_imm");
617 IMM("cpinst_operand");
649 IMM("imm0_65535_expr");
653 IMM("jt2block_operand");
654 IMM("t_imm0_1020s4");
662 IMM("neon_vcvt_imm32");
669 IMM("postidx_imm8s4");
673 IMM("VectorIndex16");
674 IMM("VectorIndex32");
676 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
677 MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?
678 MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ?
679 MISC("t_bcctarget", "kOperandTypeARMBranchTarget"); // ?
680 MISC("t_cbtarget", "kOperandTypeARMBranchTarget"); // ?
681 MISC("bltarget", "kOperandTypeARMBranchTarget"); // ?
683 MISC("br_target", "kOperandTypeARMBranchTarget"); // ?
684 MISC("bl_target", "kOperandTypeARMBranchTarget"); // ?
685 MISC("blx_target", "kOperandTypeARMBranchTarget"); // ?
687 MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ?
688 MISC("t_blxtarget", "kOperandTypeARMBranchTarget"); // ?
689 MISC("so_reg_imm", "kOperandTypeARMSoRegReg"); // R, R, I
690 MISC("so_reg_reg", "kOperandTypeARMSoRegImm"); // R, R, I
691 MISC("shift_so_reg_reg", "kOperandTypeARMSoRegReg"); // R, R, I
692 MISC("shift_so_reg_imm", "kOperandTypeARMSoRegImm"); // R, R, I
693 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
694 MISC("so_imm", "kOperandTypeARMSoImm"); // I
695 MISC("rot_imm", "kOperandTypeARMRotImm"); // I
696 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I
697 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
698 MISC("pred", "kOperandTypeARMPredicate"); // I, R
699 MISC("it_pred", "kOperandTypeARMPredicate"); // I
700 MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I
701 MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I
702 MISC("postidx_reg", "kOperandTypeARMAddrMode3Offset"); // R, I
703 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
704 MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset"); // R, I
705 MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset"); // R, I
706 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
707 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
708 MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I
709 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
710 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
711 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
712 MISC("addrmode6dup", "kOperandTypeARMAddrMode6"); // R, R, I, I
713 MISC("addrmode6oneL32", "kOperandTypeARMAddrMode6"); // R, R, I, I
714 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
715 MISC("addr_offset_none", "kOperandTypeARMAddrMode7"); // R
716 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
717 MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList"); // I, R, ...
718 MISC("spr_reglist", "kOperandTypeARMSPRRegisterList"); // I, R, ...
719 MISC("it_mask", "kOperandTypeThumbITMask"); // I
720 MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg"); // R
721 MISC("t2addrmode_posimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
722 MISC("t2addrmode_negimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
723 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
724 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
725 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
726 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
727 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
728 MISC("t2addrmode_imm0_1020s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
729 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
731 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I
732 MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS1"); // R, R
733 MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS2"); // R, R
734 MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS4"); // R, R
735 MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS1"); // R, I
736 MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS2"); // R, I
737 MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS4"); // R, I
738 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
739 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
740 MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I
741 MISC("addrmode_tbb", "kOperandTypeThumbAddrModeRR"); // R, R
742 MISC("addrmode_tbh", "kOperandTypeThumbAddrModeRR"); // R, R
753 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
754 /// the appropriate flags to their descriptors
756 /// \param operandTypes A reference the array of operand type objects
757 /// \param inst The instruction to use as a source of information
758 static void ARMPopulateOperands(
759 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
760 const CodeGenInstruction &inst) {
761 if (!inst.TheDef->isSubClassOf("InstARM") &&
762 !inst.TheDef->isSubClassOf("InstThumb"))
766 unsigned int numOperands = inst.Operands.size();
768 if (numOperands > EDIS_MAX_OPERANDS) {
769 errs() << "numOperands == " << numOperands << " > " <<
770 EDIS_MAX_OPERANDS << '\n';
771 llvm_unreachable("Too many operands");
774 for (index = 0; index < numOperands; ++index) {
775 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
776 Record &rec = *operandInfo.Rec;
778 if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
779 errs() << "Operand type: " << rec.getName() << '\n';
780 errs() << "Operand name: " << operandInfo.Name << '\n';
781 errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
782 PrintFatalError("Unhandled type in EDEmitter");
787 #define BRANCH(target) { \
788 instType.set("kInstructionTypeBranch"); \
789 DECORATE1(target, "kOperandFlagTarget"); \
792 /// ARMExtractSemantics - Performs various checks on the name of an ARM
793 /// instruction to determine what sort of an instruction it is and then adds
794 /// the appropriate flags to the instruction and its operands
796 /// \param instType A reference to the type for the instruction as a whole
797 /// \param operandTypes A reference to the array of operand type object pointers
798 /// \param operandFlags A reference to the array of operand flag object pointers
799 /// \param inst A reference to the original instruction
800 static void ARMExtractSemantics(
801 LiteralConstantEmitter &instType,
802 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
803 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
804 const CodeGenInstruction &inst) {
805 const std::string &name = inst.TheDef->getName();
807 if (name == "tBcc" ||
816 if (name == "tBLr9" ||
817 name == "BLr9_pred" ||
818 name == "tBLXi_r9" ||
819 name == "tBLXr_r9" ||
826 opIndex = inst.Operands.getOperandNamed("func");
827 if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
828 operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
834 /// populateInstInfo - Fills an array of InstInfos with information about each
835 /// instruction in a target
837 /// \param infoArray The array of InstInfo objects to populate
838 /// \param target The CodeGenTarget to use as a source of instructions
839 static void populateInstInfo(CompoundConstantEmitter &infoArray,
840 CodeGenTarget &target) {
841 const std::vector<const CodeGenInstruction*> &numberedInstructions =
842 target.getInstructionsByEnumValue();
845 unsigned int numInstructions = numberedInstructions.size();
847 for (index = 0; index < numInstructions; ++index) {
848 const CodeGenInstruction& inst = *numberedInstructions[index];
850 CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
851 infoArray.addEntry(infoStruct);
853 LiteralConstantEmitter *instType = new LiteralConstantEmitter;
854 infoStruct->addEntry(instType);
856 LiteralConstantEmitter *numOperandsEmitter =
857 new LiteralConstantEmitter(inst.Operands.size());
858 infoStruct->addEntry(numOperandsEmitter);
860 CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
861 infoStruct->addEntry(operandTypeArray);
863 LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
865 CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
866 infoStruct->addEntry(operandFlagArray);
868 FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
870 for (unsigned operandIndex = 0;
871 operandIndex < EDIS_MAX_OPERANDS;
873 operandTypes[operandIndex] = new LiteralConstantEmitter;
874 operandTypeArray->addEntry(operandTypes[operandIndex]);
876 operandFlags[operandIndex] = new FlagsConstantEmitter;
877 operandFlagArray->addEntry(operandFlags[operandIndex]);
880 unsigned numSyntaxes = 0;
882 // We don't need to do anything for pseudo-instructions, as we'll never
883 // see them here. We'll only see real instructions.
884 // We still need to emit null initializers for everything.
885 if (!inst.isPseudo) {
886 if (target.getName() == "X86") {
887 X86PopulateOperands(operandTypes, inst);
888 X86ExtractSemantics(*instType, operandFlags, inst);
891 else if (target.getName() == "ARM") {
892 ARMPopulateOperands(operandTypes, inst);
893 ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
898 CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
900 infoStruct->addEntry(operandOrderArray);
902 for (unsigned syntaxIndex = 0;
903 syntaxIndex < EDIS_MAX_SYNTAXES;
905 CompoundConstantEmitter *operandOrder =
906 new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
908 operandOrderArray->addEntry(operandOrder);
910 if (syntaxIndex < numSyntaxes) {
911 populateOperandOrder(operandOrder, inst, syntaxIndex);
919 static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
920 EnumEmitter operandTypes("OperandTypes");
921 operandTypes.addEntry("kOperandTypeNone");
922 operandTypes.addEntry("kOperandTypeImmediate");
923 operandTypes.addEntry("kOperandTypeRegister");
924 operandTypes.addEntry("kOperandTypeX86Memory");
925 operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
926 operandTypes.addEntry("kOperandTypeX86PCRelative");
927 operandTypes.addEntry("kOperandTypeARMBranchTarget");
928 operandTypes.addEntry("kOperandTypeARMSoRegReg");
929 operandTypes.addEntry("kOperandTypeARMSoRegImm");
930 operandTypes.addEntry("kOperandTypeARMSoImm");
931 operandTypes.addEntry("kOperandTypeARMRotImm");
932 operandTypes.addEntry("kOperandTypeARMSoImm2Part");
933 operandTypes.addEntry("kOperandTypeARMPredicate");
934 operandTypes.addEntry("kOperandTypeAddrModeImm12");
935 operandTypes.addEntry("kOperandTypeLdStSOReg");
936 operandTypes.addEntry("kOperandTypeARMAddrMode2");
937 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
938 operandTypes.addEntry("kOperandTypeARMAddrMode3");
939 operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
940 operandTypes.addEntry("kOperandTypeARMLdStmMode");
941 operandTypes.addEntry("kOperandTypeARMAddrMode5");
942 operandTypes.addEntry("kOperandTypeARMAddrMode6");
943 operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
944 operandTypes.addEntry("kOperandTypeARMAddrMode7");
945 operandTypes.addEntry("kOperandTypeARMAddrModePC");
946 operandTypes.addEntry("kOperandTypeARMRegisterList");
947 operandTypes.addEntry("kOperandTypeARMDPRRegisterList");
948 operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
949 operandTypes.addEntry("kOperandTypeARMTBAddrMode");
950 operandTypes.addEntry("kOperandTypeThumbITMask");
951 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS1");
952 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS2");
953 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS4");
954 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS1");
955 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS2");
956 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS4");
957 operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
958 operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
959 operandTypes.addEntry("kOperandTypeThumbAddrModePC");
960 operandTypes.addEntry("kOperandTypeThumb2AddrModeReg");
961 operandTypes.addEntry("kOperandTypeThumb2SoReg");
962 operandTypes.addEntry("kOperandTypeThumb2SoImm");
963 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
964 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
965 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
966 operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
967 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
968 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
969 operandTypes.emit(o, i);
973 EnumEmitter operandFlags("OperandFlags");
974 operandFlags.addEntry("kOperandFlagSource");
975 operandFlags.addEntry("kOperandFlagTarget");
976 operandFlags.emitAsFlags(o, i);
980 EnumEmitter instructionTypes("InstructionTypes");
981 instructionTypes.addEntry("kInstructionTypeNone");
982 instructionTypes.addEntry("kInstructionTypeMove");
983 instructionTypes.addEntry("kInstructionTypeBranch");
984 instructionTypes.addEntry("kInstructionTypePush");
985 instructionTypes.addEntry("kInstructionTypePop");
986 instructionTypes.addEntry("kInstructionTypeCall");
987 instructionTypes.addEntry("kInstructionTypeReturn");
988 instructionTypes.emit(o, i);
995 void EmitEnhancedDisassemblerInfo(RecordKeeper &RK, raw_ostream &OS) {
996 emitSourceFileHeader("Enhanced Disassembler Info", OS);
999 CompoundConstantEmitter infoArray;
1000 CodeGenTarget target(RK);
1002 populateInstInfo(infoArray, target);
1004 emitCommonEnums(OS, i);
1006 OS << "static const llvm::EDInstInfo instInfo"
1007 << target.getName() << "[] = ";
1008 infoArray.emit(OS, i);
1012 } // End llvm namespace