1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of each
11 // instruction in a format that the enhanced disassembler can use to tokenize
12 // and parse instructions.
14 //===----------------------------------------------------------------------===//
16 #include "EDEmitter.h"
18 #include "AsmWriterInst.h"
19 #include "CodeGenTarget.h"
22 #include "llvm/MC/EDInstInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/Format.h"
25 #include "llvm/Support/raw_ostream.h"
33 ///////////////////////////////////////////////////////////
34 // Support classes for emitting nested C data structures //
35 ///////////////////////////////////////////////////////////
42 std::vector<std::string> Entries;
44 EnumEmitter(const char *N) : Name(N) {
46 int addEntry(const char *e) {
47 Entries.push_back(std::string(e));
48 return Entries.size() - 1;
50 void emit(raw_ostream &o, unsigned int &i) {
51 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
54 unsigned int index = 0;
55 unsigned int numEntries = Entries.size();
56 for (index = 0; index < numEntries; ++index) {
57 o.indent(i) << Entries[index];
58 if (index < (numEntries - 1))
64 o.indent(i) << "};" << "\n";
67 void emitAsFlags(raw_ostream &o, unsigned int &i) {
68 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
71 unsigned int index = 0;
72 unsigned int numEntries = Entries.size();
73 unsigned int flag = 1;
74 for (index = 0; index < numEntries; ++index) {
75 o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
76 if (index < (numEntries - 1))
83 o.indent(i) << "};" << "\n";
87 class ConstantEmitter {
89 virtual ~ConstantEmitter() { }
90 virtual void emit(raw_ostream &o, unsigned int &i) = 0;
93 class LiteralConstantEmitter : public ConstantEmitter {
101 LiteralConstantEmitter(int number = 0) :
105 void set(const char *string) {
110 bool is(const char *string) {
111 return !strcmp(String, string);
113 void emit(raw_ostream &o, unsigned int &i) {
121 class CompoundConstantEmitter : public ConstantEmitter {
123 unsigned int Padding;
124 std::vector<ConstantEmitter *> Entries;
126 CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
128 CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
129 Entries.push_back(e);
133 ~CompoundConstantEmitter() {
134 while (Entries.size()) {
135 ConstantEmitter *entry = Entries.back();
140 void emit(raw_ostream &o, unsigned int &i) {
145 unsigned int numEntries = Entries.size();
147 unsigned int numToPrint;
150 if (numEntries > Padding) {
151 fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
152 llvm_unreachable("More entries than padding");
154 numToPrint = Padding;
156 numToPrint = numEntries;
159 for (index = 0; index < numToPrint; ++index) {
161 if (index < numEntries)
162 Entries[index]->emit(o, i);
166 if (index < (numToPrint - 1))
176 class FlagsConstantEmitter : public ConstantEmitter {
178 std::vector<std::string> Flags;
180 FlagsConstantEmitter() {
182 FlagsConstantEmitter &addEntry(const char *f) {
183 Flags.push_back(std::string(f));
186 void emit(raw_ostream &o, unsigned int &i) {
188 unsigned int numFlags = Flags.size();
192 for (index = 0; index < numFlags; ++index) {
193 o << Flags[index].c_str();
194 if (index < (numFlags - 1))
201 EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
204 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its
205 /// AsmWriterInst for the desired assembly syntax, giving an ordered list of
206 /// operands in the order they appear in the printed instruction. Then, for
207 /// each entry in that list, determines the index of the same operand in the
208 /// CodeGenInstruction, and emits the resulting mapping into an array, filling
209 /// in unused slots with -1.
211 /// @arg operandOrder - The array that will be populated with the operand
212 /// mapping. Each entry will contain -1 (invalid index
213 /// into the operands present in the AsmString) or a number
214 /// representing an index in the operand descriptor array.
215 /// @arg inst - The instruction to use when looking up the operands
216 /// @arg syntax - The syntax to use, according to LLVM's enumeration
217 void populateOperandOrder(CompoundConstantEmitter *operandOrder,
218 const CodeGenInstruction &inst,
220 unsigned int numArgs = 0;
222 AsmWriterInst awInst(inst, syntax, -1, -1);
224 std::vector<AsmWriterOperand>::iterator operandIterator;
226 for (operandIterator = awInst.Operands.begin();
227 operandIterator != awInst.Operands.end();
229 if (operandIterator->OperandType ==
230 AsmWriterOperand::isMachineInstrOperand) {
231 operandOrder->addEntry(
232 new LiteralConstantEmitter(operandIterator->CGIOpNo));
238 /////////////////////////////////////////////////////
239 // Support functions for handling X86 instructions //
240 /////////////////////////////////////////////////////
242 #define SET(flag) { type->set(flag); return 0; }
244 #define REG(str) if (name == str) SET("kOperandTypeRegister");
245 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
246 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
247 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
248 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
250 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is
251 /// actually its type) and translates it into an operand type
253 /// @arg flags - The type object to set
254 /// @arg name - The name of the operand
255 static int X86TypeFromOpName(LiteralConstantEmitter *type,
256 const std::string &name) {
318 PCR("i64i32imm_pcrel");
325 PCR("uncondbrtarget");
339 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
340 /// the appropriate flags to their descriptors
342 /// @operandFlags - A reference the array of operand flag objects
343 /// @inst - The instruction to use as a source of information
344 static void X86PopulateOperands(
345 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
346 const CodeGenInstruction &inst) {
347 if (!inst.TheDef->isSubClassOf("X86Inst"))
351 unsigned int numOperands = inst.Operands.size();
353 for (index = 0; index < numOperands; ++index) {
354 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
355 Record &rec = *operandInfo.Rec;
357 if (X86TypeFromOpName(operandTypes[index], rec.getName())) {
358 errs() << "Operand type: " << rec.getName().c_str() << "\n";
359 errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
360 errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n";
361 llvm_unreachable("Unhandled type");
366 /// decorate1 - Decorates a named operand with a new flag
368 /// @operandFlags - The array of operand flag objects, which don't have names
369 /// @inst - The CodeGenInstruction, which provides a way to translate
370 /// between names and operand indices
371 /// @opName - The name of the operand
372 /// @flag - The name of the flag to add
373 static inline void decorate1(
374 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
375 const CodeGenInstruction &inst,
377 const char *opFlag) {
380 opIndex = inst.Operands.getOperandNamed(std::string(opName));
382 operandFlags[opIndex]->addEntry(opFlag);
385 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
387 #define MOV(source, target) { \
388 instType.set("kInstructionTypeMove"); \
389 DECORATE1(source, "kOperandFlagSource"); \
390 DECORATE1(target, "kOperandFlagTarget"); \
393 #define BRANCH(target) { \
394 instType.set("kInstructionTypeBranch"); \
395 DECORATE1(target, "kOperandFlagTarget"); \
398 #define PUSH(source) { \
399 instType.set("kInstructionTypePush"); \
400 DECORATE1(source, "kOperandFlagSource"); \
403 #define POP(target) { \
404 instType.set("kInstructionTypePop"); \
405 DECORATE1(target, "kOperandFlagTarget"); \
408 #define CALL(target) { \
409 instType.set("kInstructionTypeCall"); \
410 DECORATE1(target, "kOperandFlagTarget"); \
414 instType.set("kInstructionTypeReturn"); \
417 /// X86ExtractSemantics - Performs various checks on the name of an X86
418 /// instruction to determine what sort of an instruction it is and then adds
419 /// the appropriate flags to the instruction and its operands
421 /// @arg instType - A reference to the type for the instruction as a whole
422 /// @arg operandFlags - A reference to the array of operand flag object pointers
423 /// @arg inst - A reference to the original instruction
424 static void X86ExtractSemantics(
425 LiteralConstantEmitter &instType,
426 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
427 const CodeGenInstruction &inst) {
428 const std::string &name = inst.TheDef->getName();
430 if (name.find("MOV") != name.npos) {
431 if (name.find("MOV_V") != name.npos) {
432 // ignore (this is a pseudoinstruction)
433 } else if (name.find("MASK") != name.npos) {
434 // ignore (this is a masking move)
435 } else if (name.find("r0") != name.npos) {
436 // ignore (this is a pseudoinstruction)
437 } else if (name.find("PS") != name.npos ||
438 name.find("PD") != name.npos) {
439 // ignore (this is a shuffling move)
440 } else if (name.find("MOVS") != name.npos) {
441 // ignore (this is a string move)
442 } else if (name.find("_F") != name.npos) {
443 // TODO handle _F moves to ST(0)
444 } else if (name.find("a") != name.npos) {
445 // TODO handle moves to/from %ax
446 } else if (name.find("CMOV") != name.npos) {
448 } else if (name.find("PC") != name.npos) {
455 if (name.find("JMP") != name.npos ||
456 name.find("J") == 0) {
457 if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
464 if (name.find("PUSH") != name.npos) {
465 if (name.find("CS") != name.npos ||
466 name.find("DS") != name.npos ||
467 name.find("ES") != name.npos ||
468 name.find("FS") != name.npos ||
469 name.find("GS") != name.npos ||
470 name.find("SS") != name.npos) {
471 instType.set("kInstructionTypePush");
472 // TODO add support for fixed operands
473 } else if (name.find("F") != name.npos) {
474 // ignore (this pushes onto the FP stack)
475 } else if (name.find("A") != name.npos) {
476 // ignore (pushes all GP registoers onto the stack)
477 } else if (name[name.length() - 1] == 'm') {
479 } else if (name.find("i") != name.npos) {
486 if (name.find("POP") != name.npos) {
487 if (name.find("POPCNT") != name.npos) {
488 // ignore (not a real pop)
489 } else if (name.find("CS") != name.npos ||
490 name.find("DS") != name.npos ||
491 name.find("ES") != name.npos ||
492 name.find("FS") != name.npos ||
493 name.find("GS") != name.npos ||
494 name.find("SS") != name.npos) {
495 instType.set("kInstructionTypePop");
496 // TODO add support for fixed operands
497 } else if (name.find("F") != name.npos) {
498 // ignore (this pops from the FP stack)
499 } else if (name.find("A") != name.npos) {
500 // ignore (pushes all GP registoers onto the stack)
501 } else if (name[name.length() - 1] == 'm') {
508 if (name.find("CALL") != name.npos) {
509 if (name.find("ADJ") != name.npos) {
510 // ignore (not a call)
511 } else if (name.find("SYSCALL") != name.npos) {
512 // ignore (doesn't go anywhere we know about)
513 } else if (name.find("VMCALL") != name.npos) {
514 // ignore (rather different semantics than a regular call)
515 } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
522 if (name.find("RET") != name.npos) {
534 /////////////////////////////////////////////////////
535 // Support functions for handling ARM instructions //
536 /////////////////////////////////////////////////////
538 #define SET(flag) { type->set(flag); return 0; }
540 #define REG(str) if (name == str) SET("kOperandTypeRegister");
541 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
543 #define MISC(str, type) if (name == str) SET(type);
545 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
546 /// actually its type) and translates it into an operand type
548 /// @arg type - The type object to set
549 /// @arg name - The name of the operand
550 static int ARMFlagFromOpName(LiteralConstantEmitter *type,
551 const std::string &name) {
568 IMM("bf_inv_mask_imm");
569 IMM("jtblock_operand");
571 IMM("cpinst_operand");
583 IMM("jt2block_operand");
590 IMM("neon_vcvt_imm32");
592 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
593 MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?
594 MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ?
595 MISC("t_bcctarget", "kOperandTypeARMBranchTarget"); // ?
596 MISC("t_cbtarget", "kOperandTypeARMBranchTarget"); // ?
597 MISC("bltarget", "kOperandTypeARMBranchTarget"); // ?
598 MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ?
599 MISC("t_blxtarget", "kOperandTypeARMBranchTarget"); // ?
600 MISC("so_reg", "kOperandTypeARMSoReg"); // R, R, I
601 MISC("shift_so_reg", "kOperandTypeARMSoReg"); // R, R, I
602 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
603 MISC("so_imm", "kOperandTypeARMSoImm"); // I
604 MISC("rot_imm", "kOperandTypeARMRotImm"); // I
605 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I
606 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
607 MISC("pred", "kOperandTypeARMPredicate"); // I, R
608 MISC("it_pred", "kOperandTypeARMPredicate"); // I
609 MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I
610 MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I
611 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
612 MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I
613 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
614 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
615 MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I
616 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
617 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
618 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
619 MISC("addrmode6dup", "kOperandTypeARMAddrMode6"); // R, R, I, I
620 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
621 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
622 MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList"); // I, R, ...
623 MISC("spr_reglist", "kOperandTypeARMSPRRegisterList"); // I, R, ...
624 MISC("it_mask", "kOperandTypeThumbITMask"); // I
625 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
626 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
627 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
628 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
629 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
630 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
632 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I
633 MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS"); // R, R
634 MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS"); // R, R
635 MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS"); // R, R
636 MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS"); // R, I
637 MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS"); // R, I
638 MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS"); // R, I
639 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
640 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
641 MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I
657 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
658 /// the appropriate flags to their descriptors
660 /// @operandFlags - A reference the array of operand flag objects
661 /// @inst - The instruction to use as a source of information
662 static void ARMPopulateOperands(
663 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
664 const CodeGenInstruction &inst) {
665 if (!inst.TheDef->isSubClassOf("InstARM") &&
666 !inst.TheDef->isSubClassOf("InstThumb"))
670 unsigned int numOperands = inst.Operands.size();
672 if (numOperands > EDIS_MAX_OPERANDS) {
673 errs() << "numOperands == " << numOperands << " > " <<
674 EDIS_MAX_OPERANDS << '\n';
675 llvm_unreachable("Too many operands");
678 for (index = 0; index < numOperands; ++index) {
679 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
680 Record &rec = *operandInfo.Rec;
682 if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
683 errs() << "Operand type: " << rec.getName() << '\n';
684 errs() << "Operand name: " << operandInfo.Name << '\n';
685 errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
686 llvm_unreachable("Unhandled type");
691 #define BRANCH(target) { \
692 instType.set("kInstructionTypeBranch"); \
693 DECORATE1(target, "kOperandFlagTarget"); \
696 /// ARMExtractSemantics - Performs various checks on the name of an ARM
697 /// instruction to determine what sort of an instruction it is and then adds
698 /// the appropriate flags to the instruction and its operands
700 /// @arg instType - A reference to the type for the instruction as a whole
701 /// @arg operandTypes - A reference to the array of operand type object pointers
702 /// @arg operandFlags - A reference to the array of operand flag object pointers
703 /// @arg inst - A reference to the original instruction
704 static void ARMExtractSemantics(
705 LiteralConstantEmitter &instType,
706 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
707 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
708 const CodeGenInstruction &inst) {
709 const std::string &name = inst.TheDef->getName();
711 if (name == "tBcc" ||
720 if (name == "tBLr9" ||
721 name == "BLr9_pred" ||
722 name == "tBLXi_r9" ||
723 name == "tBLXr_r9" ||
730 opIndex = inst.Operands.getOperandNamed("func");
731 if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
732 operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
738 /// populateInstInfo - Fills an array of InstInfos with information about each
739 /// instruction in a target
741 /// @arg infoArray - The array of InstInfo objects to populate
742 /// @arg target - The CodeGenTarget to use as a source of instructions
743 static void populateInstInfo(CompoundConstantEmitter &infoArray,
744 CodeGenTarget &target) {
745 const std::vector<const CodeGenInstruction*> &numberedInstructions =
746 target.getInstructionsByEnumValue();
749 unsigned int numInstructions = numberedInstructions.size();
751 for (index = 0; index < numInstructions; ++index) {
752 const CodeGenInstruction& inst = *numberedInstructions[index];
754 CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
755 infoArray.addEntry(infoStruct);
757 LiteralConstantEmitter *instType = new LiteralConstantEmitter;
758 infoStruct->addEntry(instType);
760 LiteralConstantEmitter *numOperandsEmitter =
761 new LiteralConstantEmitter(inst.Operands.size());
762 infoStruct->addEntry(numOperandsEmitter);
764 CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
765 infoStruct->addEntry(operandTypeArray);
767 LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
769 CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
770 infoStruct->addEntry(operandFlagArray);
772 FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
774 for (unsigned operandIndex = 0;
775 operandIndex < EDIS_MAX_OPERANDS;
777 operandTypes[operandIndex] = new LiteralConstantEmitter;
778 operandTypeArray->addEntry(operandTypes[operandIndex]);
780 operandFlags[operandIndex] = new FlagsConstantEmitter;
781 operandFlagArray->addEntry(operandFlags[operandIndex]);
784 unsigned numSyntaxes = 0;
786 if (target.getName() == "X86") {
787 X86PopulateOperands(operandTypes, inst);
788 X86ExtractSemantics(*instType, operandFlags, inst);
791 else if (target.getName() == "ARM") {
792 ARMPopulateOperands(operandTypes, inst);
793 ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
797 CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
799 infoStruct->addEntry(operandOrderArray);
801 for (unsigned syntaxIndex = 0;
802 syntaxIndex < EDIS_MAX_SYNTAXES;
804 CompoundConstantEmitter *operandOrder =
805 new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
807 operandOrderArray->addEntry(operandOrder);
809 if (syntaxIndex < numSyntaxes) {
810 populateOperandOrder(operandOrder, inst, syntaxIndex);
818 static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
819 EnumEmitter operandTypes("OperandTypes");
820 operandTypes.addEntry("kOperandTypeNone");
821 operandTypes.addEntry("kOperandTypeImmediate");
822 operandTypes.addEntry("kOperandTypeRegister");
823 operandTypes.addEntry("kOperandTypeX86Memory");
824 operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
825 operandTypes.addEntry("kOperandTypeX86PCRelative");
826 operandTypes.addEntry("kOperandTypeARMBranchTarget");
827 operandTypes.addEntry("kOperandTypeARMSoReg");
828 operandTypes.addEntry("kOperandTypeARMSoImm");
829 operandTypes.addEntry("kOperandTypeARMRotImm");
830 operandTypes.addEntry("kOperandTypeARMSoImm2Part");
831 operandTypes.addEntry("kOperandTypeARMPredicate");
832 operandTypes.addEntry("kOperandTypeAddrModeImm12");
833 operandTypes.addEntry("kOperandTypeLdStSOReg");
834 operandTypes.addEntry("kOperandTypeARMAddrMode2");
835 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
836 operandTypes.addEntry("kOperandTypeARMAddrMode3");
837 operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
838 operandTypes.addEntry("kOperandTypeARMLdStmMode");
839 operandTypes.addEntry("kOperandTypeARMAddrMode5");
840 operandTypes.addEntry("kOperandTypeARMAddrMode6");
841 operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
842 operandTypes.addEntry("kOperandTypeARMAddrModePC");
843 operandTypes.addEntry("kOperandTypeARMRegisterList");
844 operandTypes.addEntry("kOperandTypeARMDPRRegisterList");
845 operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
846 operandTypes.addEntry("kOperandTypeARMTBAddrMode");
847 operandTypes.addEntry("kOperandTypeThumbITMask");
848 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS");
849 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS");
850 operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
851 operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
852 operandTypes.addEntry("kOperandTypeThumbAddrModePC");
853 operandTypes.addEntry("kOperandTypeThumb2SoReg");
854 operandTypes.addEntry("kOperandTypeThumb2SoImm");
855 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
856 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
857 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
858 operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
859 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
860 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
861 operandTypes.emit(o, i);
865 EnumEmitter operandFlags("OperandFlags");
866 operandFlags.addEntry("kOperandFlagSource");
867 operandFlags.addEntry("kOperandFlagTarget");
868 operandFlags.emitAsFlags(o, i);
872 EnumEmitter instructionTypes("InstructionTypes");
873 instructionTypes.addEntry("kInstructionTypeNone");
874 instructionTypes.addEntry("kInstructionTypeMove");
875 instructionTypes.addEntry("kInstructionTypeBranch");
876 instructionTypes.addEntry("kInstructionTypePush");
877 instructionTypes.addEntry("kInstructionTypePop");
878 instructionTypes.addEntry("kInstructionTypeCall");
879 instructionTypes.addEntry("kInstructionTypeReturn");
880 instructionTypes.emit(o, i);
885 void EDEmitter::run(raw_ostream &o) {
888 CompoundConstantEmitter infoArray;
889 CodeGenTarget target(Records);
891 populateInstInfo(infoArray, target);
893 emitCommonEnums(o, i);
895 o << "namespace {\n";
897 o << "llvm::EDInstInfo instInfo" << target.getName().c_str() << "[] = ";
898 infoArray.emit(o, i);