1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of each
11 // instruction in a format that the enhanced disassembler can use to tokenize
12 // and parse instructions.
14 //===----------------------------------------------------------------------===//
16 #include "EDEmitter.h"
18 #include "AsmWriterInst.h"
19 #include "CodeGenTarget.h"
22 #include "llvm/MC/EDInstInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/Format.h"
25 #include "llvm/Support/raw_ostream.h"
33 ///////////////////////////////////////////////////////////
34 // Support classes for emitting nested C data structures //
35 ///////////////////////////////////////////////////////////
42 std::vector<std::string> Entries;
44 EnumEmitter(const char *N) : Name(N) {
46 int addEntry(const char *e) {
47 Entries.push_back(std::string(e));
48 return Entries.size() - 1;
50 void emit(raw_ostream &o, unsigned int &i) {
51 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
54 unsigned int index = 0;
55 unsigned int numEntries = Entries.size();
56 for (index = 0; index < numEntries; ++index) {
57 o.indent(i) << Entries[index];
58 if (index < (numEntries - 1))
64 o.indent(i) << "};" << "\n";
67 void emitAsFlags(raw_ostream &o, unsigned int &i) {
68 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
71 unsigned int index = 0;
72 unsigned int numEntries = Entries.size();
73 unsigned int flag = 1;
74 for (index = 0; index < numEntries; ++index) {
75 o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
76 if (index < (numEntries - 1))
83 o.indent(i) << "};" << "\n";
90 typedef std::pair<const char*, const char*> member;
91 std::vector< member > Members;
93 StructEmitter(const char *N) : Name(N) {
95 void addMember(const char *t, const char *n) {
99 void emit(raw_ostream &o, unsigned int &i) {
100 o.indent(i) << "struct " << Name.c_str() << " {" << "\n";
103 unsigned int index = 0;
104 unsigned int numMembers = Members.size();
105 for (index = 0; index < numMembers; ++index) {
106 o.indent(i) << Members[index].first << " ";
107 o.indent(i) << Members[index].second << ";" << "\n";
111 o.indent(i) << "};" << "\n";
115 class ConstantEmitter {
117 virtual ~ConstantEmitter() { }
118 virtual void emit(raw_ostream &o, unsigned int &i) = 0;
121 class LiteralConstantEmitter : public ConstantEmitter {
129 LiteralConstantEmitter(const char *string) :
133 LiteralConstantEmitter(int number = 0) :
137 void set(const char *string) {
142 void set(int number) {
147 bool is(const char *string) {
148 return !strcmp(String, string);
150 void emit(raw_ostream &o, unsigned int &i) {
158 class CompoundConstantEmitter : public ConstantEmitter {
160 unsigned int Padding;
161 std::vector<ConstantEmitter *> Entries;
163 CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
165 CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
166 Entries.push_back(e);
170 ~CompoundConstantEmitter() {
171 while (Entries.size()) {
172 ConstantEmitter *entry = Entries.back();
177 void emit(raw_ostream &o, unsigned int &i) {
182 unsigned int numEntries = Entries.size();
184 unsigned int numToPrint;
187 if (numEntries > Padding) {
188 fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
189 llvm_unreachable("More entries than padding");
191 numToPrint = Padding;
193 numToPrint = numEntries;
196 for (index = 0; index < numToPrint; ++index) {
198 if (index < numEntries)
199 Entries[index]->emit(o, i);
203 if (index < (numToPrint - 1))
213 class FlagsConstantEmitter : public ConstantEmitter {
215 std::vector<std::string> Flags;
217 FlagsConstantEmitter() {
219 FlagsConstantEmitter &addEntry(const char *f) {
220 Flags.push_back(std::string(f));
223 void emit(raw_ostream &o, unsigned int &i) {
225 unsigned int numFlags = Flags.size();
229 for (index = 0; index < numFlags; ++index) {
230 o << Flags[index].c_str();
231 if (index < (numFlags - 1))
238 EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
241 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its
242 /// AsmWriterInst for the desired assembly syntax, giving an ordered list of
243 /// operands in the order they appear in the printed instruction. Then, for
244 /// each entry in that list, determines the index of the same operand in the
245 /// CodeGenInstruction, and emits the resulting mapping into an array, filling
246 /// in unused slots with -1.
248 /// @arg operandOrder - The array that will be populated with the operand
249 /// mapping. Each entry will contain -1 (invalid index
250 /// into the operands present in the AsmString) or a number
251 /// representing an index in the operand descriptor array.
252 /// @arg inst - The instruction to use when looking up the operands
253 /// @arg syntax - The syntax to use, according to LLVM's enumeration
254 void populateOperandOrder(CompoundConstantEmitter *operandOrder,
255 const CodeGenInstruction &inst,
257 unsigned int numArgs = 0;
259 AsmWriterInst awInst(inst, syntax, -1, -1);
261 std::vector<AsmWriterOperand>::iterator operandIterator;
263 for (operandIterator = awInst.Operands.begin();
264 operandIterator != awInst.Operands.end();
266 if (operandIterator->OperandType ==
267 AsmWriterOperand::isMachineInstrOperand) {
268 operandOrder->addEntry(
269 new LiteralConstantEmitter(operandIterator->CGIOpNo));
275 /////////////////////////////////////////////////////
276 // Support functions for handling X86 instructions //
277 /////////////////////////////////////////////////////
279 #define SET(flag) { type->set(flag); return 0; }
281 #define REG(str) if (name == str) SET("kOperandTypeRegister");
282 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
283 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
284 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
285 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
287 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is
288 /// actually its type) and translates it into an operand type
290 /// @arg flags - The type object to set
291 /// @arg name - The name of the operand
292 static int X86TypeFromOpName(LiteralConstantEmitter *type,
293 const std::string &name) {
354 PCR("i64i32imm_pcrel");
373 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
374 /// the appropriate flags to their descriptors
376 /// @operandFlags - A reference the array of operand flag objects
377 /// @inst - The instruction to use as a source of information
378 static void X86PopulateOperands(
379 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
380 const CodeGenInstruction &inst) {
381 if (!inst.TheDef->isSubClassOf("X86Inst"))
385 unsigned int numOperands = inst.OperandList.size();
387 for (index = 0; index < numOperands; ++index) {
388 const CodeGenInstruction::OperandInfo &operandInfo =
389 inst.OperandList[index];
390 Record &rec = *operandInfo.Rec;
392 if (X86TypeFromOpName(operandTypes[index], rec.getName())) {
393 errs() << "Operand type: " << rec.getName().c_str() << "\n";
394 errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
395 errs() << "Instruction mame: " << inst.TheDef->getName().c_str() << "\n";
396 llvm_unreachable("Unhandled type");
401 /// decorate1 - Decorates a named operand with a new flag
403 /// @operandFlags - The array of operand flag objects, which don't have names
404 /// @inst - The CodeGenInstruction, which provides a way to translate
405 /// between names and operand indices
406 /// @opName - The name of the operand
407 /// @flag - The name of the flag to add
408 static inline void decorate1(
409 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
410 const CodeGenInstruction &inst,
412 const char *opFlag) {
415 opIndex = inst.getOperandNamed(std::string(opName));
417 operandFlags[opIndex]->addEntry(opFlag);
420 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
422 #define MOV(source, target) { \
423 instType.set("kInstructionTypeMove"); \
424 DECORATE1(source, "kOperandFlagSource"); \
425 DECORATE1(target, "kOperandFlagTarget"); \
428 #define BRANCH(target) { \
429 instType.set("kInstructionTypeBranch"); \
430 DECORATE1(target, "kOperandFlagTarget"); \
433 #define PUSH(source) { \
434 instType.set("kInstructionTypePush"); \
435 DECORATE1(source, "kOperandFlagSource"); \
438 #define POP(target) { \
439 instType.set("kInstructionTypePop"); \
440 DECORATE1(target, "kOperandFlagTarget"); \
443 #define CALL(target) { \
444 instType.set("kInstructionTypeCall"); \
445 DECORATE1(target, "kOperandFlagTarget"); \
449 instType.set("kInstructionTypeReturn"); \
452 /// X86ExtractSemantics - Performs various checks on the name of an X86
453 /// instruction to determine what sort of an instruction it is and then adds
454 /// the appropriate flags to the instruction and its operands
456 /// @arg instType - A reference to the type for the instruction as a whole
457 /// @arg operandFlags - A reference to the array of operand flag object pointers
458 /// @arg inst - A reference to the original instruction
459 static void X86ExtractSemantics(
460 LiteralConstantEmitter &instType,
461 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
462 const CodeGenInstruction &inst) {
463 const std::string &name = inst.TheDef->getName();
465 if (name.find("MOV") != name.npos) {
466 if (name.find("MOV_V") != name.npos) {
467 // ignore (this is a pseudoinstruction)
468 } else if (name.find("MASK") != name.npos) {
469 // ignore (this is a masking move)
470 } else if (name.find("r0") != name.npos) {
471 // ignore (this is a pseudoinstruction)
472 } else if (name.find("PS") != name.npos ||
473 name.find("PD") != name.npos) {
474 // ignore (this is a shuffling move)
475 } else if (name.find("MOVS") != name.npos) {
476 // ignore (this is a string move)
477 } else if (name.find("_F") != name.npos) {
478 // TODO handle _F moves to ST(0)
479 } else if (name.find("a") != name.npos) {
480 // TODO handle moves to/from %ax
481 } else if (name.find("CMOV") != name.npos) {
483 } else if (name.find("PC") != name.npos) {
490 if (name.find("JMP") != name.npos ||
491 name.find("J") == 0) {
492 if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
499 if (name.find("PUSH") != name.npos) {
500 if (name.find("FS") != name.npos ||
501 name.find("GS") != name.npos) {
502 instType.set("kInstructionTypePush");
503 // TODO add support for fixed operands
504 } else if (name.find("F") != name.npos) {
505 // ignore (this pushes onto the FP stack)
506 } else if (name.find("A") != name.npos) {
507 // ignore (pushes all GP registoers onto the stack)
508 } else if (name[name.length() - 1] == 'm') {
510 } else if (name.find("i") != name.npos) {
517 if (name.find("POP") != name.npos) {
518 if (name.find("POPCNT") != name.npos) {
519 // ignore (not a real pop)
520 } else if (name.find("FS") != name.npos ||
521 name.find("GS") != name.npos) {
522 instType.set("kInstructionTypePop");
523 // TODO add support for fixed operands
524 } else if (name.find("F") != name.npos) {
525 // ignore (this pops from the FP stack)
526 } else if (name.find("A") != name.npos) {
527 // ignore (pushes all GP registoers onto the stack)
528 } else if (name[name.length() - 1] == 'm') {
535 if (name.find("CALL") != name.npos) {
536 if (name.find("ADJ") != name.npos) {
537 // ignore (not a call)
538 } else if (name.find("SYSCALL") != name.npos) {
539 // ignore (doesn't go anywhere we know about)
540 } else if (name.find("VMCALL") != name.npos) {
541 // ignore (rather different semantics than a regular call)
542 } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
549 if (name.find("RET") != name.npos) {
561 /////////////////////////////////////////////////////
562 // Support functions for handling ARM instructions //
563 /////////////////////////////////////////////////////
565 #define SET(flag) { type->set(flag); return 0; }
567 #define REG(str) if (name == str) SET("kOperandTypeRegister");
568 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
570 #define MISC(str, type) if (name == str) SET(type);
572 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
573 /// actually its type) and translates it into an operand type
575 /// @arg type - The type object to set
576 /// @arg name - The name of the operand
577 static int ARMFlagFromOpName(LiteralConstantEmitter *type,
578 const std::string &name) {
593 IMM("bf_inv_mask_imm");
594 IMM("jtblock_operand");
596 IMM("cpinst_operand");
605 IMM("jt2block_operand");
609 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
610 MISC("so_reg", "kOperandTypeARMSoReg"); // R, R, I
611 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
612 MISC("so_imm", "kOperandTypeARMSoImm"); // I
613 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I
614 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
615 MISC("pred", "kOperandTypeARMPredicate"); // I, R
616 MISC("it_pred", "kOperandTypeARMPredicate"); // I
617 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
618 MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I
619 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
620 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
621 MISC("addrmode4", "kOperandTypeARMAddrMode4"); // R, I
622 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
623 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
624 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
625 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
626 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
627 MISC("it_mask", "kOperandTypeThumbITMask"); // I
628 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
629 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
630 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
631 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
632 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
633 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
635 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I
636 MISC("t_addrmode_s1", "kOperandTypeThumbAddrModeS1"); // R, I, R
637 MISC("t_addrmode_s2", "kOperandTypeThumbAddrModeS2"); // R, I, R
638 MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4"); // R, I, R
639 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
640 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
656 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
657 /// the appropriate flags to their descriptors
659 /// @operandFlags - A reference the array of operand flag objects
660 /// @inst - The instruction to use as a source of information
661 static void ARMPopulateOperands(
662 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
663 const CodeGenInstruction &inst) {
664 if (!inst.TheDef->isSubClassOf("InstARM") &&
665 !inst.TheDef->isSubClassOf("InstThumb"))
669 unsigned int numOperands = inst.OperandList.size();
671 if (numOperands > EDIS_MAX_OPERANDS) {
672 errs() << "numOperands == " << numOperands << " > " <<
673 EDIS_MAX_OPERANDS << '\n';
674 llvm_unreachable("Too many operands");
677 for (index = 0; index < numOperands; ++index) {
678 const CodeGenInstruction::OperandInfo &operandInfo =
679 inst.OperandList[index];
680 Record &rec = *operandInfo.Rec;
682 if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
683 errs() << "Operand type: " << rec.getName() << '\n';
684 errs() << "Operand name: " << operandInfo.Name << '\n';
685 errs() << "Instruction mame: " << inst.TheDef->getName() << '\n';
686 llvm_unreachable("Unhandled type");
691 #define BRANCH(target) { \
692 instType.set("kInstructionTypeBranch"); \
693 DECORATE1(target, "kOperandFlagTarget"); \
696 /// ARMExtractSemantics - Performs various checks on the name of an ARM
697 /// instruction to determine what sort of an instruction it is and then adds
698 /// the appropriate flags to the instruction and its operands
700 /// @arg instType - A reference to the type for the instruction as a whole
701 /// @arg operandTypes - A reference to the array of operand type object pointers
702 /// @arg operandFlags - A reference to the array of operand flag object pointers
703 /// @arg inst - A reference to the original instruction
704 static void ARMExtractSemantics(
705 LiteralConstantEmitter &instType,
706 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
707 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
708 const CodeGenInstruction &inst) {
709 const std::string &name = inst.TheDef->getName();
711 if (name == "tBcc" ||
720 if (name == "tBLr9" ||
721 name == "BLr9_pred" ||
722 name == "tBLXi_r9" ||
723 name == "tBLXr_r9" ||
730 opIndex = inst.getOperandNamed("func");
731 if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
732 operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
738 /// populateInstInfo - Fills an array of InstInfos with information about each
739 /// instruction in a target
741 /// @arg infoArray - The array of InstInfo objects to populate
742 /// @arg target - The CodeGenTarget to use as a source of instructions
743 static void populateInstInfo(CompoundConstantEmitter &infoArray,
744 CodeGenTarget &target) {
745 const std::vector<const CodeGenInstruction*> &numberedInstructions =
746 target.getInstructionsByEnumValue();
749 unsigned int numInstructions = numberedInstructions.size();
751 for (index = 0; index < numInstructions; ++index) {
752 const CodeGenInstruction& inst = *numberedInstructions[index];
754 CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
755 infoArray.addEntry(infoStruct);
757 LiteralConstantEmitter *instType = new LiteralConstantEmitter;
758 infoStruct->addEntry(instType);
760 LiteralConstantEmitter *numOperandsEmitter =
761 new LiteralConstantEmitter(inst.OperandList.size());
762 infoStruct->addEntry(numOperandsEmitter);
764 CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
765 infoStruct->addEntry(operandTypeArray);
767 LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
769 CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
770 infoStruct->addEntry(operandFlagArray);
772 FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
774 for (unsigned operandIndex = 0;
775 operandIndex < EDIS_MAX_OPERANDS;
777 operandTypes[operandIndex] = new LiteralConstantEmitter;
778 operandTypeArray->addEntry(operandTypes[operandIndex]);
780 operandFlags[operandIndex] = new FlagsConstantEmitter;
781 operandFlagArray->addEntry(operandFlags[operandIndex]);
784 unsigned numSyntaxes = 0;
786 if (target.getName() == "X86") {
787 X86PopulateOperands(operandTypes, inst);
788 X86ExtractSemantics(*instType, operandFlags, inst);
791 else if (target.getName() == "ARM") {
792 ARMPopulateOperands(operandTypes, inst);
793 ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
797 CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
799 infoStruct->addEntry(operandOrderArray);
801 for (unsigned syntaxIndex = 0;
802 syntaxIndex < EDIS_MAX_SYNTAXES;
804 CompoundConstantEmitter *operandOrder =
805 new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
807 operandOrderArray->addEntry(operandOrder);
809 if (syntaxIndex < numSyntaxes) {
810 populateOperandOrder(operandOrder, inst, syntaxIndex);
818 static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
819 EnumEmitter operandTypes("OperandTypes");
820 operandTypes.addEntry("kOperandTypeNone");
821 operandTypes.addEntry("kOperandTypeImmediate");
822 operandTypes.addEntry("kOperandTypeRegister");
823 operandTypes.addEntry("kOperandTypeX86Memory");
824 operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
825 operandTypes.addEntry("kOperandTypeX86PCRelative");
826 operandTypes.addEntry("kOperandTypeARMBranchTarget");
827 operandTypes.addEntry("kOperandTypeARMSoReg");
828 operandTypes.addEntry("kOperandTypeARMSoImm");
829 operandTypes.addEntry("kOperandTypeARMSoImm2Part");
830 operandTypes.addEntry("kOperandTypeARMPredicate");
831 operandTypes.addEntry("kOperandTypeARMAddrMode2");
832 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
833 operandTypes.addEntry("kOperandTypeARMAddrMode3");
834 operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
835 operandTypes.addEntry("kOperandTypeARMAddrMode4");
836 operandTypes.addEntry("kOperandTypeARMAddrMode5");
837 operandTypes.addEntry("kOperandTypeARMAddrMode6");
838 operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
839 operandTypes.addEntry("kOperandTypeARMAddrModePC");
840 operandTypes.addEntry("kOperandTypeARMRegisterList");
841 operandTypes.addEntry("kOperandTypeARMTBAddrMode");
842 operandTypes.addEntry("kOperandTypeThumbITMask");
843 operandTypes.addEntry("kOperandTypeThumbAddrModeS1");
844 operandTypes.addEntry("kOperandTypeThumbAddrModeS2");
845 operandTypes.addEntry("kOperandTypeThumbAddrModeS4");
846 operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
847 operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
848 operandTypes.addEntry("kOperandTypeThumb2SoReg");
849 operandTypes.addEntry("kOperandTypeThumb2SoImm");
850 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
851 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
852 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
853 operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
854 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
855 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
856 operandTypes.emit(o, i);
860 EnumEmitter operandFlags("OperandFlags");
861 operandFlags.addEntry("kOperandFlagSource");
862 operandFlags.addEntry("kOperandFlagTarget");
863 operandFlags.emitAsFlags(o, i);
867 EnumEmitter instructionTypes("InstructionTypes");
868 instructionTypes.addEntry("kInstructionTypeNone");
869 instructionTypes.addEntry("kInstructionTypeMove");
870 instructionTypes.addEntry("kInstructionTypeBranch");
871 instructionTypes.addEntry("kInstructionTypePush");
872 instructionTypes.addEntry("kInstructionTypePop");
873 instructionTypes.addEntry("kInstructionTypeCall");
874 instructionTypes.addEntry("kInstructionTypeReturn");
875 instructionTypes.emit(o, i);
880 void EDEmitter::run(raw_ostream &o) {
883 CompoundConstantEmitter infoArray;
884 CodeGenTarget target;
886 populateInstInfo(infoArray, target);
888 emitCommonEnums(o, i);
890 o << "namespace {\n";
892 o << "llvm::EDInstInfo instInfo" << target.getName().c_str() << "[] = ";
893 infoArray.emit(o, i);
899 void EDEmitter::runHeader(raw_ostream &o) {
900 EmitSourceFileHeader("Enhanced Disassembly Info Header", o);
902 o << "#ifndef EDInfo_" << "\n";
903 o << "#define EDInfo_" << "\n";
905 o << "#define EDIS_MAX_OPERANDS " << format("%d", EDIS_MAX_OPERANDS) << "\n";
906 o << "#define EDIS_MAX_SYNTAXES " << format("%d", EDIS_MAX_SYNTAXES) << "\n";
911 emitCommonEnums(o, i);
914 o << "#endif" << "\n";