1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of each
11 // instruction in a format that the enhanced disassembler can use to tokenize
12 // and parse instructions.
14 //===----------------------------------------------------------------------===//
16 #include "EDEmitter.h"
18 #include "AsmWriterInst.h"
19 #include "CodeGenTarget.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/Format.h"
24 #include "llvm/Support/raw_ostream.h"
30 #define MAX_OPERANDS 13
31 #define MAX_SYNTAXES 2
35 ///////////////////////////////////////////////////////////
36 // Support classes for emitting nested C data structures //
37 ///////////////////////////////////////////////////////////
44 std::vector<std::string> Entries;
46 EnumEmitter(const char *N) : Name(N) {
48 int addEntry(const char *e) {
49 Entries.push_back(std::string(e));
50 return Entries.size() - 1;
52 void emit(raw_ostream &o, unsigned int &i) {
53 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
56 unsigned int index = 0;
57 unsigned int numEntries = Entries.size();
58 for (index = 0; index < numEntries; ++index) {
59 o.indent(i) << Entries[index];
60 if (index < (numEntries - 1))
66 o.indent(i) << "};" << "\n";
69 void emitAsFlags(raw_ostream &o, unsigned int &i) {
70 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
73 unsigned int index = 0;
74 unsigned int numEntries = Entries.size();
75 unsigned int flag = 1;
76 for (index = 0; index < numEntries; ++index) {
77 o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
78 if (index < (numEntries - 1))
85 o.indent(i) << "};" << "\n";
92 typedef std::pair<const char*, const char*> member;
93 std::vector< member > Members;
95 StructEmitter(const char *N) : Name(N) {
97 void addMember(const char *t, const char *n) {
101 void emit(raw_ostream &o, unsigned int &i) {
102 o.indent(i) << "struct " << Name.c_str() << " {" << "\n";
105 unsigned int index = 0;
106 unsigned int numMembers = Members.size();
107 for (index = 0; index < numMembers; ++index) {
108 o.indent(i) << Members[index].first << " ";
109 o.indent(i) << Members[index].second << ";" << "\n";
113 o.indent(i) << "};" << "\n";
117 class ConstantEmitter {
119 virtual ~ConstantEmitter() { }
120 virtual void emit(raw_ostream &o, unsigned int &i) = 0;
123 class LiteralConstantEmitter : public ConstantEmitter {
131 LiteralConstantEmitter(const char *string) :
135 LiteralConstantEmitter(int number = 0) :
139 void set(const char *string) {
144 void set(int number) {
149 bool is(const char *string) {
150 return !strcmp(String, string);
152 void emit(raw_ostream &o, unsigned int &i) {
160 class CompoundConstantEmitter : public ConstantEmitter {
162 unsigned int Padding;
163 std::vector<ConstantEmitter *> Entries;
165 CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
167 CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
168 Entries.push_back(e);
172 ~CompoundConstantEmitter() {
173 while (Entries.size()) {
174 ConstantEmitter *entry = Entries.back();
179 void emit(raw_ostream &o, unsigned int &i) {
184 unsigned int numEntries = Entries.size();
186 unsigned int numToPrint;
189 if (numEntries > Padding) {
190 fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
191 llvm_unreachable("More entries than padding");
193 numToPrint = Padding;
195 numToPrint = numEntries;
198 for (index = 0; index < numToPrint; ++index) {
200 if (index < numEntries)
201 Entries[index]->emit(o, i);
205 if (index < (numToPrint - 1))
215 class FlagsConstantEmitter : public ConstantEmitter {
217 std::vector<std::string> Flags;
219 FlagsConstantEmitter() {
221 FlagsConstantEmitter &addEntry(const char *f) {
222 Flags.push_back(std::string(f));
225 void emit(raw_ostream &o, unsigned int &i) {
227 unsigned int numFlags = Flags.size();
231 for (index = 0; index < numFlags; ++index) {
232 o << Flags[index].c_str();
233 if (index < (numFlags - 1))
240 EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
243 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its
244 /// AsmWriterInst for the desired assembly syntax, giving an ordered list of
245 /// operands in the order they appear in the printed instruction. Then, for
246 /// each entry in that list, determines the index of the same operand in the
247 /// CodeGenInstruction, and emits the resulting mapping into an array, filling
248 /// in unused slots with -1.
250 /// @arg operandOrder - The array that will be populated with the operand
251 /// mapping. Each entry will contain -1 (invalid index
252 /// into the operands present in the AsmString) or a number
253 /// representing an index in the operand descriptor array.
254 /// @arg inst - The instruction to use when looking up the operands
255 /// @arg syntax - The syntax to use, according to LLVM's enumeration
256 void populateOperandOrder(CompoundConstantEmitter *operandOrder,
257 const CodeGenInstruction &inst,
259 unsigned int numArgs = 0;
261 AsmWriterInst awInst(inst, syntax, -1, -1);
263 std::vector<AsmWriterOperand>::iterator operandIterator;
265 for (operandIterator = awInst.Operands.begin();
266 operandIterator != awInst.Operands.end();
268 if (operandIterator->OperandType ==
269 AsmWriterOperand::isMachineInstrOperand) {
270 operandOrder->addEntry(
271 new LiteralConstantEmitter(operandIterator->CGIOpNo));
277 /////////////////////////////////////////////////////
278 // Support functions for handling X86 instructions //
279 /////////////////////////////////////////////////////
281 #define SET(flag) { type->set(flag); return 0; }
283 #define REG(str) if (name == str) SET("kOperandTypeRegister");
284 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
285 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
286 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
287 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
289 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is
290 /// actually its type) and translates it into an operand type
292 /// @arg flags - The type object to set
293 /// @arg name - The name of the operand
294 static int X86TypeFromOpName(LiteralConstantEmitter *type,
295 const std::string &name) {
314 REG("CONTROL_REG_32");
315 REG("CONTROL_REG_64");
326 IMM("i64i32imm_pcrel");
373 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
374 /// the appropriate flags to their descriptors
376 /// @operandFlags - A reference the array of operand flag objects
377 /// @inst - The instruction to use as a source of information
378 static void X86PopulateOperands(
379 LiteralConstantEmitter *(&operandTypes)[MAX_OPERANDS],
380 const CodeGenInstruction &inst) {
381 if (!inst.TheDef->isSubClassOf("X86Inst"))
385 unsigned int numOperands = inst.OperandList.size();
387 for (index = 0; index < numOperands; ++index) {
388 const CodeGenInstruction::OperandInfo &operandInfo =
389 inst.OperandList[index];
390 Record &rec = *operandInfo.Rec;
392 if (X86TypeFromOpName(operandTypes[index], rec.getName())) {
393 errs() << "Operand type: " << rec.getName().c_str() << "\n";
394 errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
395 errs() << "Instruction mame: " << inst.TheDef->getName().c_str() << "\n";
396 llvm_unreachable("Unhandled type");
401 /// decorate1 - Decorates a named operand with a new flag
403 /// @operandFlags - The array of operand flag objects, which don't have names
404 /// @inst - The CodeGenInstruction, which provides a way to translate
405 /// between names and operand indices
406 /// @opName - The name of the operand
407 /// @flag - The name of the flag to add
408 static inline void decorate1(
409 FlagsConstantEmitter *(&operandFlags)[MAX_OPERANDS],
410 const CodeGenInstruction &inst,
412 const char *opFlag) {
415 opIndex = inst.getOperandNamed(std::string(opName));
417 operandFlags[opIndex]->addEntry(opFlag);
420 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
422 #define MOV(source, target) { \
423 instType.set("kInstructionTypeMove"); \
424 DECORATE1(source, "kOperandFlagSource"); \
425 DECORATE1(target, "kOperandFlagTarget"); \
428 #define BRANCH(target) { \
429 instType.set("kInstructionTypeBranch"); \
430 DECORATE1(target, "kOperandFlagTarget"); \
433 #define PUSH(source) { \
434 instType.set("kInstructionTypePush"); \
435 DECORATE1(source, "kOperandFlagSource"); \
438 #define POP(target) { \
439 instType.set("kInstructionTypePop"); \
440 DECORATE1(target, "kOperandFlagTarget"); \
443 #define CALL(target) { \
444 instType.set("kInstructionTypeCall"); \
445 DECORATE1(target, "kOperandFlagTarget"); \
449 instType.set("kInstructionTypeReturn"); \
452 /// X86ExtractSemantics - Performs various checks on the name of an X86
453 /// instruction to determine what sort of an instruction it is and then adds
454 /// the appropriate flags to the instruction and its operands
456 /// @arg instType - A reference to the type for the instruction as a whole
457 /// @arg operandFlags - A reference to the array of operand flag object pointers
458 /// @arg inst - A reference to the original instruction
459 static void X86ExtractSemantics(
460 LiteralConstantEmitter &instType,
461 FlagsConstantEmitter *(&operandFlags)[MAX_OPERANDS],
462 const CodeGenInstruction &inst) {
463 const std::string &name = inst.TheDef->getName();
465 if (name.find("MOV") != name.npos) {
466 if (name.find("MOV_V") != name.npos) {
467 // ignore (this is a pseudoinstruction)
468 } else if (name.find("MASK") != name.npos) {
469 // ignore (this is a masking move)
470 } else if (name.find("r0") != name.npos) {
471 // ignore (this is a pseudoinstruction)
472 } else if (name.find("PS") != name.npos ||
473 name.find("PD") != name.npos) {
474 // ignore (this is a shuffling move)
475 } else if (name.find("MOVS") != name.npos) {
476 // ignore (this is a string move)
477 } else if (name.find("_F") != name.npos) {
478 // TODO handle _F moves to ST(0)
479 } else if (name.find("a") != name.npos) {
480 // TODO handle moves to/from %ax
481 } else if (name.find("CMOV") != name.npos) {
483 } else if (name.find("PC") != name.npos) {
490 if (name.find("JMP") != name.npos ||
491 name.find("J") == 0) {
492 if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
499 if (name.find("PUSH") != name.npos) {
500 if (name.find("FS") != name.npos ||
501 name.find("GS") != name.npos) {
502 instType.set("kInstructionTypePush");
503 // TODO add support for fixed operands
504 } else if (name.find("F") != name.npos) {
505 // ignore (this pushes onto the FP stack)
506 } else if (name[name.length() - 1] == 'm') {
508 } else if (name.find("i") != name.npos) {
515 if (name.find("POP") != name.npos) {
516 if (name.find("POPCNT") != name.npos) {
517 // ignore (not a real pop)
518 } else if (name.find("FS") != name.npos ||
519 name.find("GS") != name.npos) {
520 instType.set("kInstructionTypePop");
521 // TODO add support for fixed operands
522 } else if (name.find("F") != name.npos) {
523 // ignore (this pops from the FP stack)
524 } else if (name[name.length() - 1] == 'm') {
531 if (name.find("CALL") != name.npos) {
532 if (name.find("ADJ") != name.npos) {
533 // ignore (not a call)
534 } else if (name.find("SYSCALL") != name.npos) {
535 // ignore (doesn't go anywhere we know about)
536 } else if (name.find("VMCALL") != name.npos) {
537 // ignore (rather different semantics than a regular call)
538 } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
545 if (name.find("RET") != name.npos) {
557 /////////////////////////////////////////////////////
558 // Support functions for handling ARM instructions //
559 /////////////////////////////////////////////////////
561 #define SET(flag) { type->set(flag); return 0; }
563 #define REG(str) if (name == str) SET("kOperandTypeRegister");
564 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
566 #define MISC(str, type) if (name == str) SET(type);
568 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
569 /// actually its type) and translates it into an operand type
571 /// @arg type - The type object to set
572 /// @arg name - The name of the operand
573 static int ARMFlagFromOpName(LiteralConstantEmitter *type,
574 const std::string &name) {
586 IMM("bf_inv_mask_imm");
587 IMM("jtblock_operand");
589 IMM("cpinst_operand");
601 IMM("jt2block_operand");
605 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
606 MISC("so_reg", "kOperandTypeARMSoReg"); // R, R, I
607 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
608 MISC("so_imm", "kOperandTypeARMSoImm"); // I
609 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I
610 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
611 MISC("pred", "kOperandTypeARMPredicate"); // I, R
612 MISC("it_pred", "kOperandTypeARMPredicate"); // I
613 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
614 MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I
615 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
616 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
617 MISC("addrmode4", "kOperandTypeARMAddrMode4"); // R, I
618 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
619 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
620 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
621 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
622 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
623 MISC("it_mask", "kOperandTypeThumbITMask"); // I
624 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
625 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
626 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
627 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
628 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
629 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
631 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I
632 MISC("t_addrmode_s1", "kOperandTypeThumbAddrModeS1"); // R, I, R
633 MISC("t_addrmode_s2", "kOperandTypeThumbAddrModeS2"); // R, I, R
634 MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4"); // R, I, R
635 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
636 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
652 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
653 /// the appropriate flags to their descriptors
655 /// @operandFlags - A reference the array of operand flag objects
656 /// @inst - The instruction to use as a source of information
657 static void ARMPopulateOperands(
658 LiteralConstantEmitter *(&operandTypes)[MAX_OPERANDS],
659 const CodeGenInstruction &inst) {
660 if (!inst.TheDef->isSubClassOf("InstARM") &&
661 !inst.TheDef->isSubClassOf("InstThumb"))
665 unsigned int numOperands = inst.OperandList.size();
667 if (numOperands > MAX_OPERANDS) {
668 errs() << "numOperands == " << numOperands << " > " << MAX_OPERANDS << '\n';
669 llvm_unreachable("Too many operands");
672 for (index = 0; index < numOperands; ++index) {
673 const CodeGenInstruction::OperandInfo &operandInfo =
674 inst.OperandList[index];
675 Record &rec = *operandInfo.Rec;
677 if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
678 errs() << "Operand type: " << rec.getName() << '\n';
679 errs() << "Operand name: " << operandInfo.Name << '\n';
680 errs() << "Instruction mame: " << inst.TheDef->getName() << '\n';
681 llvm_unreachable("Unhandled type");
686 #define BRANCH(target) { \
687 instType.set("kInstructionTypeBranch"); \
688 DECORATE1(target, "kOperandFlagTarget"); \
691 /// ARMExtractSemantics - Performs various checks on the name of an ARM
692 /// instruction to determine what sort of an instruction it is and then adds
693 /// the appropriate flags to the instruction and its operands
695 /// @arg instType - A reference to the type for the instruction as a whole
696 /// @arg operandTypes - A reference to the array of operand type object pointers
697 /// @arg operandFlags - A reference to the array of operand flag object pointers
698 /// @arg inst - A reference to the original instruction
699 static void ARMExtractSemantics(
700 LiteralConstantEmitter &instType,
701 LiteralConstantEmitter *(&operandTypes)[MAX_OPERANDS],
702 FlagsConstantEmitter *(&operandFlags)[MAX_OPERANDS],
703 const CodeGenInstruction &inst) {
704 const std::string &name = inst.TheDef->getName();
706 if (name == "tBcc" ||
715 if (name == "tBLr9" ||
716 name == "BLr9_pred" ||
717 name == "tBLXi_r9" ||
718 name == "tBLXr_r9" ||
725 opIndex = inst.getOperandNamed("func");
726 if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
727 operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
733 /// populateInstInfo - Fills an array of InstInfos with information about each
734 /// instruction in a target
736 /// @arg infoArray - The array of InstInfo objects to populate
737 /// @arg target - The CodeGenTarget to use as a source of instructions
738 static void populateInstInfo(CompoundConstantEmitter &infoArray,
739 CodeGenTarget &target) {
740 const std::vector<const CodeGenInstruction*> &numberedInstructions =
741 target.getInstructionsByEnumValue();
744 unsigned int numInstructions = numberedInstructions.size();
746 for (index = 0; index < numInstructions; ++index) {
747 const CodeGenInstruction& inst = *numberedInstructions[index];
749 CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
750 infoArray.addEntry(infoStruct);
752 LiteralConstantEmitter *instType = new LiteralConstantEmitter;
753 infoStruct->addEntry(instType);
755 LiteralConstantEmitter *numOperandsEmitter =
756 new LiteralConstantEmitter(inst.OperandList.size());
757 infoStruct->addEntry(numOperandsEmitter);
759 CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
760 infoStruct->addEntry(operandTypeArray);
762 LiteralConstantEmitter *operandTypes[MAX_OPERANDS];
764 CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
765 infoStruct->addEntry(operandFlagArray);
767 FlagsConstantEmitter *operandFlags[MAX_OPERANDS];
769 for (unsigned operandIndex = 0;
770 operandIndex < MAX_OPERANDS;
772 operandTypes[operandIndex] = new LiteralConstantEmitter;
773 operandTypeArray->addEntry(operandTypes[operandIndex]);
775 operandFlags[operandIndex] = new FlagsConstantEmitter;
776 operandFlagArray->addEntry(operandFlags[operandIndex]);
779 unsigned numSyntaxes = 0;
781 if (target.getName() == "X86") {
782 X86PopulateOperands(operandTypes, inst);
783 X86ExtractSemantics(*instType, operandFlags, inst);
786 else if (target.getName() == "ARM") {
787 ARMPopulateOperands(operandTypes, inst);
788 ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
792 CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
794 infoStruct->addEntry(operandOrderArray);
796 for (unsigned syntaxIndex = 0; syntaxIndex < MAX_SYNTAXES; ++syntaxIndex) {
797 CompoundConstantEmitter *operandOrder =
798 new CompoundConstantEmitter(MAX_OPERANDS);
800 operandOrderArray->addEntry(operandOrder);
802 if (syntaxIndex < numSyntaxes) {
803 populateOperandOrder(operandOrder, inst, syntaxIndex);
811 void EDEmitter::run(raw_ostream &o) {
814 CompoundConstantEmitter infoArray;
815 CodeGenTarget target;
817 populateInstInfo(infoArray, target);
819 o << "InstInfo instInfo" << target.getName().c_str() << "[] = ";
820 infoArray.emit(o, i);
824 void EDEmitter::runHeader(raw_ostream &o) {
825 EmitSourceFileHeader("Enhanced Disassembly Info Header", o);
827 o << "#ifndef EDInfo_" << "\n";
828 o << "#define EDInfo_" << "\n";
830 o << "#include <inttypes.h>" << "\n";
832 o << "#define MAX_OPERANDS " << format("%d", MAX_OPERANDS) << "\n";
833 o << "#define MAX_SYNTAXES " << format("%d", MAX_SYNTAXES) << "\n";
838 EnumEmitter operandTypes("OperandTypes");
839 operandTypes.addEntry("kOperandTypeNone");
840 operandTypes.addEntry("kOperandTypeImmediate");
841 operandTypes.addEntry("kOperandTypeRegister");
842 operandTypes.addEntry("kOperandTypeX86Memory");
843 operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
844 operandTypes.addEntry("kOperandTypeX86PCRelative");
845 operandTypes.addEntry("kOperandTypeARMBranchTarget");
846 operandTypes.addEntry("kOperandTypeARMSoReg");
847 operandTypes.addEntry("kOperandTypeARMSoImm");
848 operandTypes.addEntry("kOperandTypeARMSoImm2Part");
849 operandTypes.addEntry("kOperandTypeARMPredicate");
850 operandTypes.addEntry("kOperandTypeARMAddrMode2");
851 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
852 operandTypes.addEntry("kOperandTypeARMAddrMode3");
853 operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
854 operandTypes.addEntry("kOperandTypeARMAddrMode4");
855 operandTypes.addEntry("kOperandTypeARMAddrMode5");
856 operandTypes.addEntry("kOperandTypeARMAddrMode6");
857 operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
858 operandTypes.addEntry("kOperandTypeARMAddrModePC");
859 operandTypes.addEntry("kOperandTypeARMRegisterList");
860 operandTypes.addEntry("kOperandTypeARMTBAddrMode");
861 operandTypes.addEntry("kOperandTypeThumbITMask");
862 operandTypes.addEntry("kOperandTypeThumbAddrModeS1");
863 operandTypes.addEntry("kOperandTypeThumbAddrModeS2");
864 operandTypes.addEntry("kOperandTypeThumbAddrModeS4");
865 operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
866 operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
867 operandTypes.addEntry("kOperandTypeThumb2SoReg");
868 operandTypes.addEntry("kOperandTypeThumb2SoImm");
869 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
870 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
871 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
872 operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
873 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
874 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
876 operandTypes.emit(o, i);
880 EnumEmitter operandFlags("OperandFlags");
881 operandFlags.addEntry("kOperandFlagSource");
882 operandFlags.addEntry("kOperandFlagTarget");
883 operandFlags.emitAsFlags(o, i);
887 EnumEmitter instructionTypes("InstructionTypes");
888 instructionTypes.addEntry("kInstructionTypeNone");
889 instructionTypes.addEntry("kInstructionTypeMove");
890 instructionTypes.addEntry("kInstructionTypeBranch");
891 instructionTypes.addEntry("kInstructionTypePush");
892 instructionTypes.addEntry("kInstructionTypePop");
893 instructionTypes.addEntry("kInstructionTypeCall");
894 instructionTypes.addEntry("kInstructionTypeReturn");
895 instructionTypes.emit(o, i);
899 StructEmitter instInfo("InstInfo");
900 instInfo.addMember("uint8_t", "instructionType");
901 instInfo.addMember("uint8_t", "numOperands");
902 instInfo.addMember("uint8_t", "operandTypes[MAX_OPERANDS]");
903 instInfo.addMember("uint8_t", "operandFlags[MAX_OPERANDS]");
904 instInfo.addMember("const char", "operandOrders[MAX_SYNTAXES][MAX_OPERANDS]");
908 o << "#endif" << "\n";