1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of each
11 // instruction in a format that the enhanced disassembler can use to tokenize
12 // and parse instructions.
14 //===----------------------------------------------------------------------===//
16 #include "EDEmitter.h"
18 #include "AsmWriterInst.h"
19 #include "CodeGenTarget.h"
22 #include "llvm/MC/EDInstInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/Format.h"
25 #include "llvm/Support/raw_ostream.h"
33 ///////////////////////////////////////////////////////////
34 // Support classes for emitting nested C data structures //
35 ///////////////////////////////////////////////////////////
42 std::vector<std::string> Entries;
44 EnumEmitter(const char *N) : Name(N) {
46 int addEntry(const char *e) {
47 Entries.push_back(std::string(e));
48 return Entries.size() - 1;
50 void emit(raw_ostream &o, unsigned int &i) {
51 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
54 unsigned int index = 0;
55 unsigned int numEntries = Entries.size();
56 for (index = 0; index < numEntries; ++index) {
57 o.indent(i) << Entries[index];
58 if (index < (numEntries - 1))
64 o.indent(i) << "};" << "\n";
67 void emitAsFlags(raw_ostream &o, unsigned int &i) {
68 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
71 unsigned int index = 0;
72 unsigned int numEntries = Entries.size();
73 unsigned int flag = 1;
74 for (index = 0; index < numEntries; ++index) {
75 o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
76 if (index < (numEntries - 1))
83 o.indent(i) << "};" << "\n";
87 class ConstantEmitter {
89 virtual ~ConstantEmitter() { }
90 virtual void emit(raw_ostream &o, unsigned int &i) = 0;
93 class LiteralConstantEmitter : public ConstantEmitter {
101 LiteralConstantEmitter(int number = 0) :
105 void set(const char *string) {
110 bool is(const char *string) {
111 return !strcmp(String, string);
113 void emit(raw_ostream &o, unsigned int &i) {
121 class CompoundConstantEmitter : public ConstantEmitter {
123 unsigned int Padding;
124 std::vector<ConstantEmitter *> Entries;
126 CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
128 CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
129 Entries.push_back(e);
133 ~CompoundConstantEmitter() {
134 while (Entries.size()) {
135 ConstantEmitter *entry = Entries.back();
140 void emit(raw_ostream &o, unsigned int &i) {
145 unsigned int numEntries = Entries.size();
147 unsigned int numToPrint;
150 if (numEntries > Padding) {
151 fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
152 llvm_unreachable("More entries than padding");
154 numToPrint = Padding;
156 numToPrint = numEntries;
159 for (index = 0; index < numToPrint; ++index) {
161 if (index < numEntries)
162 Entries[index]->emit(o, i);
166 if (index < (numToPrint - 1))
176 class FlagsConstantEmitter : public ConstantEmitter {
178 std::vector<std::string> Flags;
180 FlagsConstantEmitter() {
182 FlagsConstantEmitter &addEntry(const char *f) {
183 Flags.push_back(std::string(f));
186 void emit(raw_ostream &o, unsigned int &i) {
188 unsigned int numFlags = Flags.size();
192 for (index = 0; index < numFlags; ++index) {
193 o << Flags[index].c_str();
194 if (index < (numFlags - 1))
201 EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
204 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its
205 /// AsmWriterInst for the desired assembly syntax, giving an ordered list of
206 /// operands in the order they appear in the printed instruction. Then, for
207 /// each entry in that list, determines the index of the same operand in the
208 /// CodeGenInstruction, and emits the resulting mapping into an array, filling
209 /// in unused slots with -1.
211 /// @arg operandOrder - The array that will be populated with the operand
212 /// mapping. Each entry will contain -1 (invalid index
213 /// into the operands present in the AsmString) or a number
214 /// representing an index in the operand descriptor array.
215 /// @arg inst - The instruction to use when looking up the operands
216 /// @arg syntax - The syntax to use, according to LLVM's enumeration
217 void populateOperandOrder(CompoundConstantEmitter *operandOrder,
218 const CodeGenInstruction &inst,
220 unsigned int numArgs = 0;
222 AsmWriterInst awInst(inst, syntax, -1, -1);
224 std::vector<AsmWriterOperand>::iterator operandIterator;
226 for (operandIterator = awInst.Operands.begin();
227 operandIterator != awInst.Operands.end();
229 if (operandIterator->OperandType ==
230 AsmWriterOperand::isMachineInstrOperand) {
231 operandOrder->addEntry(
232 new LiteralConstantEmitter(operandIterator->CGIOpNo));
238 /////////////////////////////////////////////////////
239 // Support functions for handling X86 instructions //
240 /////////////////////////////////////////////////////
242 #define SET(flag) { type->set(flag); return 0; }
244 #define REG(str) if (name == str) SET("kOperandTypeRegister");
245 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
246 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
247 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
248 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
250 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is
251 /// actually its type) and translates it into an operand type
253 /// @arg flags - The type object to set
254 /// @arg name - The name of the operand
255 static int X86TypeFromOpName(LiteralConstantEmitter *type,
256 const std::string &name) {
318 PCR("i64i32imm_pcrel");
337 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
338 /// the appropriate flags to their descriptors
340 /// @operandFlags - A reference the array of operand flag objects
341 /// @inst - The instruction to use as a source of information
342 static void X86PopulateOperands(
343 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
344 const CodeGenInstruction &inst) {
345 if (!inst.TheDef->isSubClassOf("X86Inst"))
349 unsigned int numOperands = inst.OperandList.size();
351 for (index = 0; index < numOperands; ++index) {
352 const CodeGenInstruction::OperandInfo &operandInfo =
353 inst.OperandList[index];
354 Record &rec = *operandInfo.Rec;
356 if (X86TypeFromOpName(operandTypes[index], rec.getName())) {
357 errs() << "Operand type: " << rec.getName().c_str() << "\n";
358 errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
359 errs() << "Instruction mame: " << inst.TheDef->getName().c_str() << "\n";
360 llvm_unreachable("Unhandled type");
365 /// decorate1 - Decorates a named operand with a new flag
367 /// @operandFlags - The array of operand flag objects, which don't have names
368 /// @inst - The CodeGenInstruction, which provides a way to translate
369 /// between names and operand indices
370 /// @opName - The name of the operand
371 /// @flag - The name of the flag to add
372 static inline void decorate1(
373 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
374 const CodeGenInstruction &inst,
376 const char *opFlag) {
379 opIndex = inst.getOperandNamed(std::string(opName));
381 operandFlags[opIndex]->addEntry(opFlag);
384 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
386 #define MOV(source, target) { \
387 instType.set("kInstructionTypeMove"); \
388 DECORATE1(source, "kOperandFlagSource"); \
389 DECORATE1(target, "kOperandFlagTarget"); \
392 #define BRANCH(target) { \
393 instType.set("kInstructionTypeBranch"); \
394 DECORATE1(target, "kOperandFlagTarget"); \
397 #define PUSH(source) { \
398 instType.set("kInstructionTypePush"); \
399 DECORATE1(source, "kOperandFlagSource"); \
402 #define POP(target) { \
403 instType.set("kInstructionTypePop"); \
404 DECORATE1(target, "kOperandFlagTarget"); \
407 #define CALL(target) { \
408 instType.set("kInstructionTypeCall"); \
409 DECORATE1(target, "kOperandFlagTarget"); \
413 instType.set("kInstructionTypeReturn"); \
416 /// X86ExtractSemantics - Performs various checks on the name of an X86
417 /// instruction to determine what sort of an instruction it is and then adds
418 /// the appropriate flags to the instruction and its operands
420 /// @arg instType - A reference to the type for the instruction as a whole
421 /// @arg operandFlags - A reference to the array of operand flag object pointers
422 /// @arg inst - A reference to the original instruction
423 static void X86ExtractSemantics(
424 LiteralConstantEmitter &instType,
425 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
426 const CodeGenInstruction &inst) {
427 const std::string &name = inst.TheDef->getName();
429 if (name.find("MOV") != name.npos) {
430 if (name.find("MOV_V") != name.npos) {
431 // ignore (this is a pseudoinstruction)
432 } else if (name.find("MASK") != name.npos) {
433 // ignore (this is a masking move)
434 } else if (name.find("r0") != name.npos) {
435 // ignore (this is a pseudoinstruction)
436 } else if (name.find("PS") != name.npos ||
437 name.find("PD") != name.npos) {
438 // ignore (this is a shuffling move)
439 } else if (name.find("MOVS") != name.npos) {
440 // ignore (this is a string move)
441 } else if (name.find("_F") != name.npos) {
442 // TODO handle _F moves to ST(0)
443 } else if (name.find("a") != name.npos) {
444 // TODO handle moves to/from %ax
445 } else if (name.find("CMOV") != name.npos) {
447 } else if (name.find("PC") != name.npos) {
454 if (name.find("JMP") != name.npos ||
455 name.find("J") == 0) {
456 if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
463 if (name.find("PUSH") != name.npos) {
464 if (name.find("FS") != name.npos ||
465 name.find("GS") != name.npos) {
466 instType.set("kInstructionTypePush");
467 // TODO add support for fixed operands
468 } else if (name.find("F") != name.npos) {
469 // ignore (this pushes onto the FP stack)
470 } else if (name.find("A") != name.npos) {
471 // ignore (pushes all GP registoers onto the stack)
472 } else if (name[name.length() - 1] == 'm') {
474 } else if (name.find("i") != name.npos) {
481 if (name.find("POP") != name.npos) {
482 if (name.find("POPCNT") != name.npos) {
483 // ignore (not a real pop)
484 } else if (name.find("FS") != name.npos ||
485 name.find("GS") != name.npos) {
486 instType.set("kInstructionTypePop");
487 // TODO add support for fixed operands
488 } else if (name.find("F") != name.npos) {
489 // ignore (this pops from the FP stack)
490 } else if (name.find("A") != name.npos) {
491 // ignore (pushes all GP registoers onto the stack)
492 } else if (name[name.length() - 1] == 'm') {
499 if (name.find("CALL") != name.npos) {
500 if (name.find("ADJ") != name.npos) {
501 // ignore (not a call)
502 } else if (name.find("SYSCALL") != name.npos) {
503 // ignore (doesn't go anywhere we know about)
504 } else if (name.find("VMCALL") != name.npos) {
505 // ignore (rather different semantics than a regular call)
506 } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
513 if (name.find("RET") != name.npos) {
525 /////////////////////////////////////////////////////
526 // Support functions for handling ARM instructions //
527 /////////////////////////////////////////////////////
529 #define SET(flag) { type->set(flag); return 0; }
531 #define REG(str) if (name == str) SET("kOperandTypeRegister");
532 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
534 #define MISC(str, type) if (name == str) SET(type);
536 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
537 /// actually its type) and translates it into an operand type
539 /// @arg type - The type object to set
540 /// @arg name - The name of the operand
541 static int ARMFlagFromOpName(LiteralConstantEmitter *type,
542 const std::string &name) {
558 IMM("bf_inv_mask_imm");
559 IMM("jtblock_operand");
561 IMM("cpinst_operand");
571 IMM("jt2block_operand");
576 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
577 MISC("so_reg", "kOperandTypeARMSoReg"); // R, R, I
578 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
579 MISC("so_imm", "kOperandTypeARMSoImm"); // I
580 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I
581 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
582 MISC("pred", "kOperandTypeARMPredicate"); // I, R
583 MISC("it_pred", "kOperandTypeARMPredicate"); // I
584 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
585 MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I
586 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
587 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
588 MISC("addrmode4", "kOperandTypeARMAddrMode4"); // R, I
589 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
590 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
591 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
592 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
593 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
594 MISC("it_mask", "kOperandTypeThumbITMask"); // I
595 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
596 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
597 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
598 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
599 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
600 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
602 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I
603 MISC("t_addrmode_s1", "kOperandTypeThumbAddrModeS1"); // R, I, R
604 MISC("t_addrmode_s2", "kOperandTypeThumbAddrModeS2"); // R, I, R
605 MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4"); // R, I, R
606 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
607 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
623 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
624 /// the appropriate flags to their descriptors
626 /// @operandFlags - A reference the array of operand flag objects
627 /// @inst - The instruction to use as a source of information
628 static void ARMPopulateOperands(
629 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
630 const CodeGenInstruction &inst) {
631 if (!inst.TheDef->isSubClassOf("InstARM") &&
632 !inst.TheDef->isSubClassOf("InstThumb"))
636 unsigned int numOperands = inst.OperandList.size();
638 if (numOperands > EDIS_MAX_OPERANDS) {
639 errs() << "numOperands == " << numOperands << " > " <<
640 EDIS_MAX_OPERANDS << '\n';
641 llvm_unreachable("Too many operands");
644 for (index = 0; index < numOperands; ++index) {
645 const CodeGenInstruction::OperandInfo &operandInfo =
646 inst.OperandList[index];
647 Record &rec = *operandInfo.Rec;
649 if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
650 errs() << "Operand type: " << rec.getName() << '\n';
651 errs() << "Operand name: " << operandInfo.Name << '\n';
652 errs() << "Instruction mame: " << inst.TheDef->getName() << '\n';
653 llvm_unreachable("Unhandled type");
658 #define BRANCH(target) { \
659 instType.set("kInstructionTypeBranch"); \
660 DECORATE1(target, "kOperandFlagTarget"); \
663 /// ARMExtractSemantics - Performs various checks on the name of an ARM
664 /// instruction to determine what sort of an instruction it is and then adds
665 /// the appropriate flags to the instruction and its operands
667 /// @arg instType - A reference to the type for the instruction as a whole
668 /// @arg operandTypes - A reference to the array of operand type object pointers
669 /// @arg operandFlags - A reference to the array of operand flag object pointers
670 /// @arg inst - A reference to the original instruction
671 static void ARMExtractSemantics(
672 LiteralConstantEmitter &instType,
673 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
674 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
675 const CodeGenInstruction &inst) {
676 const std::string &name = inst.TheDef->getName();
678 if (name == "tBcc" ||
687 if (name == "tBLr9" ||
688 name == "BLr9_pred" ||
689 name == "tBLXi_r9" ||
690 name == "tBLXr_r9" ||
697 opIndex = inst.getOperandNamed("func");
698 if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
699 operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
705 /// populateInstInfo - Fills an array of InstInfos with information about each
706 /// instruction in a target
708 /// @arg infoArray - The array of InstInfo objects to populate
709 /// @arg target - The CodeGenTarget to use as a source of instructions
710 static void populateInstInfo(CompoundConstantEmitter &infoArray,
711 CodeGenTarget &target) {
712 const std::vector<const CodeGenInstruction*> &numberedInstructions =
713 target.getInstructionsByEnumValue();
716 unsigned int numInstructions = numberedInstructions.size();
718 for (index = 0; index < numInstructions; ++index) {
719 const CodeGenInstruction& inst = *numberedInstructions[index];
721 CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
722 infoArray.addEntry(infoStruct);
724 LiteralConstantEmitter *instType = new LiteralConstantEmitter;
725 infoStruct->addEntry(instType);
727 LiteralConstantEmitter *numOperandsEmitter =
728 new LiteralConstantEmitter(inst.OperandList.size());
729 infoStruct->addEntry(numOperandsEmitter);
731 CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
732 infoStruct->addEntry(operandTypeArray);
734 LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
736 CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
737 infoStruct->addEntry(operandFlagArray);
739 FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
741 for (unsigned operandIndex = 0;
742 operandIndex < EDIS_MAX_OPERANDS;
744 operandTypes[operandIndex] = new LiteralConstantEmitter;
745 operandTypeArray->addEntry(operandTypes[operandIndex]);
747 operandFlags[operandIndex] = new FlagsConstantEmitter;
748 operandFlagArray->addEntry(operandFlags[operandIndex]);
751 unsigned numSyntaxes = 0;
753 if (target.getName() == "X86") {
754 X86PopulateOperands(operandTypes, inst);
755 X86ExtractSemantics(*instType, operandFlags, inst);
758 else if (target.getName() == "ARM") {
759 ARMPopulateOperands(operandTypes, inst);
760 ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
764 CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
766 infoStruct->addEntry(operandOrderArray);
768 for (unsigned syntaxIndex = 0;
769 syntaxIndex < EDIS_MAX_SYNTAXES;
771 CompoundConstantEmitter *operandOrder =
772 new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
774 operandOrderArray->addEntry(operandOrder);
776 if (syntaxIndex < numSyntaxes) {
777 populateOperandOrder(operandOrder, inst, syntaxIndex);
785 static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
786 EnumEmitter operandTypes("OperandTypes");
787 operandTypes.addEntry("kOperandTypeNone");
788 operandTypes.addEntry("kOperandTypeImmediate");
789 operandTypes.addEntry("kOperandTypeRegister");
790 operandTypes.addEntry("kOperandTypeX86Memory");
791 operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
792 operandTypes.addEntry("kOperandTypeX86PCRelative");
793 operandTypes.addEntry("kOperandTypeARMBranchTarget");
794 operandTypes.addEntry("kOperandTypeARMSoReg");
795 operandTypes.addEntry("kOperandTypeARMSoImm");
796 operandTypes.addEntry("kOperandTypeARMSoImm2Part");
797 operandTypes.addEntry("kOperandTypeARMPredicate");
798 operandTypes.addEntry("kOperandTypeARMAddrMode2");
799 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
800 operandTypes.addEntry("kOperandTypeARMAddrMode3");
801 operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
802 operandTypes.addEntry("kOperandTypeARMAddrMode4");
803 operandTypes.addEntry("kOperandTypeARMAddrMode5");
804 operandTypes.addEntry("kOperandTypeARMAddrMode6");
805 operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
806 operandTypes.addEntry("kOperandTypeARMAddrModePC");
807 operandTypes.addEntry("kOperandTypeARMRegisterList");
808 operandTypes.addEntry("kOperandTypeARMTBAddrMode");
809 operandTypes.addEntry("kOperandTypeThumbITMask");
810 operandTypes.addEntry("kOperandTypeThumbAddrModeS1");
811 operandTypes.addEntry("kOperandTypeThumbAddrModeS2");
812 operandTypes.addEntry("kOperandTypeThumbAddrModeS4");
813 operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
814 operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
815 operandTypes.addEntry("kOperandTypeThumb2SoReg");
816 operandTypes.addEntry("kOperandTypeThumb2SoImm");
817 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
818 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
819 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
820 operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
821 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
822 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
823 operandTypes.emit(o, i);
827 EnumEmitter operandFlags("OperandFlags");
828 operandFlags.addEntry("kOperandFlagSource");
829 operandFlags.addEntry("kOperandFlagTarget");
830 operandFlags.emitAsFlags(o, i);
834 EnumEmitter instructionTypes("InstructionTypes");
835 instructionTypes.addEntry("kInstructionTypeNone");
836 instructionTypes.addEntry("kInstructionTypeMove");
837 instructionTypes.addEntry("kInstructionTypeBranch");
838 instructionTypes.addEntry("kInstructionTypePush");
839 instructionTypes.addEntry("kInstructionTypePop");
840 instructionTypes.addEntry("kInstructionTypeCall");
841 instructionTypes.addEntry("kInstructionTypeReturn");
842 instructionTypes.emit(o, i);
847 void EDEmitter::run(raw_ostream &o) {
850 CompoundConstantEmitter infoArray;
851 CodeGenTarget target;
853 populateInstInfo(infoArray, target);
855 emitCommonEnums(o, i);
857 o << "namespace {\n";
859 o << "llvm::EDInstInfo instInfo" << target.getName().c_str() << "[] = ";
860 infoArray.emit(o, i);