1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of each
11 // instruction in a format that the enhanced disassembler can use to tokenize
12 // and parse instructions.
14 //===----------------------------------------------------------------------===//
16 #include "EDEmitter.h"
18 #include "AsmWriterInst.h"
19 #include "CodeGenTarget.h"
22 #include "llvm/MC/EDInstInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/Format.h"
25 #include "llvm/Support/raw_ostream.h"
33 ///////////////////////////////////////////////////////////
34 // Support classes for emitting nested C data structures //
35 ///////////////////////////////////////////////////////////
42 std::vector<std::string> Entries;
44 EnumEmitter(const char *N) : Name(N) {
46 int addEntry(const char *e) {
47 Entries.push_back(std::string(e));
48 return Entries.size() - 1;
50 void emit(raw_ostream &o, unsigned int &i) {
51 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
54 unsigned int index = 0;
55 unsigned int numEntries = Entries.size();
56 for (index = 0; index < numEntries; ++index) {
57 o.indent(i) << Entries[index];
58 if (index < (numEntries - 1))
64 o.indent(i) << "};" << "\n";
67 void emitAsFlags(raw_ostream &o, unsigned int &i) {
68 o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
71 unsigned int index = 0;
72 unsigned int numEntries = Entries.size();
73 unsigned int flag = 1;
74 for (index = 0; index < numEntries; ++index) {
75 o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
76 if (index < (numEntries - 1))
83 o.indent(i) << "};" << "\n";
90 typedef std::pair<const char*, const char*> member;
91 std::vector< member > Members;
93 StructEmitter(const char *N) : Name(N) {
95 void addMember(const char *t, const char *n) {
99 void emit(raw_ostream &o, unsigned int &i) {
100 o.indent(i) << "struct " << Name.c_str() << " {" << "\n";
103 unsigned int index = 0;
104 unsigned int numMembers = Members.size();
105 for (index = 0; index < numMembers; ++index) {
106 o.indent(i) << Members[index].first << " ";
107 o.indent(i) << Members[index].second << ";" << "\n";
111 o.indent(i) << "};" << "\n";
115 class ConstantEmitter {
117 virtual ~ConstantEmitter() { }
118 virtual void emit(raw_ostream &o, unsigned int &i) = 0;
121 class LiteralConstantEmitter : public ConstantEmitter {
129 LiteralConstantEmitter(const char *string) :
133 LiteralConstantEmitter(int number = 0) :
137 void set(const char *string) {
142 void set(int number) {
147 bool is(const char *string) {
148 return !strcmp(String, string);
150 void emit(raw_ostream &o, unsigned int &i) {
158 class CompoundConstantEmitter : public ConstantEmitter {
160 unsigned int Padding;
161 std::vector<ConstantEmitter *> Entries;
163 CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
165 CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
166 Entries.push_back(e);
170 ~CompoundConstantEmitter() {
171 while (Entries.size()) {
172 ConstantEmitter *entry = Entries.back();
177 void emit(raw_ostream &o, unsigned int &i) {
182 unsigned int numEntries = Entries.size();
184 unsigned int numToPrint;
187 if (numEntries > Padding) {
188 fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
189 llvm_unreachable("More entries than padding");
191 numToPrint = Padding;
193 numToPrint = numEntries;
196 for (index = 0; index < numToPrint; ++index) {
198 if (index < numEntries)
199 Entries[index]->emit(o, i);
203 if (index < (numToPrint - 1))
213 class FlagsConstantEmitter : public ConstantEmitter {
215 std::vector<std::string> Flags;
217 FlagsConstantEmitter() {
219 FlagsConstantEmitter &addEntry(const char *f) {
220 Flags.push_back(std::string(f));
223 void emit(raw_ostream &o, unsigned int &i) {
225 unsigned int numFlags = Flags.size();
229 for (index = 0; index < numFlags; ++index) {
230 o << Flags[index].c_str();
231 if (index < (numFlags - 1))
238 EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
241 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its
242 /// AsmWriterInst for the desired assembly syntax, giving an ordered list of
243 /// operands in the order they appear in the printed instruction. Then, for
244 /// each entry in that list, determines the index of the same operand in the
245 /// CodeGenInstruction, and emits the resulting mapping into an array, filling
246 /// in unused slots with -1.
248 /// @arg operandOrder - The array that will be populated with the operand
249 /// mapping. Each entry will contain -1 (invalid index
250 /// into the operands present in the AsmString) or a number
251 /// representing an index in the operand descriptor array.
252 /// @arg inst - The instruction to use when looking up the operands
253 /// @arg syntax - The syntax to use, according to LLVM's enumeration
254 void populateOperandOrder(CompoundConstantEmitter *operandOrder,
255 const CodeGenInstruction &inst,
257 unsigned int numArgs = 0;
259 AsmWriterInst awInst(inst, syntax, -1, -1);
261 std::vector<AsmWriterOperand>::iterator operandIterator;
263 for (operandIterator = awInst.Operands.begin();
264 operandIterator != awInst.Operands.end();
266 if (operandIterator->OperandType ==
267 AsmWriterOperand::isMachineInstrOperand) {
268 operandOrder->addEntry(
269 new LiteralConstantEmitter(operandIterator->CGIOpNo));
275 /////////////////////////////////////////////////////
276 // Support functions for handling X86 instructions //
277 /////////////////////////////////////////////////////
279 #define SET(flag) { type->set(flag); return 0; }
281 #define REG(str) if (name == str) SET("kOperandTypeRegister");
282 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
283 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
284 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
285 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
287 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is
288 /// actually its type) and translates it into an operand type
290 /// @arg flags - The type object to set
291 /// @arg name - The name of the operand
292 static int X86TypeFromOpName(LiteralConstantEmitter *type,
293 const std::string &name) {
355 PCR("i64i32imm_pcrel");
374 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
375 /// the appropriate flags to their descriptors
377 /// @operandFlags - A reference the array of operand flag objects
378 /// @inst - The instruction to use as a source of information
379 static void X86PopulateOperands(
380 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
381 const CodeGenInstruction &inst) {
382 if (!inst.TheDef->isSubClassOf("X86Inst"))
386 unsigned int numOperands = inst.OperandList.size();
388 for (index = 0; index < numOperands; ++index) {
389 const CodeGenInstruction::OperandInfo &operandInfo =
390 inst.OperandList[index];
391 Record &rec = *operandInfo.Rec;
393 if (X86TypeFromOpName(operandTypes[index], rec.getName())) {
394 errs() << "Operand type: " << rec.getName().c_str() << "\n";
395 errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
396 errs() << "Instruction mame: " << inst.TheDef->getName().c_str() << "\n";
397 llvm_unreachable("Unhandled type");
402 /// decorate1 - Decorates a named operand with a new flag
404 /// @operandFlags - The array of operand flag objects, which don't have names
405 /// @inst - The CodeGenInstruction, which provides a way to translate
406 /// between names and operand indices
407 /// @opName - The name of the operand
408 /// @flag - The name of the flag to add
409 static inline void decorate1(
410 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
411 const CodeGenInstruction &inst,
413 const char *opFlag) {
416 opIndex = inst.getOperandNamed(std::string(opName));
418 operandFlags[opIndex]->addEntry(opFlag);
421 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
423 #define MOV(source, target) { \
424 instType.set("kInstructionTypeMove"); \
425 DECORATE1(source, "kOperandFlagSource"); \
426 DECORATE1(target, "kOperandFlagTarget"); \
429 #define BRANCH(target) { \
430 instType.set("kInstructionTypeBranch"); \
431 DECORATE1(target, "kOperandFlagTarget"); \
434 #define PUSH(source) { \
435 instType.set("kInstructionTypePush"); \
436 DECORATE1(source, "kOperandFlagSource"); \
439 #define POP(target) { \
440 instType.set("kInstructionTypePop"); \
441 DECORATE1(target, "kOperandFlagTarget"); \
444 #define CALL(target) { \
445 instType.set("kInstructionTypeCall"); \
446 DECORATE1(target, "kOperandFlagTarget"); \
450 instType.set("kInstructionTypeReturn"); \
453 /// X86ExtractSemantics - Performs various checks on the name of an X86
454 /// instruction to determine what sort of an instruction it is and then adds
455 /// the appropriate flags to the instruction and its operands
457 /// @arg instType - A reference to the type for the instruction as a whole
458 /// @arg operandFlags - A reference to the array of operand flag object pointers
459 /// @arg inst - A reference to the original instruction
460 static void X86ExtractSemantics(
461 LiteralConstantEmitter &instType,
462 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
463 const CodeGenInstruction &inst) {
464 const std::string &name = inst.TheDef->getName();
466 if (name.find("MOV") != name.npos) {
467 if (name.find("MOV_V") != name.npos) {
468 // ignore (this is a pseudoinstruction)
469 } else if (name.find("MASK") != name.npos) {
470 // ignore (this is a masking move)
471 } else if (name.find("r0") != name.npos) {
472 // ignore (this is a pseudoinstruction)
473 } else if (name.find("PS") != name.npos ||
474 name.find("PD") != name.npos) {
475 // ignore (this is a shuffling move)
476 } else if (name.find("MOVS") != name.npos) {
477 // ignore (this is a string move)
478 } else if (name.find("_F") != name.npos) {
479 // TODO handle _F moves to ST(0)
480 } else if (name.find("a") != name.npos) {
481 // TODO handle moves to/from %ax
482 } else if (name.find("CMOV") != name.npos) {
484 } else if (name.find("PC") != name.npos) {
491 if (name.find("JMP") != name.npos ||
492 name.find("J") == 0) {
493 if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
500 if (name.find("PUSH") != name.npos) {
501 if (name.find("FS") != name.npos ||
502 name.find("GS") != name.npos) {
503 instType.set("kInstructionTypePush");
504 // TODO add support for fixed operands
505 } else if (name.find("F") != name.npos) {
506 // ignore (this pushes onto the FP stack)
507 } else if (name.find("A") != name.npos) {
508 // ignore (pushes all GP registoers onto the stack)
509 } else if (name[name.length() - 1] == 'm') {
511 } else if (name.find("i") != name.npos) {
518 if (name.find("POP") != name.npos) {
519 if (name.find("POPCNT") != name.npos) {
520 // ignore (not a real pop)
521 } else if (name.find("FS") != name.npos ||
522 name.find("GS") != name.npos) {
523 instType.set("kInstructionTypePop");
524 // TODO add support for fixed operands
525 } else if (name.find("F") != name.npos) {
526 // ignore (this pops from the FP stack)
527 } else if (name.find("A") != name.npos) {
528 // ignore (pushes all GP registoers onto the stack)
529 } else if (name[name.length() - 1] == 'm') {
536 if (name.find("CALL") != name.npos) {
537 if (name.find("ADJ") != name.npos) {
538 // ignore (not a call)
539 } else if (name.find("SYSCALL") != name.npos) {
540 // ignore (doesn't go anywhere we know about)
541 } else if (name.find("VMCALL") != name.npos) {
542 // ignore (rather different semantics than a regular call)
543 } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
550 if (name.find("RET") != name.npos) {
562 /////////////////////////////////////////////////////
563 // Support functions for handling ARM instructions //
564 /////////////////////////////////////////////////////
566 #define SET(flag) { type->set(flag); return 0; }
568 #define REG(str) if (name == str) SET("kOperandTypeRegister");
569 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
571 #define MISC(str, type) if (name == str) SET(type);
573 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
574 /// actually its type) and translates it into an operand type
576 /// @arg type - The type object to set
577 /// @arg name - The name of the operand
578 static int ARMFlagFromOpName(LiteralConstantEmitter *type,
579 const std::string &name) {
595 IMM("bf_inv_mask_imm");
596 IMM("jtblock_operand");
598 IMM("cpinst_operand");
607 IMM("jt2block_operand");
612 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
613 MISC("so_reg", "kOperandTypeARMSoReg"); // R, R, I
614 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
615 MISC("so_imm", "kOperandTypeARMSoImm"); // I
616 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I
617 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
618 MISC("pred", "kOperandTypeARMPredicate"); // I, R
619 MISC("it_pred", "kOperandTypeARMPredicate"); // I
620 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
621 MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I
622 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
623 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
624 MISC("addrmode4", "kOperandTypeARMAddrMode4"); // R, I
625 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
626 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
627 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
628 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
629 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
630 MISC("it_mask", "kOperandTypeThumbITMask"); // I
631 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
632 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
633 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
634 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
635 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
636 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
638 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I
639 MISC("t_addrmode_s1", "kOperandTypeThumbAddrModeS1"); // R, I, R
640 MISC("t_addrmode_s2", "kOperandTypeThumbAddrModeS2"); // R, I, R
641 MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4"); // R, I, R
642 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
643 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
659 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
660 /// the appropriate flags to their descriptors
662 /// @operandFlags - A reference the array of operand flag objects
663 /// @inst - The instruction to use as a source of information
664 static void ARMPopulateOperands(
665 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
666 const CodeGenInstruction &inst) {
667 if (!inst.TheDef->isSubClassOf("InstARM") &&
668 !inst.TheDef->isSubClassOf("InstThumb"))
672 unsigned int numOperands = inst.OperandList.size();
674 if (numOperands > EDIS_MAX_OPERANDS) {
675 errs() << "numOperands == " << numOperands << " > " <<
676 EDIS_MAX_OPERANDS << '\n';
677 llvm_unreachable("Too many operands");
680 for (index = 0; index < numOperands; ++index) {
681 const CodeGenInstruction::OperandInfo &operandInfo =
682 inst.OperandList[index];
683 Record &rec = *operandInfo.Rec;
685 if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
686 errs() << "Operand type: " << rec.getName() << '\n';
687 errs() << "Operand name: " << operandInfo.Name << '\n';
688 errs() << "Instruction mame: " << inst.TheDef->getName() << '\n';
689 llvm_unreachable("Unhandled type");
694 #define BRANCH(target) { \
695 instType.set("kInstructionTypeBranch"); \
696 DECORATE1(target, "kOperandFlagTarget"); \
699 /// ARMExtractSemantics - Performs various checks on the name of an ARM
700 /// instruction to determine what sort of an instruction it is and then adds
701 /// the appropriate flags to the instruction and its operands
703 /// @arg instType - A reference to the type for the instruction as a whole
704 /// @arg operandTypes - A reference to the array of operand type object pointers
705 /// @arg operandFlags - A reference to the array of operand flag object pointers
706 /// @arg inst - A reference to the original instruction
707 static void ARMExtractSemantics(
708 LiteralConstantEmitter &instType,
709 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
710 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
711 const CodeGenInstruction &inst) {
712 const std::string &name = inst.TheDef->getName();
714 if (name == "tBcc" ||
723 if (name == "tBLr9" ||
724 name == "BLr9_pred" ||
725 name == "tBLXi_r9" ||
726 name == "tBLXr_r9" ||
733 opIndex = inst.getOperandNamed("func");
734 if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
735 operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
741 /// populateInstInfo - Fills an array of InstInfos with information about each
742 /// instruction in a target
744 /// @arg infoArray - The array of InstInfo objects to populate
745 /// @arg target - The CodeGenTarget to use as a source of instructions
746 static void populateInstInfo(CompoundConstantEmitter &infoArray,
747 CodeGenTarget &target) {
748 const std::vector<const CodeGenInstruction*> &numberedInstructions =
749 target.getInstructionsByEnumValue();
752 unsigned int numInstructions = numberedInstructions.size();
754 for (index = 0; index < numInstructions; ++index) {
755 const CodeGenInstruction& inst = *numberedInstructions[index];
757 CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
758 infoArray.addEntry(infoStruct);
760 LiteralConstantEmitter *instType = new LiteralConstantEmitter;
761 infoStruct->addEntry(instType);
763 LiteralConstantEmitter *numOperandsEmitter =
764 new LiteralConstantEmitter(inst.OperandList.size());
765 infoStruct->addEntry(numOperandsEmitter);
767 CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
768 infoStruct->addEntry(operandTypeArray);
770 LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
772 CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
773 infoStruct->addEntry(operandFlagArray);
775 FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
777 for (unsigned operandIndex = 0;
778 operandIndex < EDIS_MAX_OPERANDS;
780 operandTypes[operandIndex] = new LiteralConstantEmitter;
781 operandTypeArray->addEntry(operandTypes[operandIndex]);
783 operandFlags[operandIndex] = new FlagsConstantEmitter;
784 operandFlagArray->addEntry(operandFlags[operandIndex]);
787 unsigned numSyntaxes = 0;
789 if (target.getName() == "X86") {
790 X86PopulateOperands(operandTypes, inst);
791 X86ExtractSemantics(*instType, operandFlags, inst);
794 else if (target.getName() == "ARM") {
795 ARMPopulateOperands(operandTypes, inst);
796 ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
800 CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
802 infoStruct->addEntry(operandOrderArray);
804 for (unsigned syntaxIndex = 0;
805 syntaxIndex < EDIS_MAX_SYNTAXES;
807 CompoundConstantEmitter *operandOrder =
808 new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
810 operandOrderArray->addEntry(operandOrder);
812 if (syntaxIndex < numSyntaxes) {
813 populateOperandOrder(operandOrder, inst, syntaxIndex);
821 static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
822 EnumEmitter operandTypes("OperandTypes");
823 operandTypes.addEntry("kOperandTypeNone");
824 operandTypes.addEntry("kOperandTypeImmediate");
825 operandTypes.addEntry("kOperandTypeRegister");
826 operandTypes.addEntry("kOperandTypeX86Memory");
827 operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
828 operandTypes.addEntry("kOperandTypeX86PCRelative");
829 operandTypes.addEntry("kOperandTypeARMBranchTarget");
830 operandTypes.addEntry("kOperandTypeARMSoReg");
831 operandTypes.addEntry("kOperandTypeARMSoImm");
832 operandTypes.addEntry("kOperandTypeARMSoImm2Part");
833 operandTypes.addEntry("kOperandTypeARMPredicate");
834 operandTypes.addEntry("kOperandTypeARMAddrMode2");
835 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
836 operandTypes.addEntry("kOperandTypeARMAddrMode3");
837 operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
838 operandTypes.addEntry("kOperandTypeARMAddrMode4");
839 operandTypes.addEntry("kOperandTypeARMAddrMode5");
840 operandTypes.addEntry("kOperandTypeARMAddrMode6");
841 operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
842 operandTypes.addEntry("kOperandTypeARMAddrModePC");
843 operandTypes.addEntry("kOperandTypeARMRegisterList");
844 operandTypes.addEntry("kOperandTypeARMTBAddrMode");
845 operandTypes.addEntry("kOperandTypeThumbITMask");
846 operandTypes.addEntry("kOperandTypeThumbAddrModeS1");
847 operandTypes.addEntry("kOperandTypeThumbAddrModeS2");
848 operandTypes.addEntry("kOperandTypeThumbAddrModeS4");
849 operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
850 operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
851 operandTypes.addEntry("kOperandTypeThumb2SoReg");
852 operandTypes.addEntry("kOperandTypeThumb2SoImm");
853 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
854 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
855 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
856 operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
857 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
858 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
859 operandTypes.emit(o, i);
863 EnumEmitter operandFlags("OperandFlags");
864 operandFlags.addEntry("kOperandFlagSource");
865 operandFlags.addEntry("kOperandFlagTarget");
866 operandFlags.emitAsFlags(o, i);
870 EnumEmitter instructionTypes("InstructionTypes");
871 instructionTypes.addEntry("kInstructionTypeNone");
872 instructionTypes.addEntry("kInstructionTypeMove");
873 instructionTypes.addEntry("kInstructionTypeBranch");
874 instructionTypes.addEntry("kInstructionTypePush");
875 instructionTypes.addEntry("kInstructionTypePop");
876 instructionTypes.addEntry("kInstructionTypeCall");
877 instructionTypes.addEntry("kInstructionTypeReturn");
878 instructionTypes.emit(o, i);
883 void EDEmitter::run(raw_ostream &o) {
886 CompoundConstantEmitter infoArray;
887 CodeGenTarget target;
889 populateInstInfo(infoArray, target);
891 emitCommonEnums(o, i);
893 o << "namespace {\n";
895 o << "llvm::EDInstInfo instInfo" << target.getName().c_str() << "[] = ";
896 infoArray.emit(o, i);