1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits code for use by the "fast" instruction
11 // selection algorithm. See the comments at the top of
12 // lib/CodeGen/SelectionDAG/FastISel.cpp for background.
14 // This file scans through the target's tablegen instruction-info files
15 // and extracts instructions with obvious-looking patterns, and it emits
16 // code to look up these instructions by type and operator.
18 //===----------------------------------------------------------------------===//
20 #include "FastISelEmitter.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/Streams.h"
24 #include "llvm/ADT/VectorExtras.h"
29 /// InstructionMemo - This class holds additional information about an
30 /// instruction needed to emit code for it.
32 struct InstructionMemo {
34 const CodeGenRegisterClass *RC;
35 unsigned char SubRegNo;
36 std::vector<std::string>* PhysRegs;
39 /// OperandsSignature - This class holds a description of a list of operand
40 /// types. It has utility methods for emitting text based on the operands.
42 struct OperandsSignature {
43 std::vector<std::string> Operands;
45 bool operator<(const OperandsSignature &O) const {
46 return Operands < O.Operands;
49 bool empty() const { return Operands.empty(); }
51 /// initialize - Examine the given pattern and initialize the contents
52 /// of the Operands array accordingly. Return true if all the operands
53 /// are supported, false otherwise.
55 bool initialize(TreePatternNode *InstPatNode,
56 const CodeGenTarget &Target,
57 MVT::SimpleValueType VT) {
58 if (!InstPatNode->isLeaf() &&
59 InstPatNode->getOperator()->getName() == "imm") {
60 Operands.push_back("i");
63 if (!InstPatNode->isLeaf() &&
64 InstPatNode->getOperator()->getName() == "fpimm") {
65 Operands.push_back("f");
69 const CodeGenRegisterClass *DstRC = 0;
71 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
72 TreePatternNode *Op = InstPatNode->getChild(i);
73 // For now, filter out any operand with a predicate.
74 if (!Op->getPredicateFns().empty())
76 // For now, filter out any operand with multiple values.
77 if (Op->getExtTypes().size() != 1)
79 // For now, all the operands must have the same type.
80 if (Op->getTypeNum(0) != VT)
83 if (Op->getOperator()->getName() == "imm") {
84 Operands.push_back("i");
87 if (Op->getOperator()->getName() == "fpimm") {
88 Operands.push_back("f");
91 // For now, ignore other non-leaf nodes.
94 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
97 Record *OpLeafRec = OpDI->getDef();
98 // For now, the only other thing we accept is register operands.
100 const CodeGenRegisterClass *RC = 0;
101 if (OpLeafRec->isSubClassOf("RegisterClass"))
102 RC = &Target.getRegisterClass(OpLeafRec);
103 else if (OpLeafRec->isSubClassOf("Register"))
104 RC = Target.getRegisterClassForRegister(OpLeafRec);
107 // For now, require the register operands' register classes to all
111 // For now, all the operands must have the same register class.
117 Operands.push_back("r");
122 void PrintParameters(std::ostream &OS) const {
123 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
124 if (Operands[i] == "r") {
125 OS << "unsigned Op" << i;
126 } else if (Operands[i] == "i") {
127 OS << "uint64_t imm" << i;
128 } else if (Operands[i] == "f") {
129 OS << "ConstantFP *f" << i;
131 assert("Unknown operand kind!");
139 void PrintArguments(std::ostream &OS,
140 const std::vector<std::string>& PR) const {
141 assert(PR.size() == Operands.size());
142 bool PrintedArg = false;
143 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
145 // Implicit physical register operand.
150 if (Operands[i] == "r") {
153 } else if (Operands[i] == "i") {
156 } else if (Operands[i] == "f") {
160 assert("Unknown operand kind!");
166 void PrintArguments(std::ostream &OS) const {
167 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
168 if (Operands[i] == "r") {
170 } else if (Operands[i] == "i") {
172 } else if (Operands[i] == "f") {
175 assert("Unknown operand kind!");
184 void PrintManglingSuffix(std::ostream &OS,
185 const std::vector<std::string>& PR) const {
186 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
188 // Implicit physical register operand. e.g. Instruction::Mul expect to
189 // select to a binary op. On x86, mul may take a single operand with
190 // the other operand being implicit. We must emit something that looks
191 // like a binary instruction except for the very inner FastEmitInst_*
198 void PrintManglingSuffix(std::ostream &OS) const {
199 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
206 typedef std::map<std::string, InstructionMemo> PredMap;
207 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
208 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
209 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
210 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> OperandsOpcodeTypeRetPredMap;
212 OperandsOpcodeTypeRetPredMap SimplePatterns;
217 explicit FastISelMap(std::string InstNS);
219 void CollectPatterns(CodeGenDAGPatterns &CGP);
220 void PrintClass(std::ostream &OS);
221 void PrintFunctionDefinitions(std::ostream &OS);
226 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
227 return CGP.getSDNodeInfo(Op).getEnumName();
230 static std::string getLegalCName(std::string OpName) {
231 std::string::size_type pos = OpName.find("::");
232 if (pos != std::string::npos)
233 OpName.replace(pos, 2, "_");
237 FastISelMap::FastISelMap(std::string instns)
241 void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
242 const CodeGenTarget &Target = CGP.getTargetInfo();
244 // Determine the target's namespace name.
245 InstNS = Target.getInstNamespace() + "::";
246 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
248 // Scan through all the patterns and record the simple ones.
249 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
250 E = CGP.ptm_end(); I != E; ++I) {
251 const PatternToMatch &Pattern = *I;
253 // For now, just look at Instructions, so that we don't have to worry
254 // about emitting multiple instructions for a pattern.
255 TreePatternNode *Dst = Pattern.getDstPattern();
256 if (Dst->isLeaf()) continue;
257 Record *Op = Dst->getOperator();
258 if (!Op->isSubClassOf("Instruction"))
260 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName());
261 if (II.OperandList.empty())
264 // For now, ignore multi-instruction patterns.
265 bool MultiInsts = false;
266 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
267 TreePatternNode *ChildOp = Dst->getChild(i);
268 if (ChildOp->isLeaf())
270 if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
278 // For now, ignore instructions where the first operand is not an
280 const CodeGenRegisterClass *DstRC = 0;
281 unsigned SubRegNo = ~0;
282 if (Op->getName() != "EXTRACT_SUBREG") {
283 Record *Op0Rec = II.OperandList[0].Rec;
284 if (!Op0Rec->isSubClassOf("RegisterClass"))
286 DstRC = &Target.getRegisterClass(Op0Rec);
290 SubRegNo = static_cast<IntInit*>(
291 Dst->getChild(1)->getLeafValue())->getValue();
294 // Inspect the pattern.
295 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
296 if (!InstPatNode) continue;
297 if (InstPatNode->isLeaf()) continue;
299 Record *InstPatOp = InstPatNode->getOperator();
300 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
301 MVT::SimpleValueType RetVT = InstPatNode->getTypeNum(0);
302 MVT::SimpleValueType VT = RetVT;
303 if (InstPatNode->getNumChildren())
304 VT = InstPatNode->getChild(0)->getTypeNum(0);
306 // For now, filter out instructions which just set a register to
307 // an Operand or an immediate, like MOV32ri.
308 if (InstPatOp->isSubClassOf("Operand"))
311 // For now, filter out any instructions with predicates.
312 if (!InstPatNode->getPredicateFns().empty())
315 // Check all the operands.
316 OperandsSignature Operands;
317 if (!Operands.initialize(InstPatNode, Target, VT))
320 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
321 if (!InstPatNode->isLeaf() &&
322 (InstPatNode->getOperator()->getName() == "imm" ||
323 InstPatNode->getOperator()->getName() == "fpimmm"))
324 PhysRegInputs->push_back("");
325 else if (!InstPatNode->isLeaf()) {
326 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
327 TreePatternNode *Op = InstPatNode->getChild(i);
329 PhysRegInputs->push_back("");
333 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
334 Record *OpLeafRec = OpDI->getDef();
336 if (OpLeafRec->isSubClassOf("Register")) {
337 PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
338 "Namespace")->getValue())->getValue();
341 std::vector<CodeGenRegister> Regs = Target.getRegisters();
342 for (unsigned i = 0; i < Regs.size(); ++i) {
343 if (Regs[i].TheDef == OpLeafRec) {
344 PhysReg += Regs[i].getName();
350 PhysRegInputs->push_back(PhysReg);
353 PhysRegInputs->push_back("");
355 // Get the predicate that guards this pattern.
356 std::string PredicateCheck = Pattern.getPredicateCheck();
358 // Ok, we found a pattern that we can handle. Remember it.
359 InstructionMemo Memo = {
360 Pattern.getDstPattern()->getOperator()->getName(),
365 assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
366 "Duplicate pattern!");
367 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
371 void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
372 // Now emit code for all the patterns that we collected.
373 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
374 OE = SimplePatterns.end(); OI != OE; ++OI) {
375 const OperandsSignature &Operands = OI->first;
376 const OpcodeTypeRetPredMap &OTM = OI->second;
378 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
380 const std::string &Opcode = I->first;
381 const TypeRetPredMap &TM = I->second;
383 OS << "// FastEmit functions for " << Opcode << ".\n";
386 // Emit one function for each opcode,type pair.
387 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
389 MVT::SimpleValueType VT = TI->first;
390 const RetPredMap &RM = TI->second;
391 if (RM.size() != 1) {
392 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
394 MVT::SimpleValueType RetVT = RI->first;
395 const PredMap &PM = RI->second;
396 bool HasPred = false;
398 OS << "unsigned FastEmit_"
399 << getLegalCName(Opcode)
400 << "_" << getLegalCName(getName(VT))
401 << "_" << getLegalCName(getName(RetVT)) << "_";
402 Operands.PrintManglingSuffix(OS);
404 Operands.PrintParameters(OS);
407 // Emit code for each possible instruction. There may be
408 // multiple if there are subtarget concerns.
409 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
411 std::string PredicateCheck = PI->first;
412 const InstructionMemo &Memo = PI->second;
414 if (PredicateCheck.empty()) {
416 "Multiple instructions match, at least one has "
417 "a predicate and at least one doesn't!");
419 OS << " if (" + PredicateCheck + ") {\n";
424 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
425 if ((*Memo.PhysRegs)[i] != "")
426 OS << " TII.copyRegToReg(*MBB, MBB->end(), "
427 << (*Memo.PhysRegs)[i] << ", Op" << i << ", "
428 << "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
429 << (*Memo.PhysRegs)[i] << "), "
430 << "MRI.getRegClass(Op" << i << "));\n";
433 OS << " return FastEmitInst_";
434 if (Memo.SubRegNo == (unsigned char)~0) {
435 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
436 OS << "(" << InstNS << Memo.Name << ", ";
437 OS << InstNS << Memo.RC->getName() << "RegisterClass";
438 if (!Operands.empty())
440 Operands.PrintArguments(OS, *Memo.PhysRegs);
443 OS << "extractsubreg(Op0, ";
444 OS << (unsigned)Memo.SubRegNo;
452 // Return 0 if none of the predicates were satisfied.
454 OS << " return 0;\n";
459 // Emit one function for the type that demultiplexes on return type.
460 OS << "unsigned FastEmit_"
461 << getLegalCName(Opcode) << "_"
462 << getLegalCName(getName(VT)) << "_";
463 Operands.PrintManglingSuffix(OS);
464 OS << "(MVT::SimpleValueType RetVT";
465 if (!Operands.empty())
467 Operands.PrintParameters(OS);
468 OS << ") {\nswitch (RetVT) {\n";
469 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
471 MVT::SimpleValueType RetVT = RI->first;
472 OS << " case " << getName(RetVT) << ": return FastEmit_"
473 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
474 << "_" << getLegalCName(getName(RetVT)) << "_";
475 Operands.PrintManglingSuffix(OS);
477 Operands.PrintArguments(OS);
480 OS << " default: return 0;\n}\n}\n\n";
483 // Non-variadic return type.
484 OS << "unsigned FastEmit_"
485 << getLegalCName(Opcode) << "_"
486 << getLegalCName(getName(VT)) << "_";
487 Operands.PrintManglingSuffix(OS);
488 OS << "(MVT::SimpleValueType RetVT";
489 if (!Operands.empty())
491 Operands.PrintParameters(OS);
494 OS << " if (RetVT != " << getName(RM.begin()->first)
495 << ")\n return 0;\n";
497 const PredMap &PM = RM.begin()->second;
498 bool HasPred = false;
500 // Emit code for each possible instruction. There may be
501 // multiple if there are subtarget concerns.
502 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
504 std::string PredicateCheck = PI->first;
505 const InstructionMemo &Memo = PI->second;
507 if (PredicateCheck.empty()) {
509 "Multiple instructions match, at least one has "
510 "a predicate and at least one doesn't!");
512 OS << " if (" + PredicateCheck + ") {\n";
517 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
518 if ((*Memo.PhysRegs)[i] != "")
519 OS << " TII.copyRegToReg(*MBB, MBB->end(), "
520 << (*Memo.PhysRegs)[i] << ", Op" << i << ", "
521 << "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
522 << (*Memo.PhysRegs)[i] << "), "
523 << "MRI.getRegClass(Op" << i << "));\n";
526 OS << " return FastEmitInst_";
528 if (Memo.SubRegNo == (unsigned char)~0) {
529 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
530 OS << "(" << InstNS << Memo.Name << ", ";
531 OS << InstNS << Memo.RC->getName() << "RegisterClass";
532 if (!Operands.empty())
534 Operands.PrintArguments(OS, *Memo.PhysRegs);
537 OS << "extractsubreg(Op0, ";
538 OS << (unsigned)Memo.SubRegNo;
546 // Return 0 if none of the predicates were satisfied.
548 OS << " return 0;\n";
554 // Emit one function for the opcode that demultiplexes based on the type.
555 OS << "unsigned FastEmit_"
556 << getLegalCName(Opcode) << "_";
557 Operands.PrintManglingSuffix(OS);
558 OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT";
559 if (!Operands.empty())
561 Operands.PrintParameters(OS);
563 OS << " switch (VT) {\n";
564 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
566 MVT::SimpleValueType VT = TI->first;
567 std::string TypeName = getName(VT);
568 OS << " case " << TypeName << ": return FastEmit_"
569 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
570 Operands.PrintManglingSuffix(OS);
572 if (!Operands.empty())
574 Operands.PrintArguments(OS);
577 OS << " default: return 0;\n";
583 OS << "// Top-level FastEmit function.\n";
586 // Emit one function for the operand signature that demultiplexes based
587 // on opcode and type.
588 OS << "unsigned FastEmit_";
589 Operands.PrintManglingSuffix(OS);
590 OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode";
591 if (!Operands.empty())
593 Operands.PrintParameters(OS);
595 OS << " switch (Opcode) {\n";
596 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
598 const std::string &Opcode = I->first;
600 OS << " case " << Opcode << ": return FastEmit_"
601 << getLegalCName(Opcode) << "_";
602 Operands.PrintManglingSuffix(OS);
604 if (!Operands.empty())
606 Operands.PrintArguments(OS);
609 OS << " default: return 0;\n";
616 void FastISelEmitter::run(std::ostream &OS) {
617 const CodeGenTarget &Target = CGP.getTargetInfo();
619 // Determine the target's namespace name.
620 std::string InstNS = Target.getInstNamespace() + "::";
621 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
623 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
624 Target.getName() + " target", OS);
626 FastISelMap F(InstNS);
627 F.CollectPatterns(CGP);
628 F.PrintFunctionDefinitions(OS);
631 FastISelEmitter::FastISelEmitter(RecordKeeper &R)