1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits code for use by the "fast" instruction
11 // selection algorithm. See the comments at the top of
12 // lib/CodeGen/SelectionDAG/FastISel.cpp for background.
14 // This file scans through the target's tablegen instruction-info files
15 // and extracts instructions with obvious-looking patterns, and it emits
16 // code to look up these instructions by type and operator.
18 //===----------------------------------------------------------------------===//
20 #include "CodeGenDAGPatterns.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/TableGen/Error.h"
26 #include "llvm/TableGen/Record.h"
27 #include "llvm/TableGen/TableGenBackend.h"
31 /// InstructionMemo - This class holds additional information about an
32 /// instruction needed to emit code for it.
35 struct InstructionMemo {
37 const CodeGenRegisterClass *RC;
39 std::vector<std::string>* PhysRegs;
41 } // End anonymous namespace
43 /// ImmPredicateSet - This uniques predicates (represented as a string) and
44 /// gives them unique (small) integer ID's that start at 0.
46 class ImmPredicateSet {
47 DenseMap<TreePattern *, unsigned> ImmIDs;
48 std::vector<TreePredicateFn> PredsByName;
51 unsigned getIDFor(TreePredicateFn Pred) {
52 unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()];
54 PredsByName.push_back(Pred);
55 Entry = PredsByName.size();
60 const TreePredicateFn &getPredicate(unsigned i) {
61 assert(i < PredsByName.size());
62 return PredsByName[i];
65 typedef std::vector<TreePredicateFn>::const_iterator iterator;
66 iterator begin() const { return PredsByName.begin(); }
67 iterator end() const { return PredsByName.end(); }
70 } // End anonymous namespace
72 /// OperandsSignature - This class holds a description of a list of operand
73 /// types. It has utility methods for emitting text based on the operands.
76 struct OperandsSignature {
78 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
82 OpKind() : Repr(OK_Invalid) {}
84 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
85 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
87 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; }
88 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; }
89 static OpKind getImm(unsigned V) {
90 assert((unsigned)OK_Imm+V < 128 &&
91 "Too many integer predicates for the 'Repr' char");
92 OpKind K; K.Repr = OK_Imm+V; return K;
95 bool isReg() const { return Repr == OK_Reg; }
96 bool isFP() const { return Repr == OK_FP; }
97 bool isImm() const { return Repr >= OK_Imm; }
99 unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; }
101 void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
102 bool StripImmCodes) const {
110 if (unsigned Code = getImmCode())
111 OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName();
117 SmallVector<OpKind, 3> Operands;
119 bool operator<(const OperandsSignature &O) const {
120 return Operands < O.Operands;
122 bool operator==(const OperandsSignature &O) const {
123 return Operands == O.Operands;
126 bool empty() const { return Operands.empty(); }
128 bool hasAnyImmediateCodes() const {
129 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
130 if (Operands[i].isImm() && Operands[i].getImmCode() != 0)
135 /// getWithoutImmCodes - Return a copy of this with any immediate codes forced
137 OperandsSignature getWithoutImmCodes() const {
138 OperandsSignature Result;
139 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
140 if (!Operands[i].isImm())
141 Result.Operands.push_back(Operands[i]);
143 Result.Operands.push_back(OpKind::getImm(0));
147 void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) {
148 bool EmittedAnything = false;
149 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
150 if (!Operands[i].isImm()) continue;
152 unsigned Code = Operands[i].getImmCode();
153 if (Code == 0) continue;
158 TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1);
160 // Emit the type check.
162 << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0))
166 OS << PredFn.getFnName() << "(imm" << i <<')';
167 EmittedAnything = true;
171 /// initialize - Examine the given pattern and initialize the contents
172 /// of the Operands array accordingly. Return true if all the operands
173 /// are supported, false otherwise.
175 bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target,
176 MVT::SimpleValueType VT,
177 ImmPredicateSet &ImmediatePredicates,
178 const CodeGenRegisterClass *OrigDstRC) {
179 if (InstPatNode->isLeaf())
182 if (InstPatNode->getOperator()->getName() == "imm") {
183 Operands.push_back(OpKind::getImm(0));
187 if (InstPatNode->getOperator()->getName() == "fpimm") {
188 Operands.push_back(OpKind::getFP());
192 const CodeGenRegisterClass *DstRC = nullptr;
194 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
195 TreePatternNode *Op = InstPatNode->getChild(i);
197 // Handle imm operands specially.
198 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
200 if (!Op->getPredicateFns().empty()) {
201 TreePredicateFn PredFn = Op->getPredicateFns()[0];
202 // If there is more than one predicate weighing in on this operand
203 // then we don't handle it. This doesn't typically happen for
204 // immediates anyway.
205 if (Op->getPredicateFns().size() > 1 ||
206 !PredFn.isImmediatePattern())
208 // Ignore any instruction with 'FastIselShouldIgnore', these are
209 // not needed and just bloat the fast instruction selector. For
210 // example, X86 doesn't need to generate code to match ADD16ri8 since
211 // ADD16ri will do just fine.
212 Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
213 if (Rec->getValueAsBit("FastIselShouldIgnore"))
216 PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
219 // Handle unmatched immediate sizes here.
220 //if (Op->getType(0) != VT)
223 Operands.push_back(OpKind::getImm(PredNo));
228 // For now, filter out any operand with a predicate.
229 // For now, filter out any operand with multiple values.
230 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
234 if (Op->getOperator()->getName() == "fpimm") {
235 Operands.push_back(OpKind::getFP());
238 // For now, ignore other non-leaf nodes.
242 assert(Op->hasTypeSet(0) && "Type infererence not done?");
244 // For now, all the operands must have the same type (if they aren't
245 // immediates). Note that this causes us to reject variable sized shifts
247 if (Op->getType(0) != VT)
250 DefInit *OpDI = dyn_cast<DefInit>(Op->getLeafValue());
253 Record *OpLeafRec = OpDI->getDef();
255 // For now, the only other thing we accept is register operands.
256 const CodeGenRegisterClass *RC = nullptr;
257 if (OpLeafRec->isSubClassOf("RegisterOperand"))
258 OpLeafRec = OpLeafRec->getValueAsDef("RegClass");
259 if (OpLeafRec->isSubClassOf("RegisterClass"))
260 RC = &Target.getRegisterClass(OpLeafRec);
261 else if (OpLeafRec->isSubClassOf("Register"))
262 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
263 else if (OpLeafRec->isSubClassOf("ValueType")) {
268 // For now, this needs to be a register class of some sort.
272 // For now, all the operands must have the same register class or be
273 // a strict subclass of the destination.
275 if (DstRC != RC && !DstRC->hasSubClass(RC))
279 Operands.push_back(OpKind::getReg());
284 void PrintParameters(raw_ostream &OS) const {
285 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
286 if (Operands[i].isReg()) {
287 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
288 } else if (Operands[i].isImm()) {
289 OS << "uint64_t imm" << i;
290 } else if (Operands[i].isFP()) {
291 OS << "const ConstantFP *f" << i;
293 llvm_unreachable("Unknown operand kind!");
300 void PrintArguments(raw_ostream &OS,
301 const std::vector<std::string> &PR) const {
302 assert(PR.size() == Operands.size());
303 bool PrintedArg = false;
304 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
306 // Implicit physical register operand.
311 if (Operands[i].isReg()) {
312 OS << "Op" << i << ", Op" << i << "IsKill";
314 } else if (Operands[i].isImm()) {
317 } else if (Operands[i].isFP()) {
321 llvm_unreachable("Unknown operand kind!");
326 void PrintArguments(raw_ostream &OS) const {
327 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
328 if (Operands[i].isReg()) {
329 OS << "Op" << i << ", Op" << i << "IsKill";
330 } else if (Operands[i].isImm()) {
332 } else if (Operands[i].isFP()) {
335 llvm_unreachable("Unknown operand kind!");
343 void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR,
344 ImmPredicateSet &ImmPredicates,
345 bool StripImmCodes = false) const {
346 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
348 // Implicit physical register operand. e.g. Instruction::Mul expect to
349 // select to a binary op. On x86, mul may take a single operand with
350 // the other operand being implicit. We must emit something that looks
351 // like a binary instruction except for the very inner fastEmitInst_*
354 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
358 void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
359 bool StripImmCodes = false) const {
360 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
361 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
364 } // End anonymous namespace
368 typedef std::map<std::string, InstructionMemo> PredMap;
369 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
370 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
371 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
372 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
373 OperandsOpcodeTypeRetPredMap;
375 OperandsOpcodeTypeRetPredMap SimplePatterns;
377 std::map<OperandsSignature, std::vector<OperandsSignature> >
378 SignaturesWithConstantForms;
381 ImmPredicateSet ImmediatePredicates;
383 explicit FastISelMap(std::string InstNS);
385 void collectPatterns(CodeGenDAGPatterns &CGP);
386 void printImmediatePredicates(raw_ostream &OS);
387 void printFunctionDefinitions(raw_ostream &OS);
389 } // End anonymous namespace
391 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
392 return CGP.getSDNodeInfo(Op).getEnumName();
395 static std::string getLegalCName(std::string OpName) {
396 std::string::size_type pos = OpName.find("::");
397 if (pos != std::string::npos)
398 OpName.replace(pos, 2, "_");
402 FastISelMap::FastISelMap(std::string instns)
406 static std::string PhyRegForNode(TreePatternNode *Op,
407 const CodeGenTarget &Target) {
413 Record *OpLeafRec = cast<DefInit>(Op->getLeafValue())->getDef();
414 if (!OpLeafRec->isSubClassOf("Register"))
417 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue())
420 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
424 void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
425 const CodeGenTarget &Target = CGP.getTargetInfo();
427 // Determine the target's namespace name.
428 InstNS = Target.getInstNamespace() + "::";
429 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
431 // Scan through all the patterns and record the simple ones.
432 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
433 E = CGP.ptm_end(); I != E; ++I) {
434 const PatternToMatch &Pattern = *I;
436 // For now, just look at Instructions, so that we don't have to worry
437 // about emitting multiple instructions for a pattern.
438 TreePatternNode *Dst = Pattern.getDstPattern();
439 if (Dst->isLeaf()) continue;
440 Record *Op = Dst->getOperator();
441 if (!Op->isSubClassOf("Instruction"))
443 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
444 if (II.Operands.empty())
447 // For now, ignore multi-instruction patterns.
448 bool MultiInsts = false;
449 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
450 TreePatternNode *ChildOp = Dst->getChild(i);
451 if (ChildOp->isLeaf())
453 if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
461 // For now, ignore instructions where the first operand is not an
463 const CodeGenRegisterClass *DstRC = nullptr;
464 std::string SubRegNo;
465 if (Op->getName() != "EXTRACT_SUBREG") {
466 Record *Op0Rec = II.Operands[0].Rec;
467 if (Op0Rec->isSubClassOf("RegisterOperand"))
468 Op0Rec = Op0Rec->getValueAsDef("RegClass");
469 if (!Op0Rec->isSubClassOf("RegisterClass"))
471 DstRC = &Target.getRegisterClass(Op0Rec);
475 // If this isn't a leaf, then continue since the register classes are
476 // a bit too complicated for now.
477 if (!Dst->getChild(1)->isLeaf()) continue;
479 DefInit *SR = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue());
481 SubRegNo = getQualifiedName(SR->getDef());
483 SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString();
486 // Inspect the pattern.
487 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
488 if (!InstPatNode) continue;
489 if (InstPatNode->isLeaf()) continue;
491 // Ignore multiple result nodes for now.
492 if (InstPatNode->getNumTypes() > 1) continue;
494 Record *InstPatOp = InstPatNode->getOperator();
495 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
496 MVT::SimpleValueType RetVT = MVT::isVoid;
497 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
498 MVT::SimpleValueType VT = RetVT;
499 if (InstPatNode->getNumChildren()) {
500 assert(InstPatNode->getChild(0)->getNumTypes() == 1);
501 VT = InstPatNode->getChild(0)->getType(0);
504 // For now, filter out any instructions with predicates.
505 if (!InstPatNode->getPredicateFns().empty())
508 // Check all the operands.
509 OperandsSignature Operands;
510 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates,
514 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
515 if (InstPatNode->getOperator()->getName() == "imm" ||
516 InstPatNode->getOperator()->getName() == "fpimm")
517 PhysRegInputs->push_back("");
519 // Compute the PhysRegs used by the given pattern, and check that
520 // the mapping from the src to dst patterns is simple.
521 bool FoundNonSimplePattern = false;
522 unsigned DstIndex = 0;
523 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
524 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
525 if (PhysReg.empty()) {
526 if (DstIndex >= Dst->getNumChildren() ||
527 Dst->getChild(DstIndex)->getName() !=
528 InstPatNode->getChild(i)->getName()) {
529 FoundNonSimplePattern = true;
535 PhysRegInputs->push_back(PhysReg);
538 if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren())
539 FoundNonSimplePattern = true;
541 if (FoundNonSimplePattern)
545 // Check if the operands match one of the patterns handled by FastISel.
546 std::string ManglingSuffix;
547 raw_string_ostream SuffixOS(ManglingSuffix);
548 Operands.PrintManglingSuffix(SuffixOS, ImmediatePredicates, true);
550 if (!StringSwitch<bool>(ManglingSuffix)
551 .Cases("", "r", "rr", "ri", "rf", true)
552 .Cases("rri", "i", "f", true)
556 // Get the predicate that guards this pattern.
557 std::string PredicateCheck = Pattern.getPredicateCheck();
559 // Ok, we found a pattern that we can handle. Remember it.
560 InstructionMemo Memo = {
561 Pattern.getDstPattern()->getOperator()->getName(),
567 if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck))
568 PrintFatalError(Pattern.getSrcRecord()->getLoc(),
569 "Duplicate record in FastISel table!");
571 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
573 // If any of the operands were immediates with predicates on them, strip
574 // them down to a signature that doesn't have predicates so that we can
575 // associate them with the stripped predicate version.
576 if (Operands.hasAnyImmediateCodes()) {
577 SignaturesWithConstantForms[Operands.getWithoutImmCodes()]
578 .push_back(Operands);
583 void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
584 if (ImmediatePredicates.begin() == ImmediatePredicates.end())
587 OS << "\n// FastEmit Immediate Predicate functions.\n";
588 for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
589 E = ImmediatePredicates.end(); I != E; ++I) {
590 OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
591 OS << I->getImmediatePredicateCode() << "\n}\n";
598 void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
599 // Now emit code for all the patterns that we collected.
600 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
601 OE = SimplePatterns.end(); OI != OE; ++OI) {
602 const OperandsSignature &Operands = OI->first;
603 const OpcodeTypeRetPredMap &OTM = OI->second;
605 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
607 const std::string &Opcode = I->first;
608 const TypeRetPredMap &TM = I->second;
610 OS << "// FastEmit functions for " << Opcode << ".\n";
613 // Emit one function for each opcode,type pair.
614 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
616 MVT::SimpleValueType VT = TI->first;
617 const RetPredMap &RM = TI->second;
618 if (RM.size() != 1) {
619 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
621 MVT::SimpleValueType RetVT = RI->first;
622 const PredMap &PM = RI->second;
623 bool HasPred = false;
625 OS << "unsigned fastEmit_"
626 << getLegalCName(Opcode)
627 << "_" << getLegalCName(getName(VT))
628 << "_" << getLegalCName(getName(RetVT)) << "_";
629 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
631 Operands.PrintParameters(OS);
634 // Emit code for each possible instruction. There may be
635 // multiple if there are subtarget concerns.
636 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
638 std::string PredicateCheck = PI->first;
639 const InstructionMemo &Memo = PI->second;
641 if (PredicateCheck.empty()) {
643 "Multiple instructions match, at least one has "
644 "a predicate and at least one doesn't!");
646 OS << " if (" + PredicateCheck + ") {\n";
651 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
652 if ((*Memo.PhysRegs)[i] != "")
653 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, "
654 << "TII.get(TargetOpcode::COPY), "
655 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
658 OS << " return fastEmitInst_";
659 if (Memo.SubRegNo.empty()) {
660 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
661 ImmediatePredicates, true);
662 OS << "(" << InstNS << Memo.Name << ", ";
663 OS << "&" << InstNS << Memo.RC->getName() << "RegClass";
664 if (!Operands.empty())
666 Operands.PrintArguments(OS, *Memo.PhysRegs);
669 OS << "extractsubreg(" << getName(RetVT);
670 OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n";
677 // Return 0 if none of the predicates were satisfied.
679 OS << " return 0;\n";
684 // Emit one function for the type that demultiplexes on return type.
685 OS << "unsigned fastEmit_"
686 << getLegalCName(Opcode) << "_"
687 << getLegalCName(getName(VT)) << "_";
688 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
690 if (!Operands.empty())
692 Operands.PrintParameters(OS);
693 OS << ") {\nswitch (RetVT.SimpleTy) {\n";
694 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
696 MVT::SimpleValueType RetVT = RI->first;
697 OS << " case " << getName(RetVT) << ": return fastEmit_"
698 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
699 << "_" << getLegalCName(getName(RetVT)) << "_";
700 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
702 Operands.PrintArguments(OS);
705 OS << " default: return 0;\n}\n}\n\n";
708 // Non-variadic return type.
709 OS << "unsigned fastEmit_"
710 << getLegalCName(Opcode) << "_"
711 << getLegalCName(getName(VT)) << "_";
712 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
714 if (!Operands.empty())
716 Operands.PrintParameters(OS);
719 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
720 << ")\n return 0;\n";
722 const PredMap &PM = RM.begin()->second;
723 bool HasPred = false;
725 // Emit code for each possible instruction. There may be
726 // multiple if there are subtarget concerns.
727 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
729 std::string PredicateCheck = PI->first;
730 const InstructionMemo &Memo = PI->second;
732 if (PredicateCheck.empty()) {
734 "Multiple instructions match, at least one has "
735 "a predicate and at least one doesn't!");
737 OS << " if (" + PredicateCheck + ") {\n";
742 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
743 if ((*Memo.PhysRegs)[i] != "")
744 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, "
745 << "TII.get(TargetOpcode::COPY), "
746 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
749 OS << " return fastEmitInst_";
751 if (Memo.SubRegNo.empty()) {
752 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
753 ImmediatePredicates, true);
754 OS << "(" << InstNS << Memo.Name << ", ";
755 OS << "&" << InstNS << Memo.RC->getName() << "RegClass";
756 if (!Operands.empty())
758 Operands.PrintArguments(OS, *Memo.PhysRegs);
761 OS << "extractsubreg(RetVT, Op0, Op0IsKill, ";
770 // Return 0 if none of the predicates were satisfied.
772 OS << " return 0;\n";
778 // Emit one function for the opcode that demultiplexes based on the type.
779 OS << "unsigned fastEmit_"
780 << getLegalCName(Opcode) << "_";
781 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
782 OS << "(MVT VT, MVT RetVT";
783 if (!Operands.empty())
785 Operands.PrintParameters(OS);
787 OS << " switch (VT.SimpleTy) {\n";
788 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
790 MVT::SimpleValueType VT = TI->first;
791 std::string TypeName = getName(VT);
792 OS << " case " << TypeName << ": return fastEmit_"
793 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
794 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
796 if (!Operands.empty())
798 Operands.PrintArguments(OS);
801 OS << " default: return 0;\n";
807 OS << "// Top-level FastEmit function.\n";
810 // Emit one function for the operand signature that demultiplexes based
811 // on opcode and type.
812 OS << "unsigned fastEmit_";
813 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
814 OS << "(MVT VT, MVT RetVT, unsigned Opcode";
815 if (!Operands.empty())
817 Operands.PrintParameters(OS);
819 if (!Operands.hasAnyImmediateCodes())
823 // If there are any forms of this signature available that operate on
824 // constrained forms of the immediate (e.g., 32-bit sext immediate in a
825 // 64-bit operand), check them first.
827 std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI
828 = SignaturesWithConstantForms.find(Operands);
829 if (MI != SignaturesWithConstantForms.end()) {
830 // Unique any duplicates out of the list.
831 std::sort(MI->second.begin(), MI->second.end());
832 MI->second.erase(std::unique(MI->second.begin(), MI->second.end()),
835 // Check each in order it was seen. It would be nice to have a good
836 // relative ordering between them, but we're not going for optimality
838 for (unsigned i = 0, e = MI->second.size(); i != e; ++i) {
840 MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates);
841 OS << ")\n if (unsigned Reg = fastEmit_";
842 MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates);
843 OS << "(VT, RetVT, Opcode";
844 if (!MI->second[i].empty())
846 MI->second[i].PrintArguments(OS);
847 OS << "))\n return Reg;\n\n";
850 // Done with this, remove it.
851 SignaturesWithConstantForms.erase(MI);
854 OS << " switch (Opcode) {\n";
855 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
857 const std::string &Opcode = I->first;
859 OS << " case " << Opcode << ": return fastEmit_"
860 << getLegalCName(Opcode) << "_";
861 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
863 if (!Operands.empty())
865 Operands.PrintArguments(OS);
868 OS << " default: return 0;\n";
874 // TODO: SignaturesWithConstantForms should be empty here.
879 void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
880 CodeGenDAGPatterns CGP(RK);
881 const CodeGenTarget &Target = CGP.getTargetInfo();
882 emitSourceFileHeader("\"Fast\" Instruction Selector for the " +
883 Target.getName() + " target", OS);
885 // Determine the target's namespace name.
886 std::string InstNS = Target.getInstNamespace() + "::";
887 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
889 FastISelMap F(InstNS);
890 F.collectPatterns(CGP);
891 F.printImmediatePredicates(OS);
892 F.printFunctionDefinitions(OS);
895 } // End llvm namespace