1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a "fast" instruction selector.
12 // This instruction selection method is designed to emit very poor code
13 // quickly. Also, it is not designed to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations (e.g. calls) are not
15 // supported and cannot easily be added. Blocks containing operations
16 // that are not supported need to be handled by a more capable selector,
17 // such as the SelectionDAG selector.
19 // The intended use for "fast" instruction selection is "-O0" mode
20 // compilation, where the quality of the generated code is irrelevant when
21 // weighed against the speed at which the code can be generated.
23 // If compile time is so important, you might wonder why we don't just
24 // skip codegen all-together, emit LLVM bytecode files, and execute them
25 // with an interpreter. The answer is that it would complicate linking and
26 // debugging, and also because that isn't how a compiler is expected to
27 // work in some circles.
29 // If you need better generated code or more lowering than what this
30 // instruction selector provides, use the SelectionDAG (DAGISel) instruction
31 // selector instead. If you're looking here because SelectionDAG isn't fast
32 // enough, consider looking into improving the SelectionDAG infastructure
33 // instead. At the time of this writing there remain several major
34 // opportunities for improvement.
36 //===----------------------------------------------------------------------===//
38 #include "FastISelEmitter.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Streams.h"
42 #include "llvm/ADT/VectorExtras.h"
47 /// OperandsSignature - This class holds a description of a list of operand
48 /// types. It has utility methods for emitting text based on the operands.
50 struct OperandsSignature {
51 std::vector<std::string> Operands;
53 bool operator<(const OperandsSignature &O) const {
54 return Operands < O.Operands;
57 bool empty() const { return Operands.empty(); }
59 /// initialize - Examine the given pattern and initialize the contents
60 /// of the Operands array accordingly. Return true if all the operands
61 /// are supported, false otherwise.
63 bool initialize(TreePatternNode *InstPatNode,
64 const CodeGenTarget &Target,
65 MVT::SimpleValueType VT,
66 const CodeGenRegisterClass *DstRC) {
67 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
68 TreePatternNode *Op = InstPatNode->getChild(i);
71 // For now, filter out any operand with a predicate.
72 if (!Op->getPredicateFn().empty())
74 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
77 Record *OpLeafRec = OpDI->getDef();
78 // For now, only accept register operands.
79 if (!OpLeafRec->isSubClassOf("RegisterClass"))
81 // For now, require the register operands' register classes to all
83 const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
86 // For now, all the operands must have the same register class.
89 // For now, all the operands must have the same type.
90 if (Op->getTypeNum(0) != VT)
92 Operands.push_back("r");
97 void PrintParameters(std::ostream &OS) const {
98 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
99 if (Operands[i] == "r") {
100 OS << "unsigned Op" << i;
102 assert("Unknown operand kind!");
110 void PrintArguments(std::ostream &OS) const {
111 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
112 if (Operands[i] == "r") {
115 assert("Unknown operand kind!");
123 void PrintManglingSuffix(std::ostream &OS) const {
124 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
130 /// InstructionMemo - This class holds additional information about an
131 /// instruction needed to emit code for it.
133 struct InstructionMemo {
135 const CodeGenRegisterClass *RC;
140 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
141 return CGP.getSDNodeInfo(Op).getEnumName();
144 static std::string getLegalCName(std::string OpName) {
145 std::string::size_type pos = OpName.find("::");
146 if (pos != std::string::npos)
147 OpName.replace(pos, 2, "_");
151 void FastISelEmitter::run(std::ostream &OS) {
152 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
153 Target.getName() + " target", OS);
155 OS << "#include \"llvm/CodeGen/FastISel.h\"\n";
157 OS << "namespace llvm {\n";
159 OS << "namespace " << InstNS.substr(0, InstNS.size() - 2) << " {\n";
162 typedef std::map<MVT::SimpleValueType, InstructionMemo> TypeMap;
163 typedef std::map<std::string, TypeMap> OpcodeTypeMap;
164 typedef std::map<OperandsSignature, OpcodeTypeMap> OperandsOpcodeTypeMap;
165 OperandsOpcodeTypeMap SimplePatterns;
167 // Create the supported type signatures.
168 OperandsSignature KnownOperands;
169 SimplePatterns[KnownOperands] = OpcodeTypeMap();
170 KnownOperands.Operands.push_back("r");
171 SimplePatterns[KnownOperands] = OpcodeTypeMap();
172 KnownOperands.Operands.push_back("r");
173 SimplePatterns[KnownOperands] = OpcodeTypeMap();
175 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
176 E = CGP.ptm_end(); I != E; ++I) {
177 const PatternToMatch &Pattern = *I;
179 // For now, just look at Instructions, so that we don't have to worry
180 // about emitting multiple instructions for a pattern.
181 TreePatternNode *Dst = Pattern.getDstPattern();
182 if (Dst->isLeaf()) continue;
183 Record *Op = Dst->getOperator();
184 if (!Op->isSubClassOf("Instruction"))
186 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName());
187 if (II.OperandList.empty())
190 // For now, ignore instructions where the first operand is not an
192 Record *Op0Rec = II.OperandList[0].Rec;
193 if (!Op0Rec->isSubClassOf("RegisterClass"))
195 const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec);
199 // Inspect the pattern.
200 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
201 if (!InstPatNode) continue;
202 if (InstPatNode->isLeaf()) continue;
204 Record *InstPatOp = InstPatNode->getOperator();
205 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
206 MVT::SimpleValueType VT = InstPatNode->getTypeNum(0);
208 // For now, filter out instructions which just set a register to
209 // an Operand or an immediate, like MOV32ri.
210 if (InstPatOp->isSubClassOf("Operand"))
212 if (InstPatOp->getName() == "imm" ||
213 InstPatOp->getName() == "fpimm")
216 // For now, filter out any instructions with predicates.
217 if (!InstPatNode->getPredicateFn().empty())
220 // Check all the operands.
221 OperandsSignature Operands;
222 if (!Operands.initialize(InstPatNode, Target, VT, DstRC))
225 // If it's not a known signature, ignore it.
226 if (!SimplePatterns.count(Operands))
229 // Ok, we found a pattern that we can handle. Remember it.
231 InstructionMemo Memo = {
232 Pattern.getDstPattern()->getOperator()->getName(),
235 SimplePatterns[Operands][OpcodeName][VT] = Memo;
239 // Declare the target FastISel class.
240 OS << "class FastISel : public llvm::FastISel {\n";
241 for (OperandsOpcodeTypeMap::const_iterator OI = SimplePatterns.begin(),
242 OE = SimplePatterns.end(); OI != OE; ++OI) {
243 const OperandsSignature &Operands = OI->first;
244 const OpcodeTypeMap &OTM = OI->second;
246 for (OpcodeTypeMap::const_iterator I = OTM.begin(), E = OTM.end();
248 const std::string &Opcode = I->first;
249 const TypeMap &TM = I->second;
251 for (TypeMap::const_iterator TI = TM.begin(), TE = TM.end();
253 MVT::SimpleValueType VT = TI->first;
255 OS << " unsigned FastEmit_" << getLegalCName(Opcode)
256 << "_" << getLegalCName(getName(VT)) << "(";
257 Operands.PrintParameters(OS);
261 OS << " unsigned FastEmit_" << getLegalCName(Opcode)
262 << "(MVT::SimpleValueType VT";
263 if (!Operands.empty())
265 Operands.PrintParameters(OS);
269 OS << " unsigned FastEmit_";
270 Operands.PrintManglingSuffix(OS);
271 OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
272 if (!Operands.empty())
274 Operands.PrintParameters(OS);
278 OS << " explicit FastISel(MachineFunction &mf) : llvm::FastISel(mf) {}\n";
282 // Define the target FastISel creation function.
283 OS << "llvm::FastISel *createFastISel(MachineFunction &mf) {\n";
284 OS << " return new FastISel(mf);\n";
288 // Now emit code for all the patterns that we collected.
289 for (OperandsOpcodeTypeMap::const_iterator OI = SimplePatterns.begin(),
290 OE = SimplePatterns.end(); OI != OE; ++OI) {
291 const OperandsSignature &Operands = OI->first;
292 const OpcodeTypeMap &OTM = OI->second;
294 for (OpcodeTypeMap::const_iterator I = OTM.begin(), E = OTM.end();
296 const std::string &Opcode = I->first;
297 const TypeMap &TM = I->second;
299 OS << "// FastEmit functions for " << Opcode << ".\n";
302 // Emit one function for each opcode,type pair.
303 for (TypeMap::const_iterator TI = TM.begin(), TE = TM.end();
305 MVT::SimpleValueType VT = TI->first;
306 const InstructionMemo &Memo = TI->second;
308 OS << "unsigned FastISel::FastEmit_"
309 << getLegalCName(Opcode)
310 << "_" << getLegalCName(getName(VT)) << "(";
311 Operands.PrintParameters(OS);
313 OS << " return FastEmitInst_";
314 Operands.PrintManglingSuffix(OS);
315 OS << "(" << InstNS << Memo.Name << ", ";
316 OS << InstNS << Memo.RC->getName() << "RegisterClass";
317 if (!Operands.empty())
319 Operands.PrintArguments(OS);
325 // Emit one function for the opcode that demultiplexes based on the type.
326 OS << "unsigned FastISel::FastEmit_"
327 << getLegalCName(Opcode) << "(MVT::SimpleValueType VT";
328 if (!Operands.empty())
330 Operands.PrintParameters(OS);
332 OS << " switch (VT) {\n";
333 for (TypeMap::const_iterator TI = TM.begin(), TE = TM.end();
335 MVT::SimpleValueType VT = TI->first;
336 std::string TypeName = getName(VT);
337 OS << " case " << TypeName << ": return FastEmit_"
338 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "(";
339 Operands.PrintArguments(OS);
342 OS << " default: return 0;\n";
348 // Emit one function for the operand signature that demultiplexes based
349 // on opcode and type.
350 OS << "unsigned FastISel::FastEmit_";
351 Operands.PrintManglingSuffix(OS);
352 OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
353 if (!Operands.empty())
355 Operands.PrintParameters(OS);
357 OS << " switch (Opcode) {\n";
358 for (OpcodeTypeMap::const_iterator I = OTM.begin(), E = OTM.end();
360 const std::string &Opcode = I->first;
362 OS << " case " << Opcode << ": return FastEmit_"
363 << getLegalCName(Opcode) << "(VT";
364 if (!Operands.empty())
366 Operands.PrintArguments(OS);
369 OS << " default: return 0;\n";
375 OS << "} // namespace X86\n";
377 OS << "} // namespace llvm\n";
380 FastISelEmitter::FastISelEmitter(RecordKeeper &R)
383 Target(CGP.getTargetInfo()),
384 InstNS(Target.getInstNamespace() + "::") {
386 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");