1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits code for use by the "fast" instruction
11 // selection algorithm. See the comments at the top of
12 // lib/CodeGen/SelectionDAG/FastISel.cpp for background.
14 // This file scans through the target's tablegen instruction-info files
15 // and extracts instructions with obvious-looking patterns, and it emits
16 // code to look up these instructions by type and operator.
18 //===----------------------------------------------------------------------===//
20 #include "FastISelEmitter.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/ADT/VectorExtras.h"
28 /// InstructionMemo - This class holds additional information about an
29 /// instruction needed to emit code for it.
31 struct InstructionMemo {
33 const CodeGenRegisterClass *RC;
34 unsigned char SubRegNo;
35 std::vector<std::string>* PhysRegs;
38 /// OperandsSignature - This class holds a description of a list of operand
39 /// types. It has utility methods for emitting text based on the operands.
41 struct OperandsSignature {
42 std::vector<std::string> Operands;
44 bool operator<(const OperandsSignature &O) const {
45 return Operands < O.Operands;
48 bool empty() const { return Operands.empty(); }
50 /// initialize - Examine the given pattern and initialize the contents
51 /// of the Operands array accordingly. Return true if all the operands
52 /// are supported, false otherwise.
54 bool initialize(TreePatternNode *InstPatNode,
55 const CodeGenTarget &Target,
56 MVT::SimpleValueType VT) {
57 if (!InstPatNode->isLeaf() &&
58 InstPatNode->getOperator()->getName() == "imm") {
59 Operands.push_back("i");
62 if (!InstPatNode->isLeaf() &&
63 InstPatNode->getOperator()->getName() == "fpimm") {
64 Operands.push_back("f");
68 const CodeGenRegisterClass *DstRC = 0;
70 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
71 TreePatternNode *Op = InstPatNode->getChild(i);
72 // For now, filter out any operand with a predicate.
73 // For now, filter out any operand with multiple values.
74 if (!Op->getPredicateFns().empty() ||
75 Op->getNumTypes() != 1)
78 assert(Op->hasTypeSet(0) && "Type infererence not done?");
79 // For now, all the operands must have the same type.
80 if (Op->getType(0) != VT)
84 if (Op->getOperator()->getName() == "imm") {
85 Operands.push_back("i");
88 if (Op->getOperator()->getName() == "fpimm") {
89 Operands.push_back("f");
92 // For now, ignore other non-leaf nodes.
95 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
98 Record *OpLeafRec = OpDI->getDef();
99 // For now, the only other thing we accept is register operands.
101 const CodeGenRegisterClass *RC = 0;
102 if (OpLeafRec->isSubClassOf("RegisterClass"))
103 RC = &Target.getRegisterClass(OpLeafRec);
104 else if (OpLeafRec->isSubClassOf("Register"))
105 RC = Target.getRegisterClassForRegister(OpLeafRec);
108 // For now, require the register operands' register classes to all
112 // For now, all the operands must have the same register class.
118 Operands.push_back("r");
123 void PrintParameters(raw_ostream &OS) const {
124 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
125 if (Operands[i] == "r") {
126 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
127 } else if (Operands[i] == "i") {
128 OS << "uint64_t imm" << i;
129 } else if (Operands[i] == "f") {
130 OS << "ConstantFP *f" << i;
132 assert("Unknown operand kind!");
140 void PrintArguments(raw_ostream &OS,
141 const std::vector<std::string>& PR) const {
142 assert(PR.size() == Operands.size());
143 bool PrintedArg = false;
144 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
146 // Implicit physical register operand.
151 if (Operands[i] == "r") {
152 OS << "Op" << i << ", Op" << i << "IsKill";
154 } else if (Operands[i] == "i") {
157 } else if (Operands[i] == "f") {
161 assert("Unknown operand kind!");
167 void PrintArguments(raw_ostream &OS) const {
168 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
169 if (Operands[i] == "r") {
170 OS << "Op" << i << ", Op" << i << "IsKill";
171 } else if (Operands[i] == "i") {
173 } else if (Operands[i] == "f") {
176 assert("Unknown operand kind!");
185 void PrintManglingSuffix(raw_ostream &OS,
186 const std::vector<std::string>& PR) const {
187 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
189 // Implicit physical register operand. e.g. Instruction::Mul expect to
190 // select to a binary op. On x86, mul may take a single operand with
191 // the other operand being implicit. We must emit something that looks
192 // like a binary instruction except for the very inner FastEmitInst_*
199 void PrintManglingSuffix(raw_ostream &OS) const {
200 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
207 typedef std::map<std::string, InstructionMemo> PredMap;
208 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
209 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
210 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
211 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> OperandsOpcodeTypeRetPredMap;
213 OperandsOpcodeTypeRetPredMap SimplePatterns;
218 explicit FastISelMap(std::string InstNS);
220 void CollectPatterns(CodeGenDAGPatterns &CGP);
221 void PrintFunctionDefinitions(raw_ostream &OS);
226 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
227 return CGP.getSDNodeInfo(Op).getEnumName();
230 static std::string getLegalCName(std::string OpName) {
231 std::string::size_type pos = OpName.find("::");
232 if (pos != std::string::npos)
233 OpName.replace(pos, 2, "_");
237 FastISelMap::FastISelMap(std::string instns)
241 void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
242 const CodeGenTarget &Target = CGP.getTargetInfo();
244 // Determine the target's namespace name.
245 InstNS = Target.getInstNamespace() + "::";
246 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
248 // Scan through all the patterns and record the simple ones.
249 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
250 E = CGP.ptm_end(); I != E; ++I) {
251 const PatternToMatch &Pattern = *I;
253 // For now, just look at Instructions, so that we don't have to worry
254 // about emitting multiple instructions for a pattern.
255 TreePatternNode *Dst = Pattern.getDstPattern();
256 if (Dst->isLeaf()) continue;
257 Record *Op = Dst->getOperator();
258 if (!Op->isSubClassOf("Instruction"))
260 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
261 if (II.OperandList.empty())
264 // For now, ignore multi-instruction patterns.
265 bool MultiInsts = false;
266 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
267 TreePatternNode *ChildOp = Dst->getChild(i);
268 if (ChildOp->isLeaf())
270 if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
278 // For now, ignore instructions where the first operand is not an
280 const CodeGenRegisterClass *DstRC = 0;
281 unsigned SubRegNo = ~0;
282 if (Op->getName() != "EXTRACT_SUBREG") {
283 Record *Op0Rec = II.OperandList[0].Rec;
284 if (!Op0Rec->isSubClassOf("RegisterClass"))
286 DstRC = &Target.getRegisterClass(Op0Rec);
290 SubRegNo = static_cast<IntInit*>(
291 Dst->getChild(1)->getLeafValue())->getValue();
294 // Inspect the pattern.
295 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
296 if (!InstPatNode) continue;
297 if (InstPatNode->isLeaf()) continue;
299 // Ignore multiple result nodes for now.
300 if (InstPatNode->getNumTypes() > 1) continue;
302 Record *InstPatOp = InstPatNode->getOperator();
303 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
304 MVT::SimpleValueType RetVT = MVT::isVoid;
305 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
306 MVT::SimpleValueType VT = RetVT;
307 if (InstPatNode->getNumChildren()) {
308 assert(InstPatNode->getChild(0)->getNumTypes() == 1);
309 VT = InstPatNode->getChild(0)->getType(0);
312 // For now, filter out instructions which just set a register to
313 // an Operand or an immediate, like MOV32ri.
314 if (InstPatOp->isSubClassOf("Operand"))
317 // For now, filter out any instructions with predicates.
318 if (!InstPatNode->getPredicateFns().empty())
321 // Check all the operands.
322 OperandsSignature Operands;
323 if (!Operands.initialize(InstPatNode, Target, VT))
326 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
327 if (!InstPatNode->isLeaf() &&
328 (InstPatNode->getOperator()->getName() == "imm" ||
329 InstPatNode->getOperator()->getName() == "fpimmm"))
330 PhysRegInputs->push_back("");
331 else if (!InstPatNode->isLeaf()) {
332 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
333 TreePatternNode *Op = InstPatNode->getChild(i);
335 PhysRegInputs->push_back("");
339 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
340 Record *OpLeafRec = OpDI->getDef();
342 if (OpLeafRec->isSubClassOf("Register")) {
343 PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
344 "Namespace")->getValue())->getValue();
347 std::vector<CodeGenRegister> Regs = Target.getRegisters();
348 for (unsigned i = 0; i < Regs.size(); ++i) {
349 if (Regs[i].TheDef == OpLeafRec) {
350 PhysReg += Regs[i].getName();
356 PhysRegInputs->push_back(PhysReg);
359 PhysRegInputs->push_back("");
361 // Get the predicate that guards this pattern.
362 std::string PredicateCheck = Pattern.getPredicateCheck();
364 // Ok, we found a pattern that we can handle. Remember it.
365 InstructionMemo Memo = {
366 Pattern.getDstPattern()->getOperator()->getName(),
371 assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
372 "Duplicate pattern!");
373 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
377 void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
378 // Now emit code for all the patterns that we collected.
379 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
380 OE = SimplePatterns.end(); OI != OE; ++OI) {
381 const OperandsSignature &Operands = OI->first;
382 const OpcodeTypeRetPredMap &OTM = OI->second;
384 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
386 const std::string &Opcode = I->first;
387 const TypeRetPredMap &TM = I->second;
389 OS << "// FastEmit functions for " << Opcode << ".\n";
392 // Emit one function for each opcode,type pair.
393 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
395 MVT::SimpleValueType VT = TI->first;
396 const RetPredMap &RM = TI->second;
397 if (RM.size() != 1) {
398 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
400 MVT::SimpleValueType RetVT = RI->first;
401 const PredMap &PM = RI->second;
402 bool HasPred = false;
404 OS << "unsigned FastEmit_"
405 << getLegalCName(Opcode)
406 << "_" << getLegalCName(getName(VT))
407 << "_" << getLegalCName(getName(RetVT)) << "_";
408 Operands.PrintManglingSuffix(OS);
410 Operands.PrintParameters(OS);
413 // Emit code for each possible instruction. There may be
414 // multiple if there are subtarget concerns.
415 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
417 std::string PredicateCheck = PI->first;
418 const InstructionMemo &Memo = PI->second;
420 if (PredicateCheck.empty()) {
422 "Multiple instructions match, at least one has "
423 "a predicate and at least one doesn't!");
425 OS << " if (" + PredicateCheck + ") {\n";
430 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
431 if ((*Memo.PhysRegs)[i] != "")
432 OS << " TII.copyRegToReg(*MBB, MBB->end(), "
433 << (*Memo.PhysRegs)[i] << ", Op" << i << ", "
434 << "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
435 << (*Memo.PhysRegs)[i] << "), "
436 << "MRI.getRegClass(Op" << i << "), DL);\n";
439 OS << " return FastEmitInst_";
440 if (Memo.SubRegNo == (unsigned char)~0) {
441 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
442 OS << "(" << InstNS << Memo.Name << ", ";
443 OS << InstNS << Memo.RC->getName() << "RegisterClass";
444 if (!Operands.empty())
446 Operands.PrintArguments(OS, *Memo.PhysRegs);
449 OS << "extractsubreg(" << getName(RetVT);
450 OS << ", Op0, Op0IsKill, ";
451 OS << (unsigned)Memo.SubRegNo;
459 // Return 0 if none of the predicates were satisfied.
461 OS << " return 0;\n";
466 // Emit one function for the type that demultiplexes on return type.
467 OS << "unsigned FastEmit_"
468 << getLegalCName(Opcode) << "_"
469 << getLegalCName(getName(VT)) << "_";
470 Operands.PrintManglingSuffix(OS);
472 if (!Operands.empty())
474 Operands.PrintParameters(OS);
475 OS << ") {\nswitch (RetVT.SimpleTy) {\n";
476 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
478 MVT::SimpleValueType RetVT = RI->first;
479 OS << " case " << getName(RetVT) << ": return FastEmit_"
480 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
481 << "_" << getLegalCName(getName(RetVT)) << "_";
482 Operands.PrintManglingSuffix(OS);
484 Operands.PrintArguments(OS);
487 OS << " default: return 0;\n}\n}\n\n";
490 // Non-variadic return type.
491 OS << "unsigned FastEmit_"
492 << getLegalCName(Opcode) << "_"
493 << getLegalCName(getName(VT)) << "_";
494 Operands.PrintManglingSuffix(OS);
496 if (!Operands.empty())
498 Operands.PrintParameters(OS);
501 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
502 << ")\n return 0;\n";
504 const PredMap &PM = RM.begin()->second;
505 bool HasPred = false;
507 // Emit code for each possible instruction. There may be
508 // multiple if there are subtarget concerns.
509 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
511 std::string PredicateCheck = PI->first;
512 const InstructionMemo &Memo = PI->second;
514 if (PredicateCheck.empty()) {
516 "Multiple instructions match, at least one has "
517 "a predicate and at least one doesn't!");
519 OS << " if (" + PredicateCheck + ") {\n";
524 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
525 if ((*Memo.PhysRegs)[i] != "")
526 OS << " TII.copyRegToReg(*MBB, MBB->end(), "
527 << (*Memo.PhysRegs)[i] << ", Op" << i << ", "
528 << "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
529 << (*Memo.PhysRegs)[i] << "), "
530 << "MRI.getRegClass(Op" << i << "), DL);\n";
533 OS << " return FastEmitInst_";
535 if (Memo.SubRegNo == (unsigned char)~0) {
536 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
537 OS << "(" << InstNS << Memo.Name << ", ";
538 OS << InstNS << Memo.RC->getName() << "RegisterClass";
539 if (!Operands.empty())
541 Operands.PrintArguments(OS, *Memo.PhysRegs);
544 OS << "extractsubreg(RetVT, Op0, Op0IsKill, ";
545 OS << (unsigned)Memo.SubRegNo;
553 // Return 0 if none of the predicates were satisfied.
555 OS << " return 0;\n";
561 // Emit one function for the opcode that demultiplexes based on the type.
562 OS << "unsigned FastEmit_"
563 << getLegalCName(Opcode) << "_";
564 Operands.PrintManglingSuffix(OS);
565 OS << "(MVT VT, MVT RetVT";
566 if (!Operands.empty())
568 Operands.PrintParameters(OS);
570 OS << " switch (VT.SimpleTy) {\n";
571 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
573 MVT::SimpleValueType VT = TI->first;
574 std::string TypeName = getName(VT);
575 OS << " case " << TypeName << ": return FastEmit_"
576 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
577 Operands.PrintManglingSuffix(OS);
579 if (!Operands.empty())
581 Operands.PrintArguments(OS);
584 OS << " default: return 0;\n";
590 OS << "// Top-level FastEmit function.\n";
593 // Emit one function for the operand signature that demultiplexes based
594 // on opcode and type.
595 OS << "unsigned FastEmit_";
596 Operands.PrintManglingSuffix(OS);
597 OS << "(MVT VT, MVT RetVT, unsigned Opcode";
598 if (!Operands.empty())
600 Operands.PrintParameters(OS);
602 OS << " switch (Opcode) {\n";
603 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
605 const std::string &Opcode = I->first;
607 OS << " case " << Opcode << ": return FastEmit_"
608 << getLegalCName(Opcode) << "_";
609 Operands.PrintManglingSuffix(OS);
611 if (!Operands.empty())
613 Operands.PrintArguments(OS);
616 OS << " default: return 0;\n";
623 void FastISelEmitter::run(raw_ostream &OS) {
624 const CodeGenTarget &Target = CGP.getTargetInfo();
626 // Determine the target's namespace name.
627 std::string InstNS = Target.getInstNamespace() + "::";
628 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
630 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
631 Target.getName() + " target", OS);
633 FastISelMap F(InstNS);
634 F.CollectPatterns(CGP);
635 F.PrintFunctionDefinitions(OS);
638 FastISelEmitter::FastISelEmitter(RecordKeeper &R)