1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits code for use by the "fast" instruction
11 // selection algorithm. See the comments at the top of
12 // lib/CodeGen/SelectionDAG/FastISel.cpp for background.
14 // This file scans through the target's tablegen instruction-info files
15 // and extracts instructions with obvious-looking patterns, and it emits
16 // code to look up these instructions by type and operator.
18 //===----------------------------------------------------------------------===//
20 #include "FastISelEmitter.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/VectorExtras.h"
29 /// InstructionMemo - This class holds additional information about an
30 /// instruction needed to emit code for it.
32 struct InstructionMemo {
34 const CodeGenRegisterClass *RC;
36 std::vector<std::string>* PhysRegs;
39 /// ImmPredicateSet - This uniques predicates (represented as a string) and
40 /// gives them unique (small) integer ID's that start at 0.
41 class ImmPredicateSet {
42 DenseMap<TreePattern *, unsigned> ImmIDs;
43 std::vector<TreePredicateFn> PredsByName;
46 unsigned getIDFor(TreePredicateFn Pred) {
47 unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()];
49 PredsByName.push_back(Pred);
50 Entry = PredsByName.size();
55 const TreePredicateFn &getPredicate(unsigned i) {
56 assert(i < PredsByName.size());
57 return PredsByName[i];
60 typedef std::vector<TreePredicateFn>::const_iterator iterator;
61 iterator begin() const { return PredsByName.begin(); }
62 iterator end() const { return PredsByName.end(); }
66 /// OperandsSignature - This class holds a description of a list of operand
67 /// types. It has utility methods for emitting text based on the operands.
69 struct OperandsSignature {
71 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
75 OpKind() : Repr(OK_Invalid) {}
77 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
78 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
80 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; }
81 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; }
82 static OpKind getImm(unsigned V) {
83 assert((unsigned)OK_Imm+V < 128 &&
84 "Too many integer predicates for the 'Repr' char");
85 OpKind K; K.Repr = OK_Imm+V; return K;
88 bool isReg() const { return Repr == OK_Reg; }
89 bool isFP() const { return Repr == OK_FP; }
90 bool isImm() const { return Repr >= OK_Imm; }
92 unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; }
94 void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
95 bool StripImmCodes) const {
103 if (unsigned Code = getImmCode())
104 OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName();
110 SmallVector<OpKind, 3> Operands;
112 bool operator<(const OperandsSignature &O) const {
113 return Operands < O.Operands;
115 bool operator==(const OperandsSignature &O) const {
116 return Operands == O.Operands;
119 bool empty() const { return Operands.empty(); }
121 bool hasAnyImmediateCodes() const {
122 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
123 if (Operands[i].isImm() && Operands[i].getImmCode() != 0)
128 /// getWithoutImmCodes - Return a copy of this with any immediate codes forced
130 OperandsSignature getWithoutImmCodes() const {
131 OperandsSignature Result;
132 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
133 if (!Operands[i].isImm())
134 Result.Operands.push_back(Operands[i]);
136 Result.Operands.push_back(OpKind::getImm(0));
140 void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) {
141 bool EmittedAnything = false;
142 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
143 if (!Operands[i].isImm()) continue;
145 unsigned Code = Operands[i].getImmCode();
146 if (Code == 0) continue;
151 TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1);
153 // Emit the type check.
155 << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0))
159 OS << PredFn.getFnName() << "(imm" << i <<')';
160 EmittedAnything = true;
164 /// initialize - Examine the given pattern and initialize the contents
165 /// of the Operands array accordingly. Return true if all the operands
166 /// are supported, false otherwise.
168 bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target,
169 MVT::SimpleValueType VT,
170 ImmPredicateSet &ImmediatePredicates) {
171 if (InstPatNode->isLeaf())
174 if (InstPatNode->getOperator()->getName() == "imm") {
175 Operands.push_back(OpKind::getImm(0));
179 if (InstPatNode->getOperator()->getName() == "fpimm") {
180 Operands.push_back(OpKind::getFP());
184 const CodeGenRegisterClass *DstRC = 0;
186 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
187 TreePatternNode *Op = InstPatNode->getChild(i);
189 // Handle imm operands specially.
190 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
192 if (!Op->getPredicateFns().empty()) {
193 TreePredicateFn PredFn = Op->getPredicateFns()[0];
194 // If there is more than one predicate weighing in on this operand
195 // then we don't handle it. This doesn't typically happen for
196 // immediates anyway.
197 if (Op->getPredicateFns().size() > 1 ||
198 !PredFn.isImmediatePattern())
200 // Ignore any instruction with 'FastIselShouldIgnore', these are
201 // not needed and just bloat the fast instruction selector. For
202 // example, X86 doesn't need to generate code to match ADD16ri8 since
203 // ADD16ri will do just fine.
204 Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
205 if (Rec->getValueAsBit("FastIselShouldIgnore"))
208 PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
211 // Handle unmatched immediate sizes here.
212 //if (Op->getType(0) != VT)
215 Operands.push_back(OpKind::getImm(PredNo));
220 // For now, filter out any operand with a predicate.
221 // For now, filter out any operand with multiple values.
222 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
226 if (Op->getOperator()->getName() == "fpimm") {
227 Operands.push_back(OpKind::getFP());
230 // For now, ignore other non-leaf nodes.
234 assert(Op->hasTypeSet(0) && "Type infererence not done?");
236 // For now, all the operands must have the same type (if they aren't
237 // immediates). Note that this causes us to reject variable sized shifts
239 if (Op->getType(0) != VT)
242 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
245 Record *OpLeafRec = OpDI->getDef();
247 // For now, the only other thing we accept is register operands.
248 const CodeGenRegisterClass *RC = 0;
249 if (OpLeafRec->isSubClassOf("RegisterClass"))
250 RC = &Target.getRegisterClass(OpLeafRec);
251 else if (OpLeafRec->isSubClassOf("Register"))
252 RC = Target.getRegisterClassForRegister(OpLeafRec);
256 // For now, this needs to be a register class of some sort.
260 // For now, all the operands must have the same register class or be
261 // a strict subclass of the destination.
263 if (DstRC != RC && !DstRC->hasSubClass(RC))
267 Operands.push_back(OpKind::getReg());
272 void PrintParameters(raw_ostream &OS) const {
273 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
274 if (Operands[i].isReg()) {
275 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
276 } else if (Operands[i].isImm()) {
277 OS << "uint64_t imm" << i;
278 } else if (Operands[i].isFP()) {
279 OS << "ConstantFP *f" << i;
281 assert("Unknown operand kind!");
289 void PrintArguments(raw_ostream &OS,
290 const std::vector<std::string> &PR) const {
291 assert(PR.size() == Operands.size());
292 bool PrintedArg = false;
293 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
295 // Implicit physical register operand.
300 if (Operands[i].isReg()) {
301 OS << "Op" << i << ", Op" << i << "IsKill";
303 } else if (Operands[i].isImm()) {
306 } else if (Operands[i].isFP()) {
310 assert("Unknown operand kind!");
316 void PrintArguments(raw_ostream &OS) const {
317 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
318 if (Operands[i].isReg()) {
319 OS << "Op" << i << ", Op" << i << "IsKill";
320 } else if (Operands[i].isImm()) {
322 } else if (Operands[i].isFP()) {
325 assert("Unknown operand kind!");
334 void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR,
335 ImmPredicateSet &ImmPredicates,
336 bool StripImmCodes = false) const {
337 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
339 // Implicit physical register operand. e.g. Instruction::Mul expect to
340 // select to a binary op. On x86, mul may take a single operand with
341 // the other operand being implicit. We must emit something that looks
342 // like a binary instruction except for the very inner FastEmitInst_*
345 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
349 void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
350 bool StripImmCodes = false) const {
351 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
352 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
357 typedef std::map<std::string, InstructionMemo> PredMap;
358 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
359 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
360 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
361 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
362 OperandsOpcodeTypeRetPredMap;
364 OperandsOpcodeTypeRetPredMap SimplePatterns;
366 std::map<OperandsSignature, std::vector<OperandsSignature> >
367 SignaturesWithConstantForms;
370 ImmPredicateSet ImmediatePredicates;
372 explicit FastISelMap(std::string InstNS);
374 void collectPatterns(CodeGenDAGPatterns &CGP);
375 void printImmediatePredicates(raw_ostream &OS);
376 void printFunctionDefinitions(raw_ostream &OS);
381 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
382 return CGP.getSDNodeInfo(Op).getEnumName();
385 static std::string getLegalCName(std::string OpName) {
386 std::string::size_type pos = OpName.find("::");
387 if (pos != std::string::npos)
388 OpName.replace(pos, 2, "_");
392 FastISelMap::FastISelMap(std::string instns)
396 void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
397 const CodeGenTarget &Target = CGP.getTargetInfo();
399 // Determine the target's namespace name.
400 InstNS = Target.getInstNamespace() + "::";
401 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
403 // Scan through all the patterns and record the simple ones.
404 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
405 E = CGP.ptm_end(); I != E; ++I) {
406 const PatternToMatch &Pattern = *I;
408 // For now, just look at Instructions, so that we don't have to worry
409 // about emitting multiple instructions for a pattern.
410 TreePatternNode *Dst = Pattern.getDstPattern();
411 if (Dst->isLeaf()) continue;
412 Record *Op = Dst->getOperator();
413 if (!Op->isSubClassOf("Instruction"))
415 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
416 if (II.Operands.empty())
419 // For now, ignore multi-instruction patterns.
420 bool MultiInsts = false;
421 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
422 TreePatternNode *ChildOp = Dst->getChild(i);
423 if (ChildOp->isLeaf())
425 if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
433 // For now, ignore instructions where the first operand is not an
435 const CodeGenRegisterClass *DstRC = 0;
436 std::string SubRegNo;
437 if (Op->getName() != "EXTRACT_SUBREG") {
438 Record *Op0Rec = II.Operands[0].Rec;
439 if (!Op0Rec->isSubClassOf("RegisterClass"))
441 DstRC = &Target.getRegisterClass(Op0Rec);
445 // If this isn't a leaf, then continue since the register classes are
446 // a bit too complicated for now.
447 if (!Dst->getChild(1)->isLeaf()) continue;
449 DefInit *SR = dynamic_cast<DefInit*>(Dst->getChild(1)->getLeafValue());
451 SubRegNo = getQualifiedName(SR->getDef());
453 SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString();
456 // Inspect the pattern.
457 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
458 if (!InstPatNode) continue;
459 if (InstPatNode->isLeaf()) continue;
461 // Ignore multiple result nodes for now.
462 if (InstPatNode->getNumTypes() > 1) continue;
464 Record *InstPatOp = InstPatNode->getOperator();
465 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
466 MVT::SimpleValueType RetVT = MVT::isVoid;
467 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
468 MVT::SimpleValueType VT = RetVT;
469 if (InstPatNode->getNumChildren()) {
470 assert(InstPatNode->getChild(0)->getNumTypes() == 1);
471 VT = InstPatNode->getChild(0)->getType(0);
474 // For now, filter out instructions which just set a register to
475 // an Operand or an immediate, like MOV32ri.
476 if (InstPatOp->isSubClassOf("Operand"))
479 // For now, filter out any instructions with predicates.
480 if (!InstPatNode->getPredicateFns().empty())
483 // Check all the operands.
484 OperandsSignature Operands;
485 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates))
488 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
489 if (!InstPatNode->isLeaf() &&
490 (InstPatNode->getOperator()->getName() == "imm" ||
491 InstPatNode->getOperator()->getName() == "fpimmm"))
492 PhysRegInputs->push_back("");
493 else if (!InstPatNode->isLeaf()) {
494 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
495 TreePatternNode *Op = InstPatNode->getChild(i);
497 PhysRegInputs->push_back("");
501 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
502 Record *OpLeafRec = OpDI->getDef();
504 if (OpLeafRec->isSubClassOf("Register")) {
505 PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
506 "Namespace")->getValue())->getValue();
509 std::vector<CodeGenRegister> Regs = Target.getRegisters();
510 for (unsigned i = 0; i < Regs.size(); ++i) {
511 if (Regs[i].TheDef == OpLeafRec) {
512 PhysReg += Regs[i].getName();
518 PhysRegInputs->push_back(PhysReg);
521 PhysRegInputs->push_back("");
523 // Get the predicate that guards this pattern.
524 std::string PredicateCheck = Pattern.getPredicateCheck();
526 // Ok, we found a pattern that we can handle. Remember it.
527 InstructionMemo Memo = {
528 Pattern.getDstPattern()->getOperator()->getName(),
534 if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck))
535 throw TGError(Pattern.getSrcRecord()->getLoc(),
536 "Duplicate record in FastISel table!");
538 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
540 // If any of the operands were immediates with predicates on them, strip
541 // them down to a signature that doesn't have predicates so that we can
542 // associate them with the stripped predicate version.
543 if (Operands.hasAnyImmediateCodes()) {
544 SignaturesWithConstantForms[Operands.getWithoutImmCodes()]
545 .push_back(Operands);
550 void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
551 if (ImmediatePredicates.begin() == ImmediatePredicates.end())
554 OS << "\n// FastEmit Immediate Predicate functions.\n";
555 for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
556 E = ImmediatePredicates.end(); I != E; ++I) {
557 OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
558 OS << I->getImmediatePredicateCode() << "\n}\n";
565 void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
566 // Now emit code for all the patterns that we collected.
567 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
568 OE = SimplePatterns.end(); OI != OE; ++OI) {
569 const OperandsSignature &Operands = OI->first;
570 const OpcodeTypeRetPredMap &OTM = OI->second;
572 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
574 const std::string &Opcode = I->first;
575 const TypeRetPredMap &TM = I->second;
577 OS << "// FastEmit functions for " << Opcode << ".\n";
580 // Emit one function for each opcode,type pair.
581 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
583 MVT::SimpleValueType VT = TI->first;
584 const RetPredMap &RM = TI->second;
585 if (RM.size() != 1) {
586 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
588 MVT::SimpleValueType RetVT = RI->first;
589 const PredMap &PM = RI->second;
590 bool HasPred = false;
592 OS << "unsigned FastEmit_"
593 << getLegalCName(Opcode)
594 << "_" << getLegalCName(getName(VT))
595 << "_" << getLegalCName(getName(RetVT)) << "_";
596 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
598 Operands.PrintParameters(OS);
601 // Emit code for each possible instruction. There may be
602 // multiple if there are subtarget concerns.
603 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
605 std::string PredicateCheck = PI->first;
606 const InstructionMemo &Memo = PI->second;
608 if (PredicateCheck.empty()) {
610 "Multiple instructions match, at least one has "
611 "a predicate and at least one doesn't!");
613 OS << " if (" + PredicateCheck + ") {\n";
618 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
619 if ((*Memo.PhysRegs)[i] != "")
620 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
621 << "TII.get(TargetOpcode::COPY), "
622 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
625 OS << " return FastEmitInst_";
626 if (Memo.SubRegNo.empty()) {
627 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
628 ImmediatePredicates, true);
629 OS << "(" << InstNS << Memo.Name << ", ";
630 OS << InstNS << Memo.RC->getName() << "RegisterClass";
631 if (!Operands.empty())
633 Operands.PrintArguments(OS, *Memo.PhysRegs);
636 OS << "extractsubreg(" << getName(RetVT);
637 OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n";
644 // Return 0 if none of the predicates were satisfied.
646 OS << " return 0;\n";
651 // Emit one function for the type that demultiplexes on return type.
652 OS << "unsigned FastEmit_"
653 << getLegalCName(Opcode) << "_"
654 << getLegalCName(getName(VT)) << "_";
655 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
657 if (!Operands.empty())
659 Operands.PrintParameters(OS);
660 OS << ") {\nswitch (RetVT.SimpleTy) {\n";
661 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
663 MVT::SimpleValueType RetVT = RI->first;
664 OS << " case " << getName(RetVT) << ": return FastEmit_"
665 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
666 << "_" << getLegalCName(getName(RetVT)) << "_";
667 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
669 Operands.PrintArguments(OS);
672 OS << " default: return 0;\n}\n}\n\n";
675 // Non-variadic return type.
676 OS << "unsigned FastEmit_"
677 << getLegalCName(Opcode) << "_"
678 << getLegalCName(getName(VT)) << "_";
679 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
681 if (!Operands.empty())
683 Operands.PrintParameters(OS);
686 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
687 << ")\n return 0;\n";
689 const PredMap &PM = RM.begin()->second;
690 bool HasPred = false;
692 // Emit code for each possible instruction. There may be
693 // multiple if there are subtarget concerns.
694 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
696 std::string PredicateCheck = PI->first;
697 const InstructionMemo &Memo = PI->second;
699 if (PredicateCheck.empty()) {
701 "Multiple instructions match, at least one has "
702 "a predicate and at least one doesn't!");
704 OS << " if (" + PredicateCheck + ") {\n";
709 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
710 if ((*Memo.PhysRegs)[i] != "")
711 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
712 << "TII.get(TargetOpcode::COPY), "
713 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
716 OS << " return FastEmitInst_";
718 if (Memo.SubRegNo.empty()) {
719 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
720 ImmediatePredicates, true);
721 OS << "(" << InstNS << Memo.Name << ", ";
722 OS << InstNS << Memo.RC->getName() << "RegisterClass";
723 if (!Operands.empty())
725 Operands.PrintArguments(OS, *Memo.PhysRegs);
728 OS << "extractsubreg(RetVT, Op0, Op0IsKill, ";
737 // Return 0 if none of the predicates were satisfied.
739 OS << " return 0;\n";
745 // Emit one function for the opcode that demultiplexes based on the type.
746 OS << "unsigned FastEmit_"
747 << getLegalCName(Opcode) << "_";
748 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
749 OS << "(MVT VT, MVT RetVT";
750 if (!Operands.empty())
752 Operands.PrintParameters(OS);
754 OS << " switch (VT.SimpleTy) {\n";
755 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
757 MVT::SimpleValueType VT = TI->first;
758 std::string TypeName = getName(VT);
759 OS << " case " << TypeName << ": return FastEmit_"
760 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
761 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
763 if (!Operands.empty())
765 Operands.PrintArguments(OS);
768 OS << " default: return 0;\n";
774 OS << "// Top-level FastEmit function.\n";
777 // Emit one function for the operand signature that demultiplexes based
778 // on opcode and type.
779 OS << "unsigned FastEmit_";
780 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
781 OS << "(MVT VT, MVT RetVT, unsigned Opcode";
782 if (!Operands.empty())
784 Operands.PrintParameters(OS);
787 // If there are any forms of this signature available that operand on
788 // constrained forms of the immediate (e.g. 32-bit sext immediate in a
789 // 64-bit operand), check them first.
791 std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI
792 = SignaturesWithConstantForms.find(Operands);
793 if (MI != SignaturesWithConstantForms.end()) {
794 // Unique any duplicates out of the list.
795 std::sort(MI->second.begin(), MI->second.end());
796 MI->second.erase(std::unique(MI->second.begin(), MI->second.end()),
799 // Check each in order it was seen. It would be nice to have a good
800 // relative ordering between them, but we're not going for optimality
802 for (unsigned i = 0, e = MI->second.size(); i != e; ++i) {
804 MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates);
805 OS << ")\n if (unsigned Reg = FastEmit_";
806 MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates);
807 OS << "(VT, RetVT, Opcode";
808 if (!MI->second[i].empty())
810 MI->second[i].PrintArguments(OS);
811 OS << "))\n return Reg;\n\n";
814 // Done with this, remove it.
815 SignaturesWithConstantForms.erase(MI);
818 OS << " switch (Opcode) {\n";
819 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
821 const std::string &Opcode = I->first;
823 OS << " case " << Opcode << ": return FastEmit_"
824 << getLegalCName(Opcode) << "_";
825 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
827 if (!Operands.empty())
829 Operands.PrintArguments(OS);
832 OS << " default: return 0;\n";
838 // TODO: SignaturesWithConstantForms should be empty here.
841 void FastISelEmitter::run(raw_ostream &OS) {
842 const CodeGenTarget &Target = CGP.getTargetInfo();
844 // Determine the target's namespace name.
845 std::string InstNS = Target.getInstNamespace() + "::";
846 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
848 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
849 Target.getName() + " target", OS);
851 FastISelMap F(InstNS);
852 F.collectPatterns(CGP);
853 F.printImmediatePredicates(OS);
854 F.printFunctionDefinitions(OS);
857 FastISelEmitter::FastISelEmitter(RecordKeeper &R)
858 : Records(R), CGP(R) {