1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits code for use by the "fast" instruction
11 // selection algorithm. See the comments at the top of
12 // lib/CodeGen/SelectionDAG/FastISel.cpp for background.
14 // This file scans through the target's tablegen instruction-info files
15 // and extracts instructions with obvious-looking patterns, and it emits
16 // code to look up these instructions by type and operator.
18 //===----------------------------------------------------------------------===//
20 #include "FastISelEmitter.h"
21 #include "llvm/TableGen/Error.h"
22 #include "llvm/TableGen/Record.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
30 /// InstructionMemo - This class holds additional information about an
31 /// instruction needed to emit code for it.
33 struct InstructionMemo {
35 const CodeGenRegisterClass *RC;
37 std::vector<std::string>* PhysRegs;
40 /// ImmPredicateSet - This uniques predicates (represented as a string) and
41 /// gives them unique (small) integer ID's that start at 0.
42 class ImmPredicateSet {
43 DenseMap<TreePattern *, unsigned> ImmIDs;
44 std::vector<TreePredicateFn> PredsByName;
47 unsigned getIDFor(TreePredicateFn Pred) {
48 unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()];
50 PredsByName.push_back(Pred);
51 Entry = PredsByName.size();
56 const TreePredicateFn &getPredicate(unsigned i) {
57 assert(i < PredsByName.size());
58 return PredsByName[i];
61 typedef std::vector<TreePredicateFn>::const_iterator iterator;
62 iterator begin() const { return PredsByName.begin(); }
63 iterator end() const { return PredsByName.end(); }
67 /// OperandsSignature - This class holds a description of a list of operand
68 /// types. It has utility methods for emitting text based on the operands.
70 struct OperandsSignature {
72 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
76 OpKind() : Repr(OK_Invalid) {}
78 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
79 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
81 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; }
82 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; }
83 static OpKind getImm(unsigned V) {
84 assert((unsigned)OK_Imm+V < 128 &&
85 "Too many integer predicates for the 'Repr' char");
86 OpKind K; K.Repr = OK_Imm+V; return K;
89 bool isReg() const { return Repr == OK_Reg; }
90 bool isFP() const { return Repr == OK_FP; }
91 bool isImm() const { return Repr >= OK_Imm; }
93 unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; }
95 void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
96 bool StripImmCodes) const {
104 if (unsigned Code = getImmCode())
105 OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName();
111 SmallVector<OpKind, 3> Operands;
113 bool operator<(const OperandsSignature &O) const {
114 return Operands < O.Operands;
116 bool operator==(const OperandsSignature &O) const {
117 return Operands == O.Operands;
120 bool empty() const { return Operands.empty(); }
122 bool hasAnyImmediateCodes() const {
123 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
124 if (Operands[i].isImm() && Operands[i].getImmCode() != 0)
129 /// getWithoutImmCodes - Return a copy of this with any immediate codes forced
131 OperandsSignature getWithoutImmCodes() const {
132 OperandsSignature Result;
133 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
134 if (!Operands[i].isImm())
135 Result.Operands.push_back(Operands[i]);
137 Result.Operands.push_back(OpKind::getImm(0));
141 void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) {
142 bool EmittedAnything = false;
143 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
144 if (!Operands[i].isImm()) continue;
146 unsigned Code = Operands[i].getImmCode();
147 if (Code == 0) continue;
152 TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1);
154 // Emit the type check.
156 << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0))
160 OS << PredFn.getFnName() << "(imm" << i <<')';
161 EmittedAnything = true;
165 /// initialize - Examine the given pattern and initialize the contents
166 /// of the Operands array accordingly. Return true if all the operands
167 /// are supported, false otherwise.
169 bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target,
170 MVT::SimpleValueType VT,
171 ImmPredicateSet &ImmediatePredicates) {
172 if (InstPatNode->isLeaf())
175 if (InstPatNode->getOperator()->getName() == "imm") {
176 Operands.push_back(OpKind::getImm(0));
180 if (InstPatNode->getOperator()->getName() == "fpimm") {
181 Operands.push_back(OpKind::getFP());
185 const CodeGenRegisterClass *DstRC = 0;
187 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
188 TreePatternNode *Op = InstPatNode->getChild(i);
190 // Handle imm operands specially.
191 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
193 if (!Op->getPredicateFns().empty()) {
194 TreePredicateFn PredFn = Op->getPredicateFns()[0];
195 // If there is more than one predicate weighing in on this operand
196 // then we don't handle it. This doesn't typically happen for
197 // immediates anyway.
198 if (Op->getPredicateFns().size() > 1 ||
199 !PredFn.isImmediatePattern())
201 // Ignore any instruction with 'FastIselShouldIgnore', these are
202 // not needed and just bloat the fast instruction selector. For
203 // example, X86 doesn't need to generate code to match ADD16ri8 since
204 // ADD16ri will do just fine.
205 Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
206 if (Rec->getValueAsBit("FastIselShouldIgnore"))
209 PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
212 // Handle unmatched immediate sizes here.
213 //if (Op->getType(0) != VT)
216 Operands.push_back(OpKind::getImm(PredNo));
221 // For now, filter out any operand with a predicate.
222 // For now, filter out any operand with multiple values.
223 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
227 if (Op->getOperator()->getName() == "fpimm") {
228 Operands.push_back(OpKind::getFP());
231 // For now, ignore other non-leaf nodes.
235 assert(Op->hasTypeSet(0) && "Type infererence not done?");
237 // For now, all the operands must have the same type (if they aren't
238 // immediates). Note that this causes us to reject variable sized shifts
240 if (Op->getType(0) != VT)
243 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
246 Record *OpLeafRec = OpDI->getDef();
248 // For now, the only other thing we accept is register operands.
249 const CodeGenRegisterClass *RC = 0;
250 if (OpLeafRec->isSubClassOf("RegisterOperand"))
251 OpLeafRec = OpLeafRec->getValueAsDef("RegClass");
252 if (OpLeafRec->isSubClassOf("RegisterClass"))
253 RC = &Target.getRegisterClass(OpLeafRec);
254 else if (OpLeafRec->isSubClassOf("Register"))
255 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
259 // For now, this needs to be a register class of some sort.
263 // For now, all the operands must have the same register class or be
264 // a strict subclass of the destination.
266 if (DstRC != RC && !DstRC->hasSubClass(RC))
270 Operands.push_back(OpKind::getReg());
275 void PrintParameters(raw_ostream &OS) const {
276 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
277 if (Operands[i].isReg()) {
278 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
279 } else if (Operands[i].isImm()) {
280 OS << "uint64_t imm" << i;
281 } else if (Operands[i].isFP()) {
282 OS << "const ConstantFP *f" << i;
284 llvm_unreachable("Unknown operand kind!");
291 void PrintArguments(raw_ostream &OS,
292 const std::vector<std::string> &PR) const {
293 assert(PR.size() == Operands.size());
294 bool PrintedArg = false;
295 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
297 // Implicit physical register operand.
302 if (Operands[i].isReg()) {
303 OS << "Op" << i << ", Op" << i << "IsKill";
305 } else if (Operands[i].isImm()) {
308 } else if (Operands[i].isFP()) {
312 llvm_unreachable("Unknown operand kind!");
317 void PrintArguments(raw_ostream &OS) const {
318 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
319 if (Operands[i].isReg()) {
320 OS << "Op" << i << ", Op" << i << "IsKill";
321 } else if (Operands[i].isImm()) {
323 } else if (Operands[i].isFP()) {
326 llvm_unreachable("Unknown operand kind!");
334 void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR,
335 ImmPredicateSet &ImmPredicates,
336 bool StripImmCodes = false) const {
337 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
339 // Implicit physical register operand. e.g. Instruction::Mul expect to
340 // select to a binary op. On x86, mul may take a single operand with
341 // the other operand being implicit. We must emit something that looks
342 // like a binary instruction except for the very inner FastEmitInst_*
345 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
349 void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
350 bool StripImmCodes = false) const {
351 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
352 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
357 typedef std::map<std::string, InstructionMemo> PredMap;
358 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
359 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
360 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
361 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
362 OperandsOpcodeTypeRetPredMap;
364 OperandsOpcodeTypeRetPredMap SimplePatterns;
366 std::map<OperandsSignature, std::vector<OperandsSignature> >
367 SignaturesWithConstantForms;
370 ImmPredicateSet ImmediatePredicates;
372 explicit FastISelMap(std::string InstNS);
374 void collectPatterns(CodeGenDAGPatterns &CGP);
375 void printImmediatePredicates(raw_ostream &OS);
376 void printFunctionDefinitions(raw_ostream &OS);
381 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
382 return CGP.getSDNodeInfo(Op).getEnumName();
385 static std::string getLegalCName(std::string OpName) {
386 std::string::size_type pos = OpName.find("::");
387 if (pos != std::string::npos)
388 OpName.replace(pos, 2, "_");
392 FastISelMap::FastISelMap(std::string instns)
396 static std::string PhyRegForNode(TreePatternNode *Op,
397 const CodeGenTarget &Target) {
403 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
404 Record *OpLeafRec = OpDI->getDef();
405 if (!OpLeafRec->isSubClassOf("Register"))
408 PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
409 "Namespace")->getValue())->getValue();
411 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
415 void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
416 const CodeGenTarget &Target = CGP.getTargetInfo();
418 // Determine the target's namespace name.
419 InstNS = Target.getInstNamespace() + "::";
420 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
422 // Scan through all the patterns and record the simple ones.
423 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
424 E = CGP.ptm_end(); I != E; ++I) {
425 const PatternToMatch &Pattern = *I;
427 // For now, just look at Instructions, so that we don't have to worry
428 // about emitting multiple instructions for a pattern.
429 TreePatternNode *Dst = Pattern.getDstPattern();
430 if (Dst->isLeaf()) continue;
431 Record *Op = Dst->getOperator();
432 if (!Op->isSubClassOf("Instruction"))
434 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
435 if (II.Operands.empty())
438 // For now, ignore multi-instruction patterns.
439 bool MultiInsts = false;
440 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
441 TreePatternNode *ChildOp = Dst->getChild(i);
442 if (ChildOp->isLeaf())
444 if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
452 // For now, ignore instructions where the first operand is not an
454 const CodeGenRegisterClass *DstRC = 0;
455 std::string SubRegNo;
456 if (Op->getName() != "EXTRACT_SUBREG") {
457 Record *Op0Rec = II.Operands[0].Rec;
458 if (Op0Rec->isSubClassOf("RegisterOperand"))
459 Op0Rec = Op0Rec->getValueAsDef("RegClass");
460 if (!Op0Rec->isSubClassOf("RegisterClass"))
462 DstRC = &Target.getRegisterClass(Op0Rec);
466 // If this isn't a leaf, then continue since the register classes are
467 // a bit too complicated for now.
468 if (!Dst->getChild(1)->isLeaf()) continue;
470 DefInit *SR = dynamic_cast<DefInit*>(Dst->getChild(1)->getLeafValue());
472 SubRegNo = getQualifiedName(SR->getDef());
474 SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString();
477 // Inspect the pattern.
478 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
479 if (!InstPatNode) continue;
480 if (InstPatNode->isLeaf()) continue;
482 // Ignore multiple result nodes for now.
483 if (InstPatNode->getNumTypes() > 1) continue;
485 Record *InstPatOp = InstPatNode->getOperator();
486 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
487 MVT::SimpleValueType RetVT = MVT::isVoid;
488 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
489 MVT::SimpleValueType VT = RetVT;
490 if (InstPatNode->getNumChildren()) {
491 assert(InstPatNode->getChild(0)->getNumTypes() == 1);
492 VT = InstPatNode->getChild(0)->getType(0);
495 // For now, filter out any instructions with predicates.
496 if (!InstPatNode->getPredicateFns().empty())
499 // Check all the operands.
500 OperandsSignature Operands;
501 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates))
504 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
505 if (InstPatNode->getOperator()->getName() == "imm" ||
506 InstPatNode->getOperator()->getName() == "fpimm")
507 PhysRegInputs->push_back("");
509 // Compute the PhysRegs used by the given pattern, and check that
510 // the mapping from the src to dst patterns is simple.
511 bool FoundNonSimplePattern = false;
512 unsigned DstIndex = 0;
513 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
514 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
515 if (PhysReg.empty()) {
516 if (DstIndex >= Dst->getNumChildren() ||
517 Dst->getChild(DstIndex)->getName() !=
518 InstPatNode->getChild(i)->getName()) {
519 FoundNonSimplePattern = true;
525 PhysRegInputs->push_back(PhysReg);
528 if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren())
529 FoundNonSimplePattern = true;
531 if (FoundNonSimplePattern)
535 // Get the predicate that guards this pattern.
536 std::string PredicateCheck = Pattern.getPredicateCheck();
538 // Ok, we found a pattern that we can handle. Remember it.
539 InstructionMemo Memo = {
540 Pattern.getDstPattern()->getOperator()->getName(),
546 if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck))
547 throw TGError(Pattern.getSrcRecord()->getLoc(),
548 "Duplicate record in FastISel table!");
550 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
552 // If any of the operands were immediates with predicates on them, strip
553 // them down to a signature that doesn't have predicates so that we can
554 // associate them with the stripped predicate version.
555 if (Operands.hasAnyImmediateCodes()) {
556 SignaturesWithConstantForms[Operands.getWithoutImmCodes()]
557 .push_back(Operands);
562 void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
563 if (ImmediatePredicates.begin() == ImmediatePredicates.end())
566 OS << "\n// FastEmit Immediate Predicate functions.\n";
567 for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
568 E = ImmediatePredicates.end(); I != E; ++I) {
569 OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
570 OS << I->getImmediatePredicateCode() << "\n}\n";
577 void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
578 // Now emit code for all the patterns that we collected.
579 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
580 OE = SimplePatterns.end(); OI != OE; ++OI) {
581 const OperandsSignature &Operands = OI->first;
582 const OpcodeTypeRetPredMap &OTM = OI->second;
584 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
586 const std::string &Opcode = I->first;
587 const TypeRetPredMap &TM = I->second;
589 OS << "// FastEmit functions for " << Opcode << ".\n";
592 // Emit one function for each opcode,type pair.
593 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
595 MVT::SimpleValueType VT = TI->first;
596 const RetPredMap &RM = TI->second;
597 if (RM.size() != 1) {
598 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
600 MVT::SimpleValueType RetVT = RI->first;
601 const PredMap &PM = RI->second;
602 bool HasPred = false;
604 OS << "unsigned FastEmit_"
605 << getLegalCName(Opcode)
606 << "_" << getLegalCName(getName(VT))
607 << "_" << getLegalCName(getName(RetVT)) << "_";
608 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
610 Operands.PrintParameters(OS);
613 // Emit code for each possible instruction. There may be
614 // multiple if there are subtarget concerns.
615 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
617 std::string PredicateCheck = PI->first;
618 const InstructionMemo &Memo = PI->second;
620 if (PredicateCheck.empty()) {
622 "Multiple instructions match, at least one has "
623 "a predicate and at least one doesn't!");
625 OS << " if (" + PredicateCheck + ") {\n";
630 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
631 if ((*Memo.PhysRegs)[i] != "")
632 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
633 << "TII.get(TargetOpcode::COPY), "
634 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
637 OS << " return FastEmitInst_";
638 if (Memo.SubRegNo.empty()) {
639 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
640 ImmediatePredicates, true);
641 OS << "(" << InstNS << Memo.Name << ", ";
642 OS << InstNS << Memo.RC->getName() << "RegisterClass";
643 if (!Operands.empty())
645 Operands.PrintArguments(OS, *Memo.PhysRegs);
648 OS << "extractsubreg(" << getName(RetVT);
649 OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n";
656 // Return 0 if none of the predicates were satisfied.
658 OS << " return 0;\n";
663 // Emit one function for the type that demultiplexes on return type.
664 OS << "unsigned FastEmit_"
665 << getLegalCName(Opcode) << "_"
666 << getLegalCName(getName(VT)) << "_";
667 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
669 if (!Operands.empty())
671 Operands.PrintParameters(OS);
672 OS << ") {\nswitch (RetVT.SimpleTy) {\n";
673 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
675 MVT::SimpleValueType RetVT = RI->first;
676 OS << " case " << getName(RetVT) << ": return FastEmit_"
677 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
678 << "_" << getLegalCName(getName(RetVT)) << "_";
679 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
681 Operands.PrintArguments(OS);
684 OS << " default: return 0;\n}\n}\n\n";
687 // Non-variadic return type.
688 OS << "unsigned FastEmit_"
689 << getLegalCName(Opcode) << "_"
690 << getLegalCName(getName(VT)) << "_";
691 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
693 if (!Operands.empty())
695 Operands.PrintParameters(OS);
698 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
699 << ")\n return 0;\n";
701 const PredMap &PM = RM.begin()->second;
702 bool HasPred = false;
704 // Emit code for each possible instruction. There may be
705 // multiple if there are subtarget concerns.
706 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
708 std::string PredicateCheck = PI->first;
709 const InstructionMemo &Memo = PI->second;
711 if (PredicateCheck.empty()) {
713 "Multiple instructions match, at least one has "
714 "a predicate and at least one doesn't!");
716 OS << " if (" + PredicateCheck + ") {\n";
721 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
722 if ((*Memo.PhysRegs)[i] != "")
723 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
724 << "TII.get(TargetOpcode::COPY), "
725 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
728 OS << " return FastEmitInst_";
730 if (Memo.SubRegNo.empty()) {
731 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
732 ImmediatePredicates, true);
733 OS << "(" << InstNS << Memo.Name << ", ";
734 OS << InstNS << Memo.RC->getName() << "RegisterClass";
735 if (!Operands.empty())
737 Operands.PrintArguments(OS, *Memo.PhysRegs);
740 OS << "extractsubreg(RetVT, Op0, Op0IsKill, ";
749 // Return 0 if none of the predicates were satisfied.
751 OS << " return 0;\n";
757 // Emit one function for the opcode that demultiplexes based on the type.
758 OS << "unsigned FastEmit_"
759 << getLegalCName(Opcode) << "_";
760 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
761 OS << "(MVT VT, MVT RetVT";
762 if (!Operands.empty())
764 Operands.PrintParameters(OS);
766 OS << " switch (VT.SimpleTy) {\n";
767 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
769 MVT::SimpleValueType VT = TI->first;
770 std::string TypeName = getName(VT);
771 OS << " case " << TypeName << ": return FastEmit_"
772 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
773 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
775 if (!Operands.empty())
777 Operands.PrintArguments(OS);
780 OS << " default: return 0;\n";
786 OS << "// Top-level FastEmit function.\n";
789 // Emit one function for the operand signature that demultiplexes based
790 // on opcode and type.
791 OS << "unsigned FastEmit_";
792 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
793 OS << "(MVT VT, MVT RetVT, unsigned Opcode";
794 if (!Operands.empty())
796 Operands.PrintParameters(OS);
799 // If there are any forms of this signature available that operand on
800 // constrained forms of the immediate (e.g. 32-bit sext immediate in a
801 // 64-bit operand), check them first.
803 std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI
804 = SignaturesWithConstantForms.find(Operands);
805 if (MI != SignaturesWithConstantForms.end()) {
806 // Unique any duplicates out of the list.
807 std::sort(MI->second.begin(), MI->second.end());
808 MI->second.erase(std::unique(MI->second.begin(), MI->second.end()),
811 // Check each in order it was seen. It would be nice to have a good
812 // relative ordering between them, but we're not going for optimality
814 for (unsigned i = 0, e = MI->second.size(); i != e; ++i) {
816 MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates);
817 OS << ")\n if (unsigned Reg = FastEmit_";
818 MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates);
819 OS << "(VT, RetVT, Opcode";
820 if (!MI->second[i].empty())
822 MI->second[i].PrintArguments(OS);
823 OS << "))\n return Reg;\n\n";
826 // Done with this, remove it.
827 SignaturesWithConstantForms.erase(MI);
830 OS << " switch (Opcode) {\n";
831 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
833 const std::string &Opcode = I->first;
835 OS << " case " << Opcode << ": return FastEmit_"
836 << getLegalCName(Opcode) << "_";
837 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
839 if (!Operands.empty())
841 Operands.PrintArguments(OS);
844 OS << " default: return 0;\n";
850 // TODO: SignaturesWithConstantForms should be empty here.
853 void FastISelEmitter::run(raw_ostream &OS) {
854 const CodeGenTarget &Target = CGP.getTargetInfo();
856 // Determine the target's namespace name.
857 std::string InstNS = Target.getInstNamespace() + "::";
858 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
860 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
861 Target.getName() + " target", OS);
863 FastISelMap F(InstNS);
864 F.collectPatterns(CGP);
865 F.printImmediatePredicates(OS);
866 F.printFunctionDefinitions(OS);
869 FastISelEmitter::FastISelEmitter(RecordKeeper &R)
870 : Records(R), CGP(R) {