1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits code for use by the "fast" instruction
11 // selection algorithm. See the comments at the top of
12 // lib/CodeGen/SelectionDAG/FastISel.cpp for background.
14 // This file scans through the target's tablegen instruction-info files
15 // and extracts instructions with obvious-looking patterns, and it emits
16 // code to look up these instructions by type and operator.
18 //===----------------------------------------------------------------------===//
20 #include "FastISelEmitter.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/VectorExtras.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
31 /// InstructionMemo - This class holds additional information about an
32 /// instruction needed to emit code for it.
34 struct InstructionMemo {
36 const CodeGenRegisterClass *RC;
38 std::vector<std::string>* PhysRegs;
41 /// ImmPredicateSet - This uniques predicates (represented as a string) and
42 /// gives them unique (small) integer ID's that start at 0.
43 class ImmPredicateSet {
44 DenseMap<TreePattern *, unsigned> ImmIDs;
45 std::vector<TreePredicateFn> PredsByName;
48 unsigned getIDFor(TreePredicateFn Pred) {
49 unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()];
51 PredsByName.push_back(Pred);
52 Entry = PredsByName.size();
57 const TreePredicateFn &getPredicate(unsigned i) {
58 assert(i < PredsByName.size());
59 return PredsByName[i];
62 typedef std::vector<TreePredicateFn>::const_iterator iterator;
63 iterator begin() const { return PredsByName.begin(); }
64 iterator end() const { return PredsByName.end(); }
68 /// OperandsSignature - This class holds a description of a list of operand
69 /// types. It has utility methods for emitting text based on the operands.
71 struct OperandsSignature {
73 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
77 OpKind() : Repr(OK_Invalid) {}
79 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
80 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
82 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; }
83 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; }
84 static OpKind getImm(unsigned V) {
85 assert((unsigned)OK_Imm+V < 128 &&
86 "Too many integer predicates for the 'Repr' char");
87 OpKind K; K.Repr = OK_Imm+V; return K;
90 bool isReg() const { return Repr == OK_Reg; }
91 bool isFP() const { return Repr == OK_FP; }
92 bool isImm() const { return Repr >= OK_Imm; }
94 unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; }
96 void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
97 bool StripImmCodes) const {
105 if (unsigned Code = getImmCode())
106 OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName();
112 SmallVector<OpKind, 3> Operands;
114 bool operator<(const OperandsSignature &O) const {
115 return Operands < O.Operands;
117 bool operator==(const OperandsSignature &O) const {
118 return Operands == O.Operands;
121 bool empty() const { return Operands.empty(); }
123 bool hasAnyImmediateCodes() const {
124 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
125 if (Operands[i].isImm() && Operands[i].getImmCode() != 0)
130 /// getWithoutImmCodes - Return a copy of this with any immediate codes forced
132 OperandsSignature getWithoutImmCodes() const {
133 OperandsSignature Result;
134 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
135 if (!Operands[i].isImm())
136 Result.Operands.push_back(Operands[i]);
138 Result.Operands.push_back(OpKind::getImm(0));
142 void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) {
143 bool EmittedAnything = false;
144 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
145 if (!Operands[i].isImm()) continue;
147 unsigned Code = Operands[i].getImmCode();
148 if (Code == 0) continue;
153 TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1);
155 // Emit the type check.
157 << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0))
161 OS << PredFn.getFnName() << "(imm" << i <<')';
162 EmittedAnything = true;
166 /// initialize - Examine the given pattern and initialize the contents
167 /// of the Operands array accordingly. Return true if all the operands
168 /// are supported, false otherwise.
170 bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target,
171 MVT::SimpleValueType VT,
172 ImmPredicateSet &ImmediatePredicates) {
173 if (InstPatNode->isLeaf())
176 if (InstPatNode->getOperator()->getName() == "imm") {
177 Operands.push_back(OpKind::getImm(0));
181 if (InstPatNode->getOperator()->getName() == "fpimm") {
182 Operands.push_back(OpKind::getFP());
186 const CodeGenRegisterClass *DstRC = 0;
188 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
189 TreePatternNode *Op = InstPatNode->getChild(i);
191 // Handle imm operands specially.
192 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
194 if (!Op->getPredicateFns().empty()) {
195 TreePredicateFn PredFn = Op->getPredicateFns()[0];
196 // If there is more than one predicate weighing in on this operand
197 // then we don't handle it. This doesn't typically happen for
198 // immediates anyway.
199 if (Op->getPredicateFns().size() > 1 ||
200 !PredFn.isImmediatePattern())
202 // Ignore any instruction with 'FastIselShouldIgnore', these are
203 // not needed and just bloat the fast instruction selector. For
204 // example, X86 doesn't need to generate code to match ADD16ri8 since
205 // ADD16ri will do just fine.
206 Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
207 if (Rec->getValueAsBit("FastIselShouldIgnore"))
210 PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
213 // Handle unmatched immediate sizes here.
214 //if (Op->getType(0) != VT)
217 Operands.push_back(OpKind::getImm(PredNo));
222 // For now, filter out any operand with a predicate.
223 // For now, filter out any operand with multiple values.
224 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
228 if (Op->getOperator()->getName() == "fpimm") {
229 Operands.push_back(OpKind::getFP());
232 // For now, ignore other non-leaf nodes.
236 assert(Op->hasTypeSet(0) && "Type infererence not done?");
238 // For now, all the operands must have the same type (if they aren't
239 // immediates). Note that this causes us to reject variable sized shifts
241 if (Op->getType(0) != VT)
244 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
247 Record *OpLeafRec = OpDI->getDef();
249 // For now, the only other thing we accept is register operands.
250 const CodeGenRegisterClass *RC = 0;
251 if (OpLeafRec->isSubClassOf("RegisterClass"))
252 RC = &Target.getRegisterClass(OpLeafRec);
253 else if (OpLeafRec->isSubClassOf("Register"))
254 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
258 // For now, this needs to be a register class of some sort.
262 // For now, all the operands must have the same register class or be
263 // a strict subclass of the destination.
265 if (DstRC != RC && !DstRC->hasSubClass(RC))
269 Operands.push_back(OpKind::getReg());
274 void PrintParameters(raw_ostream &OS) const {
275 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
276 if (Operands[i].isReg()) {
277 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
278 } else if (Operands[i].isImm()) {
279 OS << "uint64_t imm" << i;
280 } else if (Operands[i].isFP()) {
281 OS << "ConstantFP *f" << i;
283 llvm_unreachable("Unknown operand kind!");
290 void PrintArguments(raw_ostream &OS,
291 const std::vector<std::string> &PR) const {
292 assert(PR.size() == Operands.size());
293 bool PrintedArg = false;
294 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
296 // Implicit physical register operand.
301 if (Operands[i].isReg()) {
302 OS << "Op" << i << ", Op" << i << "IsKill";
304 } else if (Operands[i].isImm()) {
307 } else if (Operands[i].isFP()) {
311 llvm_unreachable("Unknown operand kind!");
316 void PrintArguments(raw_ostream &OS) const {
317 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
318 if (Operands[i].isReg()) {
319 OS << "Op" << i << ", Op" << i << "IsKill";
320 } else if (Operands[i].isImm()) {
322 } else if (Operands[i].isFP()) {
325 llvm_unreachable("Unknown operand kind!");
333 void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR,
334 ImmPredicateSet &ImmPredicates,
335 bool StripImmCodes = false) const {
336 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
338 // Implicit physical register operand. e.g. Instruction::Mul expect to
339 // select to a binary op. On x86, mul may take a single operand with
340 // the other operand being implicit. We must emit something that looks
341 // like a binary instruction except for the very inner FastEmitInst_*
344 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
348 void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
349 bool StripImmCodes = false) const {
350 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
351 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
356 typedef std::map<std::string, InstructionMemo> PredMap;
357 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
358 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
359 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
360 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
361 OperandsOpcodeTypeRetPredMap;
363 OperandsOpcodeTypeRetPredMap SimplePatterns;
365 std::map<OperandsSignature, std::vector<OperandsSignature> >
366 SignaturesWithConstantForms;
369 ImmPredicateSet ImmediatePredicates;
371 explicit FastISelMap(std::string InstNS);
373 void collectPatterns(CodeGenDAGPatterns &CGP);
374 void printImmediatePredicates(raw_ostream &OS);
375 void printFunctionDefinitions(raw_ostream &OS);
380 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
381 return CGP.getSDNodeInfo(Op).getEnumName();
384 static std::string getLegalCName(std::string OpName) {
385 std::string::size_type pos = OpName.find("::");
386 if (pos != std::string::npos)
387 OpName.replace(pos, 2, "_");
391 FastISelMap::FastISelMap(std::string instns)
395 static std::string PhyRegForNode(TreePatternNode *Op,
396 const CodeGenTarget &Target) {
402 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
403 Record *OpLeafRec = OpDI->getDef();
404 if (!OpLeafRec->isSubClassOf("Register"))
407 PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
408 "Namespace")->getValue())->getValue();
410 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
414 void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
415 const CodeGenTarget &Target = CGP.getTargetInfo();
417 // Determine the target's namespace name.
418 InstNS = Target.getInstNamespace() + "::";
419 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
421 // Scan through all the patterns and record the simple ones.
422 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
423 E = CGP.ptm_end(); I != E; ++I) {
424 const PatternToMatch &Pattern = *I;
426 // For now, just look at Instructions, so that we don't have to worry
427 // about emitting multiple instructions for a pattern.
428 TreePatternNode *Dst = Pattern.getDstPattern();
429 if (Dst->isLeaf()) continue;
430 Record *Op = Dst->getOperator();
431 if (!Op->isSubClassOf("Instruction"))
433 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
434 if (II.Operands.empty())
437 // For now, ignore multi-instruction patterns.
438 bool MultiInsts = false;
439 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
440 TreePatternNode *ChildOp = Dst->getChild(i);
441 if (ChildOp->isLeaf())
443 if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
451 // For now, ignore instructions where the first operand is not an
453 const CodeGenRegisterClass *DstRC = 0;
454 std::string SubRegNo;
455 if (Op->getName() != "EXTRACT_SUBREG") {
456 Record *Op0Rec = II.Operands[0].Rec;
457 if (!Op0Rec->isSubClassOf("RegisterClass"))
459 DstRC = &Target.getRegisterClass(Op0Rec);
463 // If this isn't a leaf, then continue since the register classes are
464 // a bit too complicated for now.
465 if (!Dst->getChild(1)->isLeaf()) continue;
467 DefInit *SR = dynamic_cast<DefInit*>(Dst->getChild(1)->getLeafValue());
469 SubRegNo = getQualifiedName(SR->getDef());
471 SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString();
474 // Inspect the pattern.
475 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
476 if (!InstPatNode) continue;
477 if (InstPatNode->isLeaf()) continue;
479 // Ignore multiple result nodes for now.
480 if (InstPatNode->getNumTypes() > 1) continue;
482 Record *InstPatOp = InstPatNode->getOperator();
483 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
484 MVT::SimpleValueType RetVT = MVT::isVoid;
485 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
486 MVT::SimpleValueType VT = RetVT;
487 if (InstPatNode->getNumChildren()) {
488 assert(InstPatNode->getChild(0)->getNumTypes() == 1);
489 VT = InstPatNode->getChild(0)->getType(0);
492 // For now, filter out any instructions with predicates.
493 if (!InstPatNode->getPredicateFns().empty())
496 // Check all the operands.
497 OperandsSignature Operands;
498 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates))
501 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
502 if (InstPatNode->getOperator()->getName() == "imm" ||
503 InstPatNode->getOperator()->getName() == "fpimmm")
504 PhysRegInputs->push_back("");
506 // Compute the PhysRegs used by the given pattern, and check that
507 // the mapping from the src to dst patterns is simple.
508 bool FoundNonSimplePattern = false;
509 unsigned DstIndex = 0;
510 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
511 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
512 if (PhysReg.empty()) {
513 if (DstIndex >= Dst->getNumChildren() ||
514 Dst->getChild(DstIndex)->getName() !=
515 InstPatNode->getChild(i)->getName()) {
516 FoundNonSimplePattern = true;
522 PhysRegInputs->push_back(PhysReg);
525 if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren())
526 FoundNonSimplePattern = true;
528 if (FoundNonSimplePattern)
532 // Get the predicate that guards this pattern.
533 std::string PredicateCheck = Pattern.getPredicateCheck();
535 // Ok, we found a pattern that we can handle. Remember it.
536 InstructionMemo Memo = {
537 Pattern.getDstPattern()->getOperator()->getName(),
543 if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck))
544 throw TGError(Pattern.getSrcRecord()->getLoc(),
545 "Duplicate record in FastISel table!");
547 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
549 // If any of the operands were immediates with predicates on them, strip
550 // them down to a signature that doesn't have predicates so that we can
551 // associate them with the stripped predicate version.
552 if (Operands.hasAnyImmediateCodes()) {
553 SignaturesWithConstantForms[Operands.getWithoutImmCodes()]
554 .push_back(Operands);
559 void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
560 if (ImmediatePredicates.begin() == ImmediatePredicates.end())
563 OS << "\n// FastEmit Immediate Predicate functions.\n";
564 for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
565 E = ImmediatePredicates.end(); I != E; ++I) {
566 OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
567 OS << I->getImmediatePredicateCode() << "\n}\n";
574 void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
575 // Now emit code for all the patterns that we collected.
576 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
577 OE = SimplePatterns.end(); OI != OE; ++OI) {
578 const OperandsSignature &Operands = OI->first;
579 const OpcodeTypeRetPredMap &OTM = OI->second;
581 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
583 const std::string &Opcode = I->first;
584 const TypeRetPredMap &TM = I->second;
586 OS << "// FastEmit functions for " << Opcode << ".\n";
589 // Emit one function for each opcode,type pair.
590 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
592 MVT::SimpleValueType VT = TI->first;
593 const RetPredMap &RM = TI->second;
594 if (RM.size() != 1) {
595 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
597 MVT::SimpleValueType RetVT = RI->first;
598 const PredMap &PM = RI->second;
599 bool HasPred = false;
601 OS << "unsigned FastEmit_"
602 << getLegalCName(Opcode)
603 << "_" << getLegalCName(getName(VT))
604 << "_" << getLegalCName(getName(RetVT)) << "_";
605 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
607 Operands.PrintParameters(OS);
610 // Emit code for each possible instruction. There may be
611 // multiple if there are subtarget concerns.
612 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
614 std::string PredicateCheck = PI->first;
615 const InstructionMemo &Memo = PI->second;
617 if (PredicateCheck.empty()) {
619 "Multiple instructions match, at least one has "
620 "a predicate and at least one doesn't!");
622 OS << " if (" + PredicateCheck + ") {\n";
627 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
628 if ((*Memo.PhysRegs)[i] != "")
629 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
630 << "TII.get(TargetOpcode::COPY), "
631 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
634 OS << " return FastEmitInst_";
635 if (Memo.SubRegNo.empty()) {
636 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
637 ImmediatePredicates, true);
638 OS << "(" << InstNS << Memo.Name << ", ";
639 OS << InstNS << Memo.RC->getName() << "RegisterClass";
640 if (!Operands.empty())
642 Operands.PrintArguments(OS, *Memo.PhysRegs);
645 OS << "extractsubreg(" << getName(RetVT);
646 OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n";
653 // Return 0 if none of the predicates were satisfied.
655 OS << " return 0;\n";
660 // Emit one function for the type that demultiplexes on return type.
661 OS << "unsigned FastEmit_"
662 << getLegalCName(Opcode) << "_"
663 << getLegalCName(getName(VT)) << "_";
664 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
666 if (!Operands.empty())
668 Operands.PrintParameters(OS);
669 OS << ") {\nswitch (RetVT.SimpleTy) {\n";
670 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
672 MVT::SimpleValueType RetVT = RI->first;
673 OS << " case " << getName(RetVT) << ": return FastEmit_"
674 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
675 << "_" << getLegalCName(getName(RetVT)) << "_";
676 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
678 Operands.PrintArguments(OS);
681 OS << " default: return 0;\n}\n}\n\n";
684 // Non-variadic return type.
685 OS << "unsigned FastEmit_"
686 << getLegalCName(Opcode) << "_"
687 << getLegalCName(getName(VT)) << "_";
688 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
690 if (!Operands.empty())
692 Operands.PrintParameters(OS);
695 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
696 << ")\n return 0;\n";
698 const PredMap &PM = RM.begin()->second;
699 bool HasPred = false;
701 // Emit code for each possible instruction. There may be
702 // multiple if there are subtarget concerns.
703 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
705 std::string PredicateCheck = PI->first;
706 const InstructionMemo &Memo = PI->second;
708 if (PredicateCheck.empty()) {
710 "Multiple instructions match, at least one has "
711 "a predicate and at least one doesn't!");
713 OS << " if (" + PredicateCheck + ") {\n";
718 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
719 if ((*Memo.PhysRegs)[i] != "")
720 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
721 << "TII.get(TargetOpcode::COPY), "
722 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
725 OS << " return FastEmitInst_";
727 if (Memo.SubRegNo.empty()) {
728 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
729 ImmediatePredicates, true);
730 OS << "(" << InstNS << Memo.Name << ", ";
731 OS << InstNS << Memo.RC->getName() << "RegisterClass";
732 if (!Operands.empty())
734 Operands.PrintArguments(OS, *Memo.PhysRegs);
737 OS << "extractsubreg(RetVT, Op0, Op0IsKill, ";
746 // Return 0 if none of the predicates were satisfied.
748 OS << " return 0;\n";
754 // Emit one function for the opcode that demultiplexes based on the type.
755 OS << "unsigned FastEmit_"
756 << getLegalCName(Opcode) << "_";
757 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
758 OS << "(MVT VT, MVT RetVT";
759 if (!Operands.empty())
761 Operands.PrintParameters(OS);
763 OS << " switch (VT.SimpleTy) {\n";
764 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
766 MVT::SimpleValueType VT = TI->first;
767 std::string TypeName = getName(VT);
768 OS << " case " << TypeName << ": return FastEmit_"
769 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
770 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
772 if (!Operands.empty())
774 Operands.PrintArguments(OS);
777 OS << " default: return 0;\n";
783 OS << "// Top-level FastEmit function.\n";
786 // Emit one function for the operand signature that demultiplexes based
787 // on opcode and type.
788 OS << "unsigned FastEmit_";
789 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
790 OS << "(MVT VT, MVT RetVT, unsigned Opcode";
791 if (!Operands.empty())
793 Operands.PrintParameters(OS);
796 // If there are any forms of this signature available that operand on
797 // constrained forms of the immediate (e.g. 32-bit sext immediate in a
798 // 64-bit operand), check them first.
800 std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI
801 = SignaturesWithConstantForms.find(Operands);
802 if (MI != SignaturesWithConstantForms.end()) {
803 // Unique any duplicates out of the list.
804 std::sort(MI->second.begin(), MI->second.end());
805 MI->second.erase(std::unique(MI->second.begin(), MI->second.end()),
808 // Check each in order it was seen. It would be nice to have a good
809 // relative ordering between them, but we're not going for optimality
811 for (unsigned i = 0, e = MI->second.size(); i != e; ++i) {
813 MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates);
814 OS << ")\n if (unsigned Reg = FastEmit_";
815 MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates);
816 OS << "(VT, RetVT, Opcode";
817 if (!MI->second[i].empty())
819 MI->second[i].PrintArguments(OS);
820 OS << "))\n return Reg;\n\n";
823 // Done with this, remove it.
824 SignaturesWithConstantForms.erase(MI);
827 OS << " switch (Opcode) {\n";
828 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
830 const std::string &Opcode = I->first;
832 OS << " case " << Opcode << ": return FastEmit_"
833 << getLegalCName(Opcode) << "_";
834 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
836 if (!Operands.empty())
838 Operands.PrintArguments(OS);
841 OS << " default: return 0;\n";
847 // TODO: SignaturesWithConstantForms should be empty here.
850 void FastISelEmitter::run(raw_ostream &OS) {
851 const CodeGenTarget &Target = CGP.getTargetInfo();
853 // Determine the target's namespace name.
854 std::string InstNS = Target.getInstNamespace() + "::";
855 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
857 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
858 Target.getName() + " target", OS);
860 FastISelMap F(InstNS);
861 F.collectPatterns(CGP);
862 F.printImmediatePredicates(OS);
863 F.printFunctionDefinitions(OS);
866 FastISelEmitter::FastISelEmitter(RecordKeeper &R)
867 : Records(R), CGP(R) {