1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
18 #include "llvm/ADT/StringExtras.h"
22 static void PrintDefList(const std::vector<Record*> &Uses,
23 unsigned Num, raw_ostream &OS) {
24 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
25 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
26 OS << getQualifiedName(Uses[i]) << ", ";
30 //===----------------------------------------------------------------------===//
31 // Instruction Itinerary Information.
32 //===----------------------------------------------------------------------===//
34 void InstrInfoEmitter::GatherItinClasses() {
35 std::vector<Record*> DefList =
36 Records.getAllDerivedDefinitions("InstrItinClass");
37 std::sort(DefList.begin(), DefList.end(), LessRecord());
39 for (unsigned i = 0, N = DefList.size(); i < N; i++)
40 ItinClassMap[DefList[i]->getName()] = i;
43 unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
44 return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
47 //===----------------------------------------------------------------------===//
48 // Operand Info Emission.
49 //===----------------------------------------------------------------------===//
51 std::vector<std::string>
52 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
53 std::vector<std::string> Result;
55 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
56 // Handle aggregate operands and normal operands the same way by expanding
57 // either case into a list of operands for this op.
58 std::vector<CGIOperandList::OperandInfo> OperandList;
60 // This might be a multiple operand thing. Targets like X86 have
61 // registers in their multi-operand operands. It may also be an anonymous
62 // operand, which has a single operand, but no declared class for the
64 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
66 if (!MIOI || MIOI->getNumArgs() == 0) {
67 // Single, anonymous, operand.
68 OperandList.push_back(Inst.Operands[i]);
70 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
71 OperandList.push_back(Inst.Operands[i]);
73 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
74 OperandList.back().Rec = OpR;
78 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
79 Record *OpR = OperandList[j].Rec;
82 if (OpR->isSubClassOf("RegisterOperand"))
83 OpR = OpR->getValueAsDef("RegClass");
84 if (OpR->isSubClassOf("RegisterClass"))
85 Res += getQualifiedName(OpR) + "RegClassID, ";
86 else if (OpR->isSubClassOf("PointerLikeRegClass"))
87 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
89 // -1 means the operand does not have a fixed register class.
92 // Fill in applicable flags.
95 // Ptr value whose register class is resolved via callback.
96 if (OpR->isSubClassOf("PointerLikeRegClass"))
97 Res += "|(1<<TOI::LookupPtrRegClass)";
99 // Predicate operands. Check to see if the original unexpanded operand
100 // was of type PredicateOperand.
101 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
102 Res += "|(1<<TOI::Predicate)";
104 // Optional def operands. Check to see if the original unexpanded operand
105 // was of type OptionalDefOperand.
106 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
107 Res += "|(1<<TOI::OptionalDef)";
109 // Fill in constraint info.
112 const CGIOperandList::ConstraintInfo &Constraint =
113 Inst.Operands[i].Constraints[j];
114 if (Constraint.isNone())
116 else if (Constraint.isEarlyClobber())
117 Res += "(1 << TOI::EARLY_CLOBBER)";
119 assert(Constraint.isTied());
120 Res += "((" + utostr(Constraint.getTiedOperand()) +
121 " << 16) | (1 << TOI::TIED_TO))";
124 Result.push_back(Res);
131 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
132 OperandInfoMapTy &OperandInfoIDs) {
133 // ID #0 is for no operand info.
134 unsigned OperandListNum = 0;
135 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
138 const CodeGenTarget &Target = CDP.getTargetInfo();
139 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
140 E = Target.inst_end(); II != E; ++II) {
141 std::vector<std::string> OperandInfo = GetOperandInfo(**II);
142 unsigned &N = OperandInfoIDs[OperandInfo];
143 if (N != 0) continue;
145 N = ++OperandListNum;
146 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
147 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
148 OS << "{ " << OperandInfo[i] << " }, ";
153 //===----------------------------------------------------------------------===//
155 //===----------------------------------------------------------------------===//
157 // run - Emit the main instruction description records for the target...
158 void InstrInfoEmitter::run(raw_ostream &OS) {
161 EmitSourceFileHeader("Target Instruction Descriptors", OS);
162 OS << "namespace llvm {\n\n";
164 CodeGenTarget &Target = CDP.getTargetInfo();
165 const std::string &TargetName = Target.getName();
166 Record *InstrInfo = Target.getInstructionSet();
168 // Keep track of all of the def lists we have emitted already.
169 std::map<std::vector<Record*>, unsigned> EmittedLists;
170 unsigned ListNumber = 0;
172 // Emit all of the instruction's implicit uses and defs.
173 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
174 E = Target.inst_end(); II != E; ++II) {
175 Record *Inst = (*II)->TheDef;
176 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
178 unsigned &IL = EmittedLists[Uses];
179 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
181 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
183 unsigned &IL = EmittedLists[Defs];
184 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
188 OperandInfoMapTy OperandInfoIDs;
190 // Emit all of the operand info records.
191 EmitOperandInfo(OS, OperandInfoIDs);
193 // Emit all of the TargetInstrDesc records in their ENUM ordering.
195 OS << "\nstatic const TargetInstrDesc " << TargetName
197 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
198 Target.getInstructionsByEnumValue();
200 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
201 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
204 OS << "} // End llvm namespace \n";
207 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
209 std::map<std::vector<Record*>, unsigned> &EmittedLists,
210 const OperandInfoMapTy &OpInfo,
213 if (!Inst.Operands.size() == 0)
214 // Each logical operand can be multiple MI operands.
215 MinOperands = Inst.Operands.back().MIOperandNo +
216 Inst.Operands.back().MINumOperands;
219 OS << Num << ",\t" << MinOperands << ",\t"
220 << Inst.Operands.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
221 << ",\t\"" << Inst.TheDef->getName() << "\", 0";
223 // Emit all of the target indepedent flags...
224 if (Inst.isReturn) OS << "|(1<<TID::Return)";
225 if (Inst.isBranch) OS << "|(1<<TID::Branch)";
226 if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
227 if (Inst.isCompare) OS << "|(1<<TID::Compare)";
228 if (Inst.isMoveImm) OS << "|(1<<TID::MoveImm)";
229 if (Inst.isBitcast) OS << "|(1<<TID::Bitcast)";
230 if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
231 if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
232 if (Inst.isCall) OS << "|(1<<TID::Call)";
233 if (Inst.canFoldAsLoad) OS << "|(1<<TID::FoldableAsLoad)";
234 if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)";
235 if (Inst.mayStore) OS << "|(1<<TID::MayStore)";
236 if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
237 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
238 if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
239 if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
240 if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
241 if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)";
242 if (Inst.Operands.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)";
243 if (Inst.usesCustomInserter) OS << "|(1<<TID::UsesCustomInserter)";
244 if (Inst.Operands.isVariadic)OS << "|(1<<TID::Variadic)";
245 if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)";
246 if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)";
247 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<TID::ExtraSrcRegAllocReq)";
248 if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<TID::ExtraDefRegAllocReq)";
250 // Emit all of the target-specific flags...
251 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
252 if (!TSF) throw "no TSFlags?";
254 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
255 if (BitInit *Bit = dynamic_cast<BitInit*>(TSF->getBit(i)))
256 Value |= uint64_t(Bit->getValue()) << i;
258 throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
264 // Emit the implicit uses and defs lists...
265 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
269 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
271 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
275 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
277 // Emit the operand info.
278 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
279 if (OperandInfo.empty())
282 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
284 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";