1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
20 // runEnums - Print out enum values for all of the instructions.
21 void InstrInfoEmitter::runEnums(std::ostream &OS) {
22 EmitSourceFileHeader("Target Instruction Enum Values", OS);
23 OS << "namespace llvm {\n\n";
27 // We must emit the PHI opcode first...
28 Record *InstrInfo = Target.getInstructionSet();
29 Record *PHI = InstrInfo->getValueAsDef("PHIInst");
31 std::string Namespace = Target.inst_begin()->second.Namespace;
33 if (!Namespace.empty())
34 OS << "namespace " << Namespace << " {\n";
37 OS << " " << PHI->getName() << ", \t// 0 (fixed for all targets)\n";
39 // Print out the rest of the instructions now.
41 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
42 E = Target.inst_end(); II != E; ++II)
43 if (II->second.TheDef != PHI)
44 OS << " " << II->first << ", \t// " << ++i << "\n";
47 if (!Namespace.empty())
49 OS << "} // End llvm namespace \n";
52 void InstrInfoEmitter::printDefList(ListInit *LI, const std::string &Name,
53 std::ostream &OS) const {
54 OS << "static const unsigned " << Name << "[] = { ";
55 for (unsigned j = 0, e = LI->getSize(); j != e; ++j)
56 if (DefInit *DI = dynamic_cast<DefInit*>(LI->getElement(j)))
57 OS << getQualifiedName(DI->getDef()) << ", ";
59 throw "Illegal value in '" + Name + "' list!";
64 // run - Emit the main instruction description records for the target...
65 void InstrInfoEmitter::run(std::ostream &OS) {
66 EmitSourceFileHeader("Target Instruction Descriptors", OS);
67 OS << "namespace llvm {\n\n";
70 const std::string &TargetName = Target.getName();
71 Record *InstrInfo = Target.getInstructionSet();
72 Record *PHI = InstrInfo->getValueAsDef("PHIInst");
74 // Emit empty implicit uses and defs lists
75 OS << "static const unsigned EmptyImpUses[] = { 0 };\n"
76 << "static const unsigned EmptyImpDefs[] = { 0 };\n";
78 // Emit all of the instruction's implicit uses and defs...
79 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
80 E = Target.inst_end(); II != E; ++II) {
81 Record *Inst = II->second.TheDef;
82 ListInit *LI = Inst->getValueAsListInit("Uses");
83 if (LI->getSize()) printDefList(LI, Inst->getName()+"ImpUses", OS);
84 LI = Inst->getValueAsListInit("Defs");
85 if (LI->getSize()) printDefList(LI, Inst->getName()+"ImpDefs", OS);
88 OS << "\nstatic const TargetInstrDescriptor " << TargetName
90 emitRecord(Target.getPHIInstruction(), 0, InstrInfo, OS);
93 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
94 E = Target.inst_end(); II != E; ++II)
95 if (II->second.TheDef != PHI)
96 emitRecord(II->second, ++i, InstrInfo, OS);
98 OS << "} // End llvm namespace \n";
101 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
102 Record *InstrInfo, std::ostream &OS) {
104 if (Inst.Name.empty())
105 OS << Inst.TheDef->getName();
108 OS << "\",\t-1, -1, 0, false, 0, 0, 0, 0";
110 // Emit all of the target indepedent flags...
111 if (Inst.isReturn) OS << "|M_RET_FLAG";
112 if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
113 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
114 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
115 if (Inst.isCall) OS << "|M_CALL_FLAG";
116 if (Inst.isLoad) OS << "|M_LOAD_FLAG";
117 if (Inst.isStore) OS << "|M_STORE_FLAG";
118 if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
119 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
122 // Emit all of the target-specific flags...
123 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
124 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
125 if (LI->getSize() != Shift->getSize())
126 throw "Lengths of " + InstrInfo->getName() +
127 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
129 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
130 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
131 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
135 // Emit the implicit uses and defs lists...
136 LI = Inst.TheDef->getValueAsListInit("Uses");
138 OS << "EmptyImpUses, ";
140 OS << Inst.TheDef->getName() << "ImpUses, ";
142 LI = Inst.TheDef->getValueAsListInit("Defs");
144 OS << "EmptyImpDefs ";
146 OS << Inst.TheDef->getName() << "ImpDefs ";
148 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
151 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
152 IntInit *ShiftInt, std::ostream &OS) {
153 if (Val == 0 || ShiftInt == 0)
154 throw std::string("Illegal value or shift amount in TargetInfo*!");
155 RecordVal *RV = R->getValue(Val->getValue());
156 int Shift = ShiftInt->getValue();
158 if (RV == 0 || RV->getValue() == 0)
159 throw R->getName() + " doesn't have a field named '" + Val->getValue()+"'!";
161 Init *Value = RV->getValue();
162 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
163 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
165 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
166 // Convert the Bits to an integer to print...
167 Init *I = BI->convertInitializerTo(new IntRecTy());
169 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
171 OS << "|(" << II->getValue() << "<<" << Shift << ")";
175 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
176 if (II->getValue()) OS << "|(" << II->getValue() << "<<" << Shift << ")";
180 std::cerr << "Unhandled initializer: " << *Val << "\n";
181 throw "In record '" + R->getName() + "' for TSFlag emission.";