1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
20 // runEnums - Print out enum values for all of the instructions.
21 void InstrInfoEmitter::runEnums(std::ostream &OS) {
22 EmitSourceFileHeader("Target Instruction Enum Values", OS);
23 OS << "namespace llvm {\n\n";
27 // We must emit the PHI opcode first...
28 Record *InstrInfo = Target.getInstructionSet();
30 std::string Namespace = Target.inst_begin()->second.Namespace;
32 if (!Namespace.empty())
33 OS << "namespace " << Namespace << " {\n";
36 std::vector<const CodeGenInstruction*> NumberedInstructions;
37 Target.getInstructionsByEnumValue(NumberedInstructions);
39 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
40 OS << " " << NumberedInstructions[i]->TheDef->getName()
41 << ", \t// " << i << "\n";
43 OS << " INSTRUCTION_LIST_END\n";
45 if (!Namespace.empty())
47 OS << "} // End llvm namespace \n";
50 static std::vector<Record*> GetDefList(ListInit *LI, const std::string &Name) {
51 std::vector<Record*> Result;
52 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
53 if (DefInit *DI = dynamic_cast<DefInit*>(LI->getElement(i)))
54 Result.push_back(DI->getDef());
56 throw "Illegal value in '" + Name + "' list!";
60 void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
61 unsigned Num, std::ostream &OS) const {
62 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
63 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
64 OS << getQualifiedName(Uses[i]) << ", ";
68 static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
69 std::vector<Record*> Result;
70 if (Inst.hasVariableNumberOfOperands)
71 return Result; // No info for variable operand instrs.
73 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
74 if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass"))
75 Result.push_back(Inst.OperandList[i].Rec);
77 // This might be a multiple operand thing.
78 // FIXME: Targets like X86 have registers in their multi-operand operands.
79 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j)
87 // run - Emit the main instruction description records for the target...
88 void InstrInfoEmitter::run(std::ostream &OS) {
89 EmitSourceFileHeader("Target Instruction Descriptors", OS);
90 OS << "namespace llvm {\n\n";
93 const std::string &TargetName = Target.getName();
94 Record *InstrInfo = Target.getInstructionSet();
95 Record *PHI = InstrInfo->getValueAsDef("PHIInst");
97 // Emit empty implicit uses and defs lists
98 OS << "static const unsigned EmptyImpList[] = { 0 };\n";
100 // Keep track of all of the def lists we have emitted already.
101 std::map<std::vector<Record*>, unsigned> EmittedLists;
102 std::map<ListInit*, unsigned> ListNumbers;
103 unsigned ListNumber = 0;
105 // Emit all of the instruction's implicit uses and defs.
106 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
107 E = Target.inst_end(); II != E; ++II) {
108 Record *Inst = II->second.TheDef;
109 ListInit *LI = Inst->getValueAsListInit("Uses");
111 std::vector<Record*> Uses = GetDefList(LI, Inst->getName());
112 unsigned &IL = EmittedLists[Uses];
113 if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
114 ListNumbers[LI] = IL;
116 LI = Inst->getValueAsListInit("Defs");
118 std::vector<Record*> Uses = GetDefList(LI, Inst->getName());
119 unsigned &IL = EmittedLists[Uses];
120 if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
121 ListNumbers[LI] = IL;
125 std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
126 unsigned OperandListNum = 0;
127 OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
129 // Emit all of the operand info records.
131 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
132 E = Target.inst_end(); II != E; ++II) {
133 std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
134 unsigned &N = OperandInfosEmitted[OperandInfo];
136 N = ++OperandListNum;
137 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
138 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
139 if (Record *RC = OperandInfo[i]) {
140 OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
149 // Emit all of the TargetInstrDescriptor records.
151 OS << "\nstatic const TargetInstrDescriptor " << TargetName
153 emitRecord(Target.getPHIInstruction(), 0, InstrInfo, ListNumbers,
154 OperandInfosEmitted, OS);
157 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
158 E = Target.inst_end(); II != E; ++II)
159 if (II->second.TheDef != PHI)
160 emitRecord(II->second, ++i, InstrInfo, ListNumbers,
161 OperandInfosEmitted, OS);
163 OS << "} // End llvm namespace \n";
166 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
168 std::map<ListInit*, unsigned> &ListNumbers,
169 std::map<std::vector<Record*>, unsigned> &OpInfo,
172 if (Inst.hasVariableNumberOfOperands)
174 else if (!Inst.OperandList.empty())
175 // Each logical operand can be multiple MI operands.
176 NumOperands = Inst.OperandList.back().MIOperandNo +
177 Inst.OperandList.back().MINumOperands;
182 if (Inst.Name.empty())
183 OS << Inst.TheDef->getName();
186 OS << "\",\t" << NumOperands << ", -1, 0, false, 0, 0, 0, 0";
188 // Emit all of the target indepedent flags...
189 if (Inst.isReturn) OS << "|M_RET_FLAG";
190 if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
191 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
192 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
193 if (Inst.isCall) OS << "|M_CALL_FLAG";
194 if (Inst.isLoad) OS << "|M_LOAD_FLAG";
195 if (Inst.isStore) OS << "|M_STORE_FLAG";
196 if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
197 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
198 if (Inst.isCommutable) OS << "|M_COMMUTABLE";
199 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
200 if (Inst.usesCustomDAGSChedInserter)
201 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
204 // Emit all of the target-specific flags...
205 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
206 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
207 if (LI->getSize() != Shift->getSize())
208 throw "Lengths of " + InstrInfo->getName() +
209 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
211 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
212 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
213 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
217 // Emit the implicit uses and defs lists...
218 LI = Inst.TheDef->getValueAsListInit("Uses");
220 OS << "EmptyImpList, ";
222 OS << "ImplicitList" << ListNumbers[LI] << ", ";
224 LI = Inst.TheDef->getValueAsListInit("Defs");
226 OS << "EmptyImpList, ";
228 OS << "ImplicitList" << ListNumbers[LI] << ", ";
230 // Emit the operand info.
231 std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
232 if (OperandInfo.empty())
235 OS << "OperandInfo" << OpInfo[OperandInfo];
237 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
240 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
241 IntInit *ShiftInt, std::ostream &OS) {
242 if (Val == 0 || ShiftInt == 0)
243 throw std::string("Illegal value or shift amount in TargetInfo*!");
244 RecordVal *RV = R->getValue(Val->getValue());
245 int Shift = ShiftInt->getValue();
247 if (RV == 0 || RV->getValue() == 0)
248 throw R->getName() + " doesn't have a field named '" + Val->getValue()+"'!";
250 Init *Value = RV->getValue();
251 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
252 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
254 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
255 // Convert the Bits to an integer to print...
256 Init *I = BI->convertInitializerTo(new IntRecTy());
258 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
260 OS << "|(" << II->getValue() << "<<" << Shift << ")";
264 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
265 if (II->getValue()) OS << "|(" << II->getValue() << "<<" << Shift << ")";
269 std::cerr << "Unhandled initializer: " << *Val << "\n";
270 throw "In record '" + R->getName() + "' for TSFlag emission.";