1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/Target/TargetInstrInfo.h"
22 // runEnums - Print out enum values for all of the instructions.
23 void InstrInfoEmitter::runEnums(std::ostream &OS) {
24 EmitSourceFileHeader("Target Instruction Enum Values", OS);
25 OS << "namespace llvm {\n\n";
29 // We must emit the PHI opcode first...
30 std::string Namespace;
31 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
32 E = Target.inst_end(); II != E; ++II) {
33 if (II->second.Namespace != "TargetInstrInfo") {
34 Namespace = II->second.Namespace;
39 if (Namespace.empty()) {
40 cerr << "No instructions defined!\n";
44 std::vector<const CodeGenInstruction*> NumberedInstructions;
45 Target.getInstructionsByEnumValue(NumberedInstructions);
47 OS << "namespace " << Namespace << " {\n";
49 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
50 OS << " " << NumberedInstructions[i]->TheDef->getName()
51 << "\t= " << i << ",\n";
53 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
55 OS << "} // End llvm namespace \n";
58 void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
59 unsigned Num, std::ostream &OS) const {
60 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
61 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
62 OS << getQualifiedName(Uses[i]) << ", ";
66 std::vector<std::string>
67 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
68 std::vector<std::string> Result;
70 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
71 // Handle aggregate operands and normal operands the same way by expanding
72 // either case into a list of operands for this op.
73 std::vector<CodeGenInstruction::OperandInfo> OperandList;
75 // This might be a multiple operand thing. Targets like X86 have
76 // registers in their multi-operand operands. It may also be an anonymous
77 // operand, which has a single operand, but no declared class for the
79 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
81 if (!MIOI || MIOI->getNumArgs() == 0) {
82 // Single, anonymous, operand.
83 OperandList.push_back(Inst.OperandList[i]);
85 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
86 OperandList.push_back(Inst.OperandList[i]);
88 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
89 OperandList.back().Rec = OpR;
93 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
94 Record *OpR = OperandList[j].Rec;
97 if (OpR->isSubClassOf("RegisterClass"))
98 Res += getQualifiedName(OpR) + "RegClassID, ";
101 // Fill in applicable flags.
104 // Ptr value whose register class is resolved via callback.
105 if (OpR->getName() == "ptr_rc")
106 Res += "|M_LOOK_UP_PTR_REG_CLASS";
108 // Predicate operands. Check to see if the original unexpanded operand
109 // was of type PredicateOperand.
110 if (j == 0 && Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
111 Res += "|M_PREDICATE_OPERAND";
113 // Fill in constraint info.
114 Res += ", " + Inst.OperandList[i].Constraints[j];
115 Result.push_back(Res);
123 // run - Emit the main instruction description records for the target...
124 void InstrInfoEmitter::run(std::ostream &OS) {
127 EmitSourceFileHeader("Target Instruction Descriptors", OS);
128 OS << "namespace llvm {\n\n";
130 CodeGenTarget Target;
131 const std::string &TargetName = Target.getName();
132 Record *InstrInfo = Target.getInstructionSet();
134 // Keep track of all of the def lists we have emitted already.
135 std::map<std::vector<Record*>, unsigned> EmittedLists;
136 unsigned ListNumber = 0;
138 // Emit all of the instruction's implicit uses and defs.
139 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
140 E = Target.inst_end(); II != E; ++II) {
141 Record *Inst = II->second.TheDef;
142 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
144 unsigned &IL = EmittedLists[Uses];
145 if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
147 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
149 unsigned &IL = EmittedLists[Defs];
150 if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
154 std::map<std::vector<std::string>, unsigned> OperandInfosEmitted;
155 unsigned OperandListNum = 0;
156 OperandInfosEmitted[std::vector<std::string>()] = ++OperandListNum;
158 // Emit all of the operand info records.
160 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
161 E = Target.inst_end(); II != E; ++II) {
162 std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
163 unsigned &N = OperandInfosEmitted[OperandInfo];
165 N = ++OperandListNum;
166 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
167 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
168 OS << "{ " << OperandInfo[i] << " }, ";
173 // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
175 OS << "\nstatic const TargetInstrDescriptor " << TargetName
177 std::vector<const CodeGenInstruction*> NumberedInstructions;
178 Target.getInstructionsByEnumValue(NumberedInstructions);
180 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
181 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
182 OperandInfosEmitted, OS);
184 OS << "} // End llvm namespace \n";
187 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
189 std::map<std::vector<Record*>, unsigned> &EmittedLists,
190 std::map<std::vector<std::string>, unsigned> &OpInfo,
193 if (!Inst.OperandList.empty())
194 // Each logical operand can be multiple MI operands.
195 MinOperands = Inst.OperandList.back().MIOperandNo +
196 Inst.OperandList.back().MINumOperands;
201 OS << Num << ",\t" << MinOperands << ",\t\"";
203 if (Inst.Name.empty())
204 OS << Inst.TheDef->getName();
208 unsigned ItinClass = !IsItineraries ? 0 :
209 ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
211 OS << "\",\t" << ItinClass << ", 0";
213 // Try to determine (from the pattern), if the instruction is a store.
214 bool isStore = false;
215 if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
216 ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
217 if (LI && LI->getSize() > 0) {
218 DagInit *Dag = (DagInit *)LI->getElement(0);
219 DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
221 Record *Operator = OpDef->getDef();
222 if (Operator->isSubClassOf("SDNode")) {
223 const std::string Opcode = Operator->getValueAsString("Opcode");
224 if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
231 // Emit all of the target indepedent flags...
232 if (Inst.isReturn) OS << "|M_RET_FLAG";
233 if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
234 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
235 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
236 if (Inst.isCall) OS << "|M_CALL_FLAG";
237 if (Inst.isLoad) OS << "|M_LOAD_FLAG";
238 if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
239 if (Inst.isPredicated) OS << "|M_PREDICATED";
240 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
241 if (Inst.isCommutable) OS << "|M_COMMUTABLE";
242 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
243 if (Inst.usesCustomDAGSchedInserter)
244 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
245 if (Inst.hasVariableNumberOfOperands)
246 OS << "|M_VARIABLE_OPS";
249 // Emit all of the target-specific flags...
250 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
251 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
252 if (LI->getSize() != Shift->getSize())
253 throw "Lengths of " + InstrInfo->getName() +
254 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
256 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
257 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
258 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
262 // Emit the implicit uses and defs lists...
263 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
267 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
269 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
273 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
275 // Emit the operand info.
276 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
277 if (OperandInfo.empty())
280 OS << "OperandInfo" << OpInfo[OperandInfo];
282 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
286 bool operator()(const Record *Rec1, const Record *Rec2) const {
287 return Rec1->getName() < Rec2->getName();
290 void InstrInfoEmitter::GatherItinClasses() {
291 std::vector<Record*> DefList =
292 Records.getAllDerivedDefinitions("InstrItinClass");
293 IsItineraries = !DefList.empty();
295 if (!IsItineraries) return;
297 std::sort(DefList.begin(), DefList.end(), LessRecord());
299 for (unsigned i = 0, N = DefList.size(); i < N; i++) {
300 Record *Def = DefList[i];
301 ItinClassMap[Def->getName()] = i;
305 unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
306 return ItinClassMap[ItinName];
309 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
310 IntInit *ShiftInt, std::ostream &OS) {
311 if (Val == 0 || ShiftInt == 0)
312 throw std::string("Illegal value or shift amount in TargetInfo*!");
313 RecordVal *RV = R->getValue(Val->getValue());
314 int Shift = ShiftInt->getValue();
316 if (RV == 0 || RV->getValue() == 0) {
317 // This isn't an error if this is a builtin instruction.
318 if (R->getName() != "PHI" &&
319 R->getName() != "INLINEASM" &&
320 R->getName() != "LABEL")
321 throw R->getName() + " doesn't have a field named '" +
322 Val->getValue() + "'!";
326 Init *Value = RV->getValue();
327 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
328 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
330 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
331 // Convert the Bits to an integer to print...
332 Init *I = BI->convertInitializerTo(new IntRecTy());
334 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
335 if (II->getValue()) {
337 OS << "|(" << II->getValue() << "<<" << Shift << ")";
339 OS << "|" << II->getValue();
344 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
345 if (II->getValue()) {
347 OS << "|(" << II->getValue() << "<<" << Shift << ")";
349 OS << II->getValue();
354 cerr << "Unhandled initializer: " << *Val << "\n";
355 throw "In record '" + R->getName() + "' for TSFlag emission.";