1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
17 #include "StringToOffsetTable.h"
18 #include "llvm/TableGen/Record.h"
19 #include "llvm/ADT/StringExtras.h"
24 static void PrintDefList(const std::vector<Record*> &Uses,
25 unsigned Num, raw_ostream &OS) {
26 OS << "static const uint16_t ImplicitList" << Num << "[] = { ";
27 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
28 OS << getQualifiedName(Uses[i]) << ", ";
32 //===----------------------------------------------------------------------===//
33 // Instruction Itinerary Information.
34 //===----------------------------------------------------------------------===//
36 void InstrInfoEmitter::GatherItinClasses() {
37 std::vector<Record*> DefList =
38 Records.getAllDerivedDefinitions("InstrItinClass");
39 std::sort(DefList.begin(), DefList.end(), LessRecord());
41 for (unsigned i = 0, N = DefList.size(); i < N; i++)
42 ItinClassMap[DefList[i]->getName()] = i;
45 unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
46 return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
49 //===----------------------------------------------------------------------===//
50 // Operand Info Emission.
51 //===----------------------------------------------------------------------===//
53 std::vector<std::string>
54 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
55 std::vector<std::string> Result;
57 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
58 // Handle aggregate operands and normal operands the same way by expanding
59 // either case into a list of operands for this op.
60 std::vector<CGIOperandList::OperandInfo> OperandList;
62 // This might be a multiple operand thing. Targets like X86 have
63 // registers in their multi-operand operands. It may also be an anonymous
64 // operand, which has a single operand, but no declared class for the
66 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
68 if (!MIOI || MIOI->getNumArgs() == 0) {
69 // Single, anonymous, operand.
70 OperandList.push_back(Inst.Operands[i]);
72 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
73 OperandList.push_back(Inst.Operands[i]);
75 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
76 OperandList.back().Rec = OpR;
80 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
81 Record *OpR = OperandList[j].Rec;
84 if (OpR->isSubClassOf("RegisterOperand"))
85 OpR = OpR->getValueAsDef("RegClass");
86 if (OpR->isSubClassOf("RegisterClass"))
87 Res += getQualifiedName(OpR) + "RegClassID, ";
88 else if (OpR->isSubClassOf("PointerLikeRegClass"))
89 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
91 // -1 means the operand does not have a fixed register class.
94 // Fill in applicable flags.
97 // Ptr value whose register class is resolved via callback.
98 if (OpR->isSubClassOf("PointerLikeRegClass"))
99 Res += "|(1<<MCOI::LookupPtrRegClass)";
101 // Predicate operands. Check to see if the original unexpanded operand
102 // was of type PredicateOperand.
103 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
104 Res += "|(1<<MCOI::Predicate)";
106 // Optional def operands. Check to see if the original unexpanded operand
107 // was of type OptionalDefOperand.
108 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
109 Res += "|(1<<MCOI::OptionalDef)";
111 // Fill in operand type.
113 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.");
114 Res += Inst.Operands[i].OperandType;
116 // Fill in constraint info.
119 const CGIOperandList::ConstraintInfo &Constraint =
120 Inst.Operands[i].Constraints[j];
121 if (Constraint.isNone())
123 else if (Constraint.isEarlyClobber())
124 Res += "(1 << MCOI::EARLY_CLOBBER)";
126 assert(Constraint.isTied());
127 Res += "((" + utostr(Constraint.getTiedOperand()) +
128 " << 16) | (1 << MCOI::TIED_TO))";
131 Result.push_back(Res);
138 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
139 OperandInfoMapTy &OperandInfoIDs) {
140 // ID #0 is for no operand info.
141 unsigned OperandListNum = 0;
142 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
145 const CodeGenTarget &Target = CDP.getTargetInfo();
146 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
147 E = Target.inst_end(); II != E; ++II) {
148 std::vector<std::string> OperandInfo = GetOperandInfo(**II);
149 unsigned &N = OperandInfoIDs[OperandInfo];
150 if (N != 0) continue;
152 N = ++OperandListNum;
153 OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
154 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
155 OS << "{ " << OperandInfo[i] << " }, ";
160 //===----------------------------------------------------------------------===//
162 //===----------------------------------------------------------------------===//
164 // run - Emit the main instruction description records for the target...
165 void InstrInfoEmitter::run(raw_ostream &OS) {
170 EmitSourceFileHeader("Target Instruction Descriptors", OS);
172 OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
173 OS << "#undef GET_INSTRINFO_MC_DESC\n";
175 OS << "namespace llvm {\n\n";
177 CodeGenTarget &Target = CDP.getTargetInfo();
178 const std::string &TargetName = Target.getName();
179 Record *InstrInfo = Target.getInstructionSet();
181 // Keep track of all of the def lists we have emitted already.
182 std::map<std::vector<Record*>, unsigned> EmittedLists;
183 unsigned ListNumber = 0;
185 // Emit all of the instruction's implicit uses and defs.
186 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
187 E = Target.inst_end(); II != E; ++II) {
188 Record *Inst = (*II)->TheDef;
189 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
191 unsigned &IL = EmittedLists[Uses];
192 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
194 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
196 unsigned &IL = EmittedLists[Defs];
197 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
201 OperandInfoMapTy OperandInfoIDs;
203 // Emit all of the operand info records.
204 EmitOperandInfo(OS, OperandInfoIDs);
206 // Emit all of the MCInstrDesc records in their ENUM ordering.
208 OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
209 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
210 Target.getInstructionsByEnumValue();
212 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
213 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
217 OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {\n ";
218 StringToOffsetTable StringTable;
219 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
220 const CodeGenInstruction *Instr = NumberedInstructions[i];
221 OS << StringTable.GetOrAddStringOffset(Instr->TheDef->getName()) << "U, ";
228 OS << "const char *" << TargetName << "InstrNameData =\n";
229 StringTable.EmitString(OS);
232 // MCInstrInfo initialization routine.
233 OS << "static inline void Init" << TargetName
234 << "MCInstrInfo(MCInstrInfo *II) {\n";
235 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, "
236 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
237 << NumberedInstructions.size() << ");\n}\n\n";
239 OS << "} // End llvm namespace \n";
241 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
243 // Create a TargetInstrInfo subclass to hide the MC layer initialization.
244 OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
245 OS << "#undef GET_INSTRINFO_HEADER\n";
247 std::string ClassName = TargetName + "GenInstrInfo";
248 OS << "namespace llvm {\n";
249 OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n"
250 << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
252 OS << "} // End llvm namespace \n";
254 OS << "#endif // GET_INSTRINFO_HEADER\n\n";
256 OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
257 OS << "#undef GET_INSTRINFO_CTOR\n";
259 OS << "namespace llvm {\n";
260 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
261 OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
262 OS << "extern const char *" << TargetName << "InstrNameData;\n";
263 OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
264 << " : TargetInstrInfoImpl(SO, DO) {\n"
265 << " InitMCInstrInfo(" << TargetName << "Insts, "
266 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
267 << NumberedInstructions.size() << ");\n}\n";
268 OS << "} // End llvm namespace \n";
270 OS << "#endif // GET_INSTRINFO_CTOR\n\n";
273 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
275 std::map<std::vector<Record*>, unsigned> &EmittedLists,
276 const OperandInfoMapTy &OpInfo,
279 if (!Inst.Operands.size() == 0)
280 // Each logical operand can be multiple MI operands.
281 MinOperands = Inst.Operands.back().MIOperandNo +
282 Inst.Operands.back().MINumOperands;
285 OS << Num << ",\t" << MinOperands << ",\t"
286 << Inst.Operands.NumDefs << ",\t"
287 << getItinClassNumber(Inst.TheDef) << ",\t"
288 << Inst.TheDef->getValueAsInt("Size") << ",\t0";
290 // Emit all of the target indepedent flags...
291 if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)";
292 if (Inst.isReturn) OS << "|(1<<MCID::Return)";
293 if (Inst.isBranch) OS << "|(1<<MCID::Branch)";
294 if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)";
295 if (Inst.isCompare) OS << "|(1<<MCID::Compare)";
296 if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)";
297 if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)";
298 if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)";
299 if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)";
300 if (Inst.isCall) OS << "|(1<<MCID::Call)";
301 if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)";
302 if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)";
303 if (Inst.mayStore) OS << "|(1<<MCID::MayStore)";
304 if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)";
305 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
306 if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)";
307 if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)";
308 if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
309 if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)";
310 if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
311 if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
312 if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)";
313 if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
314 if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)";
315 if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)";
316 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
317 if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
319 // Emit all of the target-specific flags...
320 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
321 if (!TSF) throw "no TSFlags?";
323 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
324 if (BitInit *Bit = dynamic_cast<BitInit*>(TSF->getBit(i)))
325 Value |= uint64_t(Bit->getValue()) << i;
327 throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
333 // Emit the implicit uses and defs lists...
334 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
338 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
340 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
344 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
346 // Emit the operand info.
347 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
348 if (OperandInfo.empty())
351 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
353 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
356 // emitEnums - Print out enum values for all of the instructions.
357 void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
358 EmitSourceFileHeader("Target Instruction Enum Values", OS);
360 OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
361 OS << "#undef GET_INSTRINFO_ENUM\n";
363 OS << "namespace llvm {\n\n";
365 CodeGenTarget Target(Records);
367 // We must emit the PHI opcode first...
368 std::string Namespace = Target.getInstNamespace();
370 if (Namespace.empty()) {
371 fprintf(stderr, "No instructions defined!\n");
375 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
376 Target.getInstructionsByEnumValue();
378 OS << "namespace " << Namespace << " {\n";
380 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
381 OS << " " << NumberedInstructions[i]->TheDef->getName()
382 << "\t= " << i << ",\n";
384 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
386 OS << "} // End llvm namespace \n";
388 OS << "#endif // GET_INSTRINFO_ENUM\n\n";