1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
21 // runEnums - Print out enum values for all of the instructions.
22 void InstrInfoEmitter::runEnums(std::ostream &OS) {
23 EmitSourceFileHeader("Target Instruction Enum Values", OS);
24 OS << "namespace llvm {\n\n";
28 // We must emit the PHI opcode first...
29 std::string Namespace;
30 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
31 E = Target.inst_end(); II != E; ++II) {
32 if (II->second.Namespace != "TargetInstrInfo") {
33 Namespace = II->second.Namespace;
38 if (Namespace.empty()) {
39 std::cerr << "No instructions defined!\n";
43 std::vector<const CodeGenInstruction*> NumberedInstructions;
44 Target.getInstructionsByEnumValue(NumberedInstructions);
46 OS << "namespace " << Namespace << " {\n";
48 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
49 OS << " " << NumberedInstructions[i]->TheDef->getName()
50 << "\t= " << i << ",\n";
52 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
54 OS << "} // End llvm namespace \n";
57 void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
58 unsigned Num, std::ostream &OS) const {
59 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
60 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
61 OS << getQualifiedName(Uses[i]) << ", ";
65 static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
66 std::vector<Record*> Result;
67 if (Inst.hasVariableNumberOfOperands)
68 return Result; // No info for variable operand instrs.
70 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
71 if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
72 Result.push_back(Inst.OperandList[i].Rec);
74 // This might be a multiple operand thing.
75 // Targets like X86 have registers in their multi-operand operands.
76 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
77 unsigned NumDefs = MIOI->getNumArgs();
78 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
82 DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
83 Result.push_back(Def ? Def->getDef() : 0);
92 // run - Emit the main instruction description records for the target...
93 void InstrInfoEmitter::run(std::ostream &OS) {
96 EmitSourceFileHeader("Target Instruction Descriptors", OS);
97 OS << "namespace llvm {\n\n";
100 const std::string &TargetName = Target.getName();
101 Record *InstrInfo = Target.getInstructionSet();
103 // Emit empty implicit uses and defs lists
104 OS << "static const unsigned EmptyImpList[] = { 0 };\n";
106 // Keep track of all of the def lists we have emitted already.
107 std::map<std::vector<Record*>, unsigned> EmittedLists;
108 unsigned ListNumber = 0;
110 // Emit all of the instruction's implicit uses and defs.
111 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
112 E = Target.inst_end(); II != E; ++II) {
113 Record *Inst = II->second.TheDef;
114 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
116 unsigned &IL = EmittedLists[Uses];
117 if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
119 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
121 unsigned &IL = EmittedLists[Defs];
122 if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
126 std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
127 unsigned OperandListNum = 0;
128 OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
130 // Emit all of the operand info records.
132 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
133 E = Target.inst_end(); II != E; ++II) {
134 std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
135 unsigned &N = OperandInfosEmitted[OperandInfo];
137 N = ++OperandListNum;
138 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
139 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
140 Record *RC = OperandInfo[i];
141 // FIXME: We only care about register operands for now.
142 if (RC && RC->isSubClassOf("RegisterClass")) {
143 OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
152 // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
154 OS << "\nstatic const TargetInstrDescriptor " << TargetName
156 std::vector<const CodeGenInstruction*> NumberedInstructions;
157 Target.getInstructionsByEnumValue(NumberedInstructions);
159 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
160 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
161 OperandInfosEmitted, OS);
163 OS << "} // End llvm namespace \n";
166 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
168 std::map<std::vector<Record*>, unsigned> &EmittedLists,
169 std::map<std::vector<Record*>, unsigned> &OpInfo,
172 if (Inst.hasVariableNumberOfOperands)
174 else if (!Inst.OperandList.empty())
175 // Each logical operand can be multiple MI operands.
176 NumOperands = Inst.OperandList.back().MIOperandNo +
177 Inst.OperandList.back().MINumOperands;
182 if (Inst.Name.empty())
183 OS << Inst.TheDef->getName();
187 unsigned ItinClass = !IsItineraries ? 0 :
188 ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
190 OS << "\",\t" << NumOperands << ", " << ItinClass
193 // Try to determine (from the pattern), if the instruction is a store.
194 bool isStore = false;
195 if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
196 ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
197 if (LI && LI->getSize() > 0) {
198 DagInit *Dag = (DagInit *)LI->getElement(0);
199 DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
201 Record *Operator = OpDef->getDef();
202 if (Operator->isSubClassOf("SDNode")) {
203 const std::string Opcode = Operator->getValueAsString("Opcode");
204 if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
211 // Emit all of the target indepedent flags...
212 if (Inst.isReturn) OS << "|M_RET_FLAG";
213 if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
214 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
215 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
216 if (Inst.isCall) OS << "|M_CALL_FLAG";
217 if (Inst.isLoad) OS << "|M_LOAD_FLAG";
218 if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
219 if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
220 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
221 if (Inst.isCommutable) OS << "|M_COMMUTABLE";
222 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
223 if (Inst.usesCustomDAGSchedInserter)
224 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
227 // Emit all of the target-specific flags...
228 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
229 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
230 if (LI->getSize() != Shift->getSize())
231 throw "Lengths of " + InstrInfo->getName() +
232 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
234 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
235 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
236 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
240 // Emit the implicit uses and defs lists...
241 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
243 OS << "EmptyImpList, ";
245 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
247 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
249 OS << "EmptyImpList, ";
251 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
253 // Emit the operand info.
254 std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
255 if (OperandInfo.empty())
258 OS << "OperandInfo" << OpInfo[OperandInfo];
260 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
264 bool operator()(const Record *Rec1, const Record *Rec2) const {
265 return Rec1->getName() < Rec2->getName();
268 void InstrInfoEmitter::GatherItinClasses() {
269 std::vector<Record*> DefList =
270 Records.getAllDerivedDefinitions("InstrItinClass");
271 IsItineraries = !DefList.empty();
273 if (!IsItineraries) return;
275 std::sort(DefList.begin(), DefList.end(), LessRecord());
277 for (unsigned i = 0, N = DefList.size(); i < N; i++) {
278 Record *Def = DefList[i];
279 ItinClassMap[Def->getName()] = i;
283 unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
284 return ItinClassMap[ItinName];
287 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
288 IntInit *ShiftInt, std::ostream &OS) {
289 if (Val == 0 || ShiftInt == 0)
290 throw std::string("Illegal value or shift amount in TargetInfo*!");
291 RecordVal *RV = R->getValue(Val->getValue());
292 int Shift = ShiftInt->getValue();
294 if (RV == 0 || RV->getValue() == 0) {
295 // This isn't an error if this is a builtin instruction.
296 if (R->getName() != "PHI" && R->getName() != "INLINEASM")
297 throw R->getName() + " doesn't have a field named '" +
298 Val->getValue() + "'!";
302 Init *Value = RV->getValue();
303 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
304 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
306 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
307 // Convert the Bits to an integer to print...
308 Init *I = BI->convertInitializerTo(new IntRecTy());
310 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
311 if (II->getValue()) {
313 OS << "|(" << II->getValue() << "<<" << Shift << ")";
315 OS << "|" << II->getValue();
320 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
321 if (II->getValue()) {
323 OS << "|(" << II->getValue() << "<<" << Shift << ")";
325 OS << II->getValue();
330 std::cerr << "Unhandled initializer: " << *Val << "\n";
331 throw "In record '" + R->getName() + "' for TSFlag emission.";