1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
16 #include "CodeGenDAGPatterns.h"
17 #include "CodeGenSchedule.h"
18 #include "CodeGenTarget.h"
19 #include "SequenceToOffsetTable.h"
20 #include "TableGenBackends.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/TableGen/Error.h"
23 #include "llvm/TableGen/Record.h"
24 #include "llvm/TableGen/TableGenBackend.h"
32 class InstrInfoEmitter {
33 RecordKeeper &Records;
34 CodeGenDAGPatterns CDP;
35 const CodeGenSchedModels &SchedModels;
38 InstrInfoEmitter(RecordKeeper &R):
39 Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
41 // run - Output the instruction set description.
42 void run(raw_ostream &OS);
45 void emitEnums(raw_ostream &OS);
47 typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
48 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
50 std::map<std::vector<Record*>, unsigned> &EL,
51 const OperandInfoMapTy &OpInfo,
54 // Operand information.
55 void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
56 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
58 } // End anonymous namespace
60 static void PrintDefList(const std::vector<Record*> &Uses,
61 unsigned Num, raw_ostream &OS) {
62 OS << "static const uint16_t ImplicitList" << Num << "[] = { ";
63 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
64 OS << getQualifiedName(Uses[i]) << ", ";
68 //===----------------------------------------------------------------------===//
69 // Operand Info Emission.
70 //===----------------------------------------------------------------------===//
72 std::vector<std::string>
73 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
74 std::vector<std::string> Result;
76 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
77 // Handle aggregate operands and normal operands the same way by expanding
78 // either case into a list of operands for this op.
79 std::vector<CGIOperandList::OperandInfo> OperandList;
81 // This might be a multiple operand thing. Targets like X86 have
82 // registers in their multi-operand operands. It may also be an anonymous
83 // operand, which has a single operand, but no declared class for the
85 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
87 if (!MIOI || MIOI->getNumArgs() == 0) {
88 // Single, anonymous, operand.
89 OperandList.push_back(Inst.Operands[i]);
91 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
92 OperandList.push_back(Inst.Operands[i]);
94 Record *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
95 OperandList.back().Rec = OpR;
99 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
100 Record *OpR = OperandList[j].Rec;
103 if (OpR->isSubClassOf("RegisterOperand"))
104 OpR = OpR->getValueAsDef("RegClass");
105 if (OpR->isSubClassOf("RegisterClass"))
106 Res += getQualifiedName(OpR) + "RegClassID, ";
107 else if (OpR->isSubClassOf("PointerLikeRegClass"))
108 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
110 // -1 means the operand does not have a fixed register class.
113 // Fill in applicable flags.
116 // Ptr value whose register class is resolved via callback.
117 if (OpR->isSubClassOf("PointerLikeRegClass"))
118 Res += "|(1<<MCOI::LookupPtrRegClass)";
120 // Predicate operands. Check to see if the original unexpanded operand
121 // was of type PredicateOperand.
122 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
123 Res += "|(1<<MCOI::Predicate)";
125 // Optional def operands. Check to see if the original unexpanded operand
126 // was of type OptionalDefOperand.
127 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
128 Res += "|(1<<MCOI::OptionalDef)";
130 // Fill in operand type.
132 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.");
133 Res += Inst.Operands[i].OperandType;
135 // Fill in constraint info.
138 const CGIOperandList::ConstraintInfo &Constraint =
139 Inst.Operands[i].Constraints[j];
140 if (Constraint.isNone())
142 else if (Constraint.isEarlyClobber())
143 Res += "(1 << MCOI::EARLY_CLOBBER)";
145 assert(Constraint.isTied());
146 Res += "((" + utostr(Constraint.getTiedOperand()) +
147 " << 16) | (1 << MCOI::TIED_TO))";
150 Result.push_back(Res);
157 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
158 OperandInfoMapTy &OperandInfoIDs) {
159 // ID #0 is for no operand info.
160 unsigned OperandListNum = 0;
161 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
164 const CodeGenTarget &Target = CDP.getTargetInfo();
165 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
166 E = Target.inst_end(); II != E; ++II) {
167 std::vector<std::string> OperandInfo = GetOperandInfo(**II);
168 unsigned &N = OperandInfoIDs[OperandInfo];
169 if (N != 0) continue;
171 N = ++OperandListNum;
172 OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
173 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
174 OS << "{ " << OperandInfo[i] << " }, ";
179 //===----------------------------------------------------------------------===//
181 //===----------------------------------------------------------------------===//
183 // run - Emit the main instruction description records for the target...
184 void InstrInfoEmitter::run(raw_ostream &OS) {
185 emitSourceFileHeader("Target Instruction Enum Values", OS);
188 emitSourceFileHeader("Target Instruction Descriptors", OS);
190 OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
191 OS << "#undef GET_INSTRINFO_MC_DESC\n";
193 OS << "namespace llvm {\n\n";
195 CodeGenTarget &Target = CDP.getTargetInfo();
196 const std::string &TargetName = Target.getName();
197 Record *InstrInfo = Target.getInstructionSet();
199 // Keep track of all of the def lists we have emitted already.
200 std::map<std::vector<Record*>, unsigned> EmittedLists;
201 unsigned ListNumber = 0;
203 // Emit all of the instruction's implicit uses and defs.
204 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
205 E = Target.inst_end(); II != E; ++II) {
206 Record *Inst = (*II)->TheDef;
207 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
209 unsigned &IL = EmittedLists[Uses];
210 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
212 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
214 unsigned &IL = EmittedLists[Defs];
215 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
219 OperandInfoMapTy OperandInfoIDs;
221 // Emit all of the operand info records.
222 EmitOperandInfo(OS, OperandInfoIDs);
224 // Emit all of the MCInstrDesc records in their ENUM ordering.
226 OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
227 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
228 Target.getInstructionsByEnumValue();
230 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
231 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
235 // Build an array of instruction names
236 SequenceToOffsetTable<std::string> InstrNames;
237 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
238 const CodeGenInstruction *Instr = NumberedInstructions[i];
239 InstrNames.add(Instr->TheDef->getName());
243 OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
244 InstrNames.emit(OS, printChar);
247 OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
248 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
251 const CodeGenInstruction *Instr = NumberedInstructions[i];
252 OS << InstrNames.get(Instr->TheDef->getName()) << "U, ";
257 // MCInstrInfo initialization routine.
258 OS << "static inline void Init" << TargetName
259 << "MCInstrInfo(MCInstrInfo *II) {\n";
260 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, "
261 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
262 << NumberedInstructions.size() << ");\n}\n\n";
264 OS << "} // End llvm namespace \n";
266 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
268 // Create a TargetInstrInfo subclass to hide the MC layer initialization.
269 OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
270 OS << "#undef GET_INSTRINFO_HEADER\n";
272 std::string ClassName = TargetName + "GenInstrInfo";
273 OS << "namespace llvm {\n";
274 OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
275 << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
277 OS << "} // End llvm namespace \n";
279 OS << "#endif // GET_INSTRINFO_HEADER\n\n";
281 OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
282 OS << "#undef GET_INSTRINFO_CTOR\n";
284 OS << "namespace llvm {\n";
285 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
286 OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
287 OS << "extern const char " << TargetName << "InstrNameData[];\n";
288 OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
289 << " : TargetInstrInfo(SO, DO) {\n"
290 << " InitMCInstrInfo(" << TargetName << "Insts, "
291 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
292 << NumberedInstructions.size() << ");\n}\n";
293 OS << "} // End llvm namespace \n";
295 OS << "#endif // GET_INSTRINFO_CTOR\n\n";
298 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
300 std::map<std::vector<Record*>, unsigned> &EmittedLists,
301 const OperandInfoMapTy &OpInfo,
304 if (!Inst.Operands.empty())
305 // Each logical operand can be multiple MI operands.
306 MinOperands = Inst.Operands.back().MIOperandNo +
307 Inst.Operands.back().MINumOperands;
310 OS << Num << ",\t" << MinOperands << ",\t"
311 << Inst.Operands.NumDefs << ",\t"
312 << SchedModels.getSchedClassIdx(Inst) << ",\t"
313 << Inst.TheDef->getValueAsInt("Size") << ",\t0";
315 // Emit all of the target indepedent flags...
316 if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)";
317 if (Inst.isReturn) OS << "|(1<<MCID::Return)";
318 if (Inst.isBranch) OS << "|(1<<MCID::Branch)";
319 if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)";
320 if (Inst.isCompare) OS << "|(1<<MCID::Compare)";
321 if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)";
322 if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)";
323 if (Inst.isSelect) OS << "|(1<<MCID::Select)";
324 if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)";
325 if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)";
326 if (Inst.isCall) OS << "|(1<<MCID::Call)";
327 if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)";
328 if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)";
329 if (Inst.mayStore) OS << "|(1<<MCID::MayStore)";
330 if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)";
331 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
332 if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)";
333 if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)";
334 if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
335 if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)";
336 if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
337 if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
338 if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)";
339 if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
340 if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)";
341 if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)";
342 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
343 if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
345 // Emit all of the target-specific flags...
346 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
348 PrintFatalError("no TSFlags?");
350 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
351 if (BitInit *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
352 Value |= uint64_t(Bit->getValue()) << i;
354 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName());
360 // Emit the implicit uses and defs lists...
361 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
365 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
367 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
371 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
373 // Emit the operand info.
374 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
375 if (OperandInfo.empty())
378 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
380 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
383 // emitEnums - Print out enum values for all of the instructions.
384 void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
386 OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
387 OS << "#undef GET_INSTRINFO_ENUM\n";
389 OS << "namespace llvm {\n\n";
391 CodeGenTarget Target(Records);
393 // We must emit the PHI opcode first...
394 std::string Namespace = Target.getInstNamespace();
396 if (Namespace.empty()) {
397 fprintf(stderr, "No instructions defined!\n");
401 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
402 Target.getInstructionsByEnumValue();
404 OS << "namespace " << Namespace << " {\n";
406 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
407 OS << " " << NumberedInstructions[i]->TheDef->getName()
408 << "\t= " << i << ",\n";
410 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
412 OS << "} // End llvm namespace \n";
414 OS << "#endif // GET_INSTRINFO_ENUM\n\n";
419 void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
420 InstrInfoEmitter(RK).run(OS);
421 EmitMapTable(RK, OS);
424 } // End llvm namespace