1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
16 #include "CodeGenDAGPatterns.h"
17 #include "CodeGenSchedule.h"
18 #include "CodeGenTarget.h"
19 #include "SequenceToOffsetTable.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/TableGen/Record.h"
22 #include "llvm/TableGen/TableGenBackend.h"
30 class InstrInfoEmitter {
31 RecordKeeper &Records;
32 CodeGenDAGPatterns CDP;
33 const CodeGenSchedModels &SchedModels;
36 InstrInfoEmitter(RecordKeeper &R):
37 Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
39 // run - Output the instruction set description.
40 void run(raw_ostream &OS);
43 void emitEnums(raw_ostream &OS);
45 typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
46 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
48 std::map<std::vector<Record*>, unsigned> &EL,
49 const OperandInfoMapTy &OpInfo,
52 // Operand information.
53 void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
54 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
56 } // End anonymous namespace
58 static void PrintDefList(const std::vector<Record*> &Uses,
59 unsigned Num, raw_ostream &OS) {
60 OS << "static const uint16_t ImplicitList" << Num << "[] = { ";
61 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
62 OS << getQualifiedName(Uses[i]) << ", ";
66 //===----------------------------------------------------------------------===//
67 // Operand Info Emission.
68 //===----------------------------------------------------------------------===//
70 std::vector<std::string>
71 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
72 std::vector<std::string> Result;
74 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
75 // Handle aggregate operands and normal operands the same way by expanding
76 // either case into a list of operands for this op.
77 std::vector<CGIOperandList::OperandInfo> OperandList;
79 // This might be a multiple operand thing. Targets like X86 have
80 // registers in their multi-operand operands. It may also be an anonymous
81 // operand, which has a single operand, but no declared class for the
83 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
85 if (!MIOI || MIOI->getNumArgs() == 0) {
86 // Single, anonymous, operand.
87 OperandList.push_back(Inst.Operands[i]);
89 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
90 OperandList.push_back(Inst.Operands[i]);
92 Record *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
93 OperandList.back().Rec = OpR;
97 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
98 Record *OpR = OperandList[j].Rec;
101 if (OpR->isSubClassOf("RegisterOperand"))
102 OpR = OpR->getValueAsDef("RegClass");
103 if (OpR->isSubClassOf("RegisterClass"))
104 Res += getQualifiedName(OpR) + "RegClassID, ";
105 else if (OpR->isSubClassOf("PointerLikeRegClass"))
106 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
108 // -1 means the operand does not have a fixed register class.
111 // Fill in applicable flags.
114 // Ptr value whose register class is resolved via callback.
115 if (OpR->isSubClassOf("PointerLikeRegClass"))
116 Res += "|(1<<MCOI::LookupPtrRegClass)";
118 // Predicate operands. Check to see if the original unexpanded operand
119 // was of type PredicateOperand.
120 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
121 Res += "|(1<<MCOI::Predicate)";
123 // Optional def operands. Check to see if the original unexpanded operand
124 // was of type OptionalDefOperand.
125 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
126 Res += "|(1<<MCOI::OptionalDef)";
128 // Fill in operand type.
130 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.");
131 Res += Inst.Operands[i].OperandType;
133 // Fill in constraint info.
136 const CGIOperandList::ConstraintInfo &Constraint =
137 Inst.Operands[i].Constraints[j];
138 if (Constraint.isNone())
140 else if (Constraint.isEarlyClobber())
141 Res += "(1 << MCOI::EARLY_CLOBBER)";
143 assert(Constraint.isTied());
144 Res += "((" + utostr(Constraint.getTiedOperand()) +
145 " << 16) | (1 << MCOI::TIED_TO))";
148 Result.push_back(Res);
155 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
156 OperandInfoMapTy &OperandInfoIDs) {
157 // ID #0 is for no operand info.
158 unsigned OperandListNum = 0;
159 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
162 const CodeGenTarget &Target = CDP.getTargetInfo();
163 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
164 E = Target.inst_end(); II != E; ++II) {
165 std::vector<std::string> OperandInfo = GetOperandInfo(**II);
166 unsigned &N = OperandInfoIDs[OperandInfo];
167 if (N != 0) continue;
169 N = ++OperandListNum;
170 OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
171 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
172 OS << "{ " << OperandInfo[i] << " }, ";
177 //===----------------------------------------------------------------------===//
179 //===----------------------------------------------------------------------===//
181 // run - Emit the main instruction description records for the target...
182 void InstrInfoEmitter::run(raw_ostream &OS) {
183 emitSourceFileHeader("Target Instruction Enum Values", OS);
186 emitSourceFileHeader("Target Instruction Descriptors", OS);
188 OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
189 OS << "#undef GET_INSTRINFO_MC_DESC\n";
191 OS << "namespace llvm {\n\n";
193 CodeGenTarget &Target = CDP.getTargetInfo();
194 const std::string &TargetName = Target.getName();
195 Record *InstrInfo = Target.getInstructionSet();
197 // Keep track of all of the def lists we have emitted already.
198 std::map<std::vector<Record*>, unsigned> EmittedLists;
199 unsigned ListNumber = 0;
201 // Emit all of the instruction's implicit uses and defs.
202 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
203 E = Target.inst_end(); II != E; ++II) {
204 Record *Inst = (*II)->TheDef;
205 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
207 unsigned &IL = EmittedLists[Uses];
208 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
210 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
212 unsigned &IL = EmittedLists[Defs];
213 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
217 OperandInfoMapTy OperandInfoIDs;
219 // Emit all of the operand info records.
220 EmitOperandInfo(OS, OperandInfoIDs);
222 // Emit all of the MCInstrDesc records in their ENUM ordering.
224 OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
225 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
226 Target.getInstructionsByEnumValue();
228 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
229 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
233 // Build an array of instruction names
234 SequenceToOffsetTable<std::string> InstrNames;
235 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
236 const CodeGenInstruction *Instr = NumberedInstructions[i];
237 InstrNames.add(Instr->TheDef->getName());
241 OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
242 InstrNames.emit(OS, printChar);
245 OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
246 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
249 const CodeGenInstruction *Instr = NumberedInstructions[i];
250 OS << InstrNames.get(Instr->TheDef->getName()) << "U, ";
255 // MCInstrInfo initialization routine.
256 OS << "static inline void Init" << TargetName
257 << "MCInstrInfo(MCInstrInfo *II) {\n";
258 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, "
259 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
260 << NumberedInstructions.size() << ");\n}\n\n";
262 OS << "} // End llvm namespace \n";
264 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
266 // Create a TargetInstrInfo subclass to hide the MC layer initialization.
267 OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
268 OS << "#undef GET_INSTRINFO_HEADER\n";
270 std::string ClassName = TargetName + "GenInstrInfo";
271 OS << "namespace llvm {\n";
272 OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n"
273 << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
275 OS << "} // End llvm namespace \n";
277 OS << "#endif // GET_INSTRINFO_HEADER\n\n";
279 OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
280 OS << "#undef GET_INSTRINFO_CTOR\n";
282 OS << "namespace llvm {\n";
283 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
284 OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
285 OS << "extern const char " << TargetName << "InstrNameData[];\n";
286 OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
287 << " : TargetInstrInfoImpl(SO, DO) {\n"
288 << " InitMCInstrInfo(" << TargetName << "Insts, "
289 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
290 << NumberedInstructions.size() << ");\n}\n";
291 OS << "} // End llvm namespace \n";
293 OS << "#endif // GET_INSTRINFO_CTOR\n\n";
296 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
298 std::map<std::vector<Record*>, unsigned> &EmittedLists,
299 const OperandInfoMapTy &OpInfo,
302 if (!Inst.Operands.empty())
303 // Each logical operand can be multiple MI operands.
304 MinOperands = Inst.Operands.back().MIOperandNo +
305 Inst.Operands.back().MINumOperands;
308 OS << Num << ",\t" << MinOperands << ",\t"
309 << Inst.Operands.NumDefs << ",\t"
310 << SchedModels.getSchedClassIdx(Inst) << ",\t"
311 << Inst.TheDef->getValueAsInt("Size") << ",\t0";
313 // Emit all of the target indepedent flags...
314 if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)";
315 if (Inst.isReturn) OS << "|(1<<MCID::Return)";
316 if (Inst.isBranch) OS << "|(1<<MCID::Branch)";
317 if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)";
318 if (Inst.isCompare) OS << "|(1<<MCID::Compare)";
319 if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)";
320 if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)";
321 if (Inst.isSelect) OS << "|(1<<MCID::Select)";
322 if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)";
323 if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)";
324 if (Inst.isCall) OS << "|(1<<MCID::Call)";
325 if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)";
326 if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)";
327 if (Inst.mayStore) OS << "|(1<<MCID::MayStore)";
328 if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)";
329 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
330 if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)";
331 if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)";
332 if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
333 if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)";
334 if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
335 if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
336 if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)";
337 if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
338 if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)";
339 if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)";
340 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
341 if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
343 // Emit all of the target-specific flags...
344 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
345 if (!TSF) throw "no TSFlags?";
347 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
348 if (BitInit *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
349 Value |= uint64_t(Bit->getValue()) << i;
351 throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
357 // Emit the implicit uses and defs lists...
358 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
362 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
364 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
368 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
370 // Emit the operand info.
371 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
372 if (OperandInfo.empty())
375 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
377 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
380 // emitEnums - Print out enum values for all of the instructions.
381 void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
383 OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
384 OS << "#undef GET_INSTRINFO_ENUM\n";
386 OS << "namespace llvm {\n\n";
388 CodeGenTarget Target(Records);
390 // We must emit the PHI opcode first...
391 std::string Namespace = Target.getInstNamespace();
393 if (Namespace.empty()) {
394 fprintf(stderr, "No instructions defined!\n");
398 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
399 Target.getInstructionsByEnumValue();
401 OS << "namespace " << Namespace << " {\n";
403 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
404 OS << " " << NumberedInstructions[i]->TheDef->getName()
405 << "\t= " << i << ",\n";
407 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
409 OS << "} // End llvm namespace \n";
411 OS << "#endif // GET_INSTRINFO_ENUM\n\n";
416 void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
417 InstrInfoEmitter(RK).run(OS);
420 } // End llvm namespace