1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
22 static void PrintDefList(const std::vector<Record*> &Uses,
23 unsigned Num, std::ostream &OS) {
24 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
25 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
26 OS << getQualifiedName(Uses[i]) << ", ";
30 //===----------------------------------------------------------------------===//
31 // Instruction Itinerary Information.
32 //===----------------------------------------------------------------------===//
34 struct RecordNameComparator {
35 bool operator()(const Record *Rec1, const Record *Rec2) const {
36 return Rec1->getName() < Rec2->getName();
40 void InstrInfoEmitter::GatherItinClasses() {
41 std::vector<Record*> DefList =
42 Records.getAllDerivedDefinitions("InstrItinClass");
43 std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
45 for (unsigned i = 0, N = DefList.size(); i < N; i++)
46 ItinClassMap[DefList[i]->getName()] = i;
49 unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
50 return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
53 //===----------------------------------------------------------------------===//
54 // Operand Info Emission.
55 //===----------------------------------------------------------------------===//
57 std::vector<std::string>
58 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
59 std::vector<std::string> Result;
61 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
62 // Handle aggregate operands and normal operands the same way by expanding
63 // either case into a list of operands for this op.
64 std::vector<CodeGenInstruction::OperandInfo> OperandList;
66 // This might be a multiple operand thing. Targets like X86 have
67 // registers in their multi-operand operands. It may also be an anonymous
68 // operand, which has a single operand, but no declared class for the
70 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
72 if (!MIOI || MIOI->getNumArgs() == 0) {
73 // Single, anonymous, operand.
74 OperandList.push_back(Inst.OperandList[i]);
76 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
77 OperandList.push_back(Inst.OperandList[i]);
79 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
80 OperandList.back().Rec = OpR;
84 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
85 Record *OpR = OperandList[j].Rec;
88 if (OpR->isSubClassOf("RegisterClass"))
89 Res += getQualifiedName(OpR) + "RegClassID, ";
92 // Fill in applicable flags.
95 // Ptr value whose register class is resolved via callback.
96 if (OpR->getName() == "ptr_rc")
97 Res += "|(1<<TOI::LookupPtrRegClass)";
99 // Predicate operands. Check to see if the original unexpanded operand
100 // was of type PredicateOperand.
101 if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
102 Res += "|(1<<TOI::Predicate)";
104 // Optional def operands. Check to see if the original unexpanded operand
105 // was of type OptionalDefOperand.
106 if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
107 Res += "|(1<<TOI::OptionalDef)";
109 // Fill in constraint info.
110 Res += ", " + Inst.OperandList[i].Constraints[j];
111 Result.push_back(Res);
118 void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
119 OperandInfoMapTy &OperandInfoIDs) {
120 // ID #0 is for no operand info.
121 unsigned OperandListNum = 0;
122 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
125 const CodeGenTarget &Target = CDP.getTargetInfo();
126 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
127 E = Target.inst_end(); II != E; ++II) {
128 std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
129 unsigned &N = OperandInfoIDs[OperandInfo];
130 if (N != 0) continue;
132 N = ++OperandListNum;
133 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
134 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
135 OS << "{ " << OperandInfo[i] << " }, ";
140 //===----------------------------------------------------------------------===//
142 //===----------------------------------------------------------------------===//
144 // run - Emit the main instruction description records for the target...
145 void InstrInfoEmitter::run(std::ostream &OS) {
148 EmitSourceFileHeader("Target Instruction Descriptors", OS);
149 OS << "namespace llvm {\n\n";
151 CodeGenTarget &Target = CDP.getTargetInfo();
152 const std::string &TargetName = Target.getName();
153 Record *InstrInfo = Target.getInstructionSet();
155 // Keep track of all of the def lists we have emitted already.
156 std::map<std::vector<Record*>, unsigned> EmittedLists;
157 unsigned ListNumber = 0;
159 // Emit all of the instruction's implicit uses and defs.
160 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
161 E = Target.inst_end(); II != E; ++II) {
162 Record *Inst = II->second.TheDef;
163 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
165 unsigned &IL = EmittedLists[Uses];
166 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
168 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
170 unsigned &IL = EmittedLists[Defs];
171 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
175 OperandInfoMapTy OperandInfoIDs;
177 // Emit all of the operand info records.
178 EmitOperandInfo(OS, OperandInfoIDs);
180 // Emit all of the TargetInstrDesc records in their ENUM ordering.
182 OS << "\nstatic const TargetInstrDesc " << TargetName
184 std::vector<const CodeGenInstruction*> NumberedInstructions;
185 Target.getInstructionsByEnumValue(NumberedInstructions);
187 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
188 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
191 OS << "} // End llvm namespace \n";
194 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
196 std::map<std::vector<Record*>, unsigned> &EmittedLists,
197 const OperandInfoMapTy &OpInfo,
200 if (!Inst.OperandList.empty())
201 // Each logical operand can be multiple MI operands.
202 MinOperands = Inst.OperandList.back().MIOperandNo +
203 Inst.OperandList.back().MINumOperands;
206 OS << Num << ",\t" << MinOperands << ",\t"
207 << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
208 << ",\t\"" << Inst.TheDef->getName() << "\", 0";
210 // Emit all of the target indepedent flags...
211 if (Inst.isReturn) OS << "|(1<<TID::Return)";
212 if (Inst.isBranch) OS << "|(1<<TID::Branch)";
213 if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
214 if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
215 if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
216 if (Inst.isCall) OS << "|(1<<TID::Call)";
217 if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
218 if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)";
219 if (Inst.mayStore) OS << "|(1<<TID::MayStore)";
220 if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
221 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
222 if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
223 if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
224 if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
225 if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)";
226 if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)";
227 if (Inst.usesCustomDAGSchedInserter)
228 OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
229 if (Inst.isVariadic) OS << "|(1<<TID::Variadic)";
230 if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)";
231 if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)";
234 // Emit all of the target-specific flags...
235 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
236 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
237 if (LI->getSize() != Shift->getSize())
238 throw "Lengths of " + InstrInfo->getName() +
239 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
241 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
242 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
243 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
247 // Emit the implicit uses and defs lists...
248 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
252 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
254 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
258 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
260 // Emit the operand info.
261 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
262 if (OperandInfo.empty())
265 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
267 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
271 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
272 IntInit *ShiftInt, std::ostream &OS) {
273 if (Val == 0 || ShiftInt == 0)
274 throw std::string("Illegal value or shift amount in TargetInfo*!");
275 RecordVal *RV = R->getValue(Val->getValue());
276 int Shift = ShiftInt->getValue();
278 if (RV == 0 || RV->getValue() == 0) {
279 // This isn't an error if this is a builtin instruction.
280 if (R->getName() != "PHI" &&
281 R->getName() != "INLINEASM" &&
282 R->getName() != "LABEL" &&
283 R->getName() != "DECLARE" &&
284 R->getName() != "EXTRACT_SUBREG" &&
285 R->getName() != "INSERT_SUBREG" &&
286 R->getName() != "IMPLICIT_DEF" &&
287 R->getName() != "SUBREG_TO_REG")
288 throw R->getName() + " doesn't have a field named '" +
289 Val->getValue() + "'!";
293 Init *Value = RV->getValue();
294 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
295 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
297 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
298 // Convert the Bits to an integer to print...
299 Init *I = BI->convertInitializerTo(new IntRecTy());
301 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
302 if (II->getValue()) {
304 OS << "|(" << II->getValue() << "<<" << Shift << ")";
306 OS << "|" << II->getValue();
311 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
312 if (II->getValue()) {
314 OS << "|(" << II->getValue() << "<<" << Shift << ")";
316 OS << II->getValue();
321 std::cerr << "Unhandled initializer: " << *Val << "\n";
322 throw "In record '" + R->getName() + "' for TSFlag emission.";