1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
17 #include "StringToOffsetTable.h"
18 #include "llvm/TableGen/Record.h"
19 #include "llvm/ADT/StringExtras.h"
23 static void PrintDefList(const std::vector<Record*> &Uses,
24 unsigned Num, raw_ostream &OS) {
25 OS << "static const uint16_t ImplicitList" << Num << "[] = { ";
26 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
27 OS << getQualifiedName(Uses[i]) << ", ";
31 //===----------------------------------------------------------------------===//
32 // Instruction Itinerary Information.
33 //===----------------------------------------------------------------------===//
35 void InstrInfoEmitter::GatherItinClasses() {
36 std::vector<Record*> DefList =
37 Records.getAllDerivedDefinitions("InstrItinClass");
38 std::sort(DefList.begin(), DefList.end(), LessRecord());
40 for (unsigned i = 0, N = DefList.size(); i < N; i++)
41 ItinClassMap[DefList[i]->getName()] = i;
44 unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
45 return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
48 //===----------------------------------------------------------------------===//
49 // Operand Info Emission.
50 //===----------------------------------------------------------------------===//
52 std::vector<std::string>
53 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
54 std::vector<std::string> Result;
56 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
57 // Handle aggregate operands and normal operands the same way by expanding
58 // either case into a list of operands for this op.
59 std::vector<CGIOperandList::OperandInfo> OperandList;
61 // This might be a multiple operand thing. Targets like X86 have
62 // registers in their multi-operand operands. It may also be an anonymous
63 // operand, which has a single operand, but no declared class for the
65 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
67 if (!MIOI || MIOI->getNumArgs() == 0) {
68 // Single, anonymous, operand.
69 OperandList.push_back(Inst.Operands[i]);
71 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
72 OperandList.push_back(Inst.Operands[i]);
74 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
75 OperandList.back().Rec = OpR;
79 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
80 Record *OpR = OperandList[j].Rec;
83 if (OpR->isSubClassOf("RegisterOperand"))
84 OpR = OpR->getValueAsDef("RegClass");
85 if (OpR->isSubClassOf("RegisterClass"))
86 Res += getQualifiedName(OpR) + "RegClassID, ";
87 else if (OpR->isSubClassOf("PointerLikeRegClass"))
88 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
90 // -1 means the operand does not have a fixed register class.
93 // Fill in applicable flags.
96 // Ptr value whose register class is resolved via callback.
97 if (OpR->isSubClassOf("PointerLikeRegClass"))
98 Res += "|(1<<MCOI::LookupPtrRegClass)";
100 // Predicate operands. Check to see if the original unexpanded operand
101 // was of type PredicateOperand.
102 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
103 Res += "|(1<<MCOI::Predicate)";
105 // Optional def operands. Check to see if the original unexpanded operand
106 // was of type OptionalDefOperand.
107 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
108 Res += "|(1<<MCOI::OptionalDef)";
110 // Fill in constraint info.
113 const CGIOperandList::ConstraintInfo &Constraint =
114 Inst.Operands[i].Constraints[j];
115 if (Constraint.isNone())
117 else if (Constraint.isEarlyClobber())
118 Res += "(1 << MCOI::EARLY_CLOBBER)";
120 assert(Constraint.isTied());
121 Res += "((" + utostr(Constraint.getTiedOperand()) +
122 " << 16) | (1 << MCOI::TIED_TO))";
125 // Fill in operand type.
127 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.");
128 Res += Inst.Operands[i].OperandType;
130 Result.push_back(Res);
137 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
138 OperandInfoMapTy &OperandInfoIDs) {
139 // ID #0 is for no operand info.
140 unsigned OperandListNum = 0;
141 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
144 const CodeGenTarget &Target = CDP.getTargetInfo();
145 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
146 E = Target.inst_end(); II != E; ++II) {
147 std::vector<std::string> OperandInfo = GetOperandInfo(**II);
148 unsigned &N = OperandInfoIDs[OperandInfo];
149 if (N != 0) continue;
151 N = ++OperandListNum;
152 OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
153 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
154 OS << "{ " << OperandInfo[i] << " }, ";
159 //===----------------------------------------------------------------------===//
161 //===----------------------------------------------------------------------===//
163 // run - Emit the main instruction description records for the target...
164 void InstrInfoEmitter::run(raw_ostream &OS) {
169 EmitSourceFileHeader("Target Instruction Descriptors", OS);
171 OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
172 OS << "#undef GET_INSTRINFO_MC_DESC\n";
174 OS << "namespace llvm {\n\n";
176 CodeGenTarget &Target = CDP.getTargetInfo();
177 const std::string &TargetName = Target.getName();
178 Record *InstrInfo = Target.getInstructionSet();
180 // Keep track of all of the def lists we have emitted already.
181 std::map<std::vector<Record*>, unsigned> EmittedLists;
182 unsigned ListNumber = 0;
184 // Emit all of the instruction's implicit uses and defs.
185 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
186 E = Target.inst_end(); II != E; ++II) {
187 Record *Inst = (*II)->TheDef;
188 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
190 unsigned &IL = EmittedLists[Uses];
191 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
193 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
195 unsigned &IL = EmittedLists[Defs];
196 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
200 OperandInfoMapTy OperandInfoIDs;
202 // Emit all of the operand info records.
203 EmitOperandInfo(OS, OperandInfoIDs);
205 // Emit all of the MCInstrDesc records in their ENUM ordering.
207 OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
208 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
209 Target.getInstructionsByEnumValue();
211 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
212 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
216 OS << "extern const uint16_t " << TargetName <<"InstrNameIndices[] = {\n ";
217 StringToOffsetTable StringTable;
218 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
219 const CodeGenInstruction *Instr = NumberedInstructions[i];
220 unsigned Idx = StringTable.GetOrAddStringOffset(Instr->TheDef->getName());
221 assert(Idx <= 0xffff && "String offset too large to fit in table");
229 OS << "extern const char *const " << TargetName << "InstrNameData =\n";
230 StringTable.EmitString(OS);
233 // MCInstrInfo initialization routine.
234 OS << "static inline void Init" << TargetName
235 << "MCInstrInfo(MCInstrInfo *II) {\n";
236 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, "
237 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
238 << NumberedInstructions.size() << ");\n}\n\n";
240 OS << "} // End llvm namespace \n";
242 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
244 // Create a TargetInstrInfo subclass to hide the MC layer initialization.
245 OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
246 OS << "#undef GET_INSTRINFO_HEADER\n";
248 std::string ClassName = TargetName + "GenInstrInfo";
249 OS << "namespace llvm {\n";
250 OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n"
251 << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
253 OS << "} // End llvm namespace \n";
255 OS << "#endif // GET_INSTRINFO_HEADER\n\n";
257 OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
258 OS << "#undef GET_INSTRINFO_CTOR\n";
260 OS << "namespace llvm {\n";
261 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
262 OS << "extern const uint16_t " << TargetName << "InstrNameIndices[];\n";
263 OS << "extern const char *const " << TargetName << "InstrNameData;\n";
264 OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
265 << " : TargetInstrInfoImpl(SO, DO) {\n"
266 << " InitMCInstrInfo(" << TargetName << "Insts, "
267 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
268 << NumberedInstructions.size() << ");\n}\n";
269 OS << "} // End llvm namespace \n";
271 OS << "#endif // GET_INSTRINFO_CTOR\n\n";
274 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
276 std::map<std::vector<Record*>, unsigned> &EmittedLists,
277 const OperandInfoMapTy &OpInfo,
280 if (!Inst.Operands.size() == 0)
281 // Each logical operand can be multiple MI operands.
282 MinOperands = Inst.Operands.back().MIOperandNo +
283 Inst.Operands.back().MINumOperands;
286 OS << Num << ",\t" << MinOperands << ",\t"
287 << Inst.Operands.NumDefs << ",\t"
288 << getItinClassNumber(Inst.TheDef) << ",\t"
289 << Inst.TheDef->getValueAsInt("Size") << ",\t0";
291 // Emit all of the target indepedent flags...
292 if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)";
293 if (Inst.isReturn) OS << "|(1<<MCID::Return)";
294 if (Inst.isBranch) OS << "|(1<<MCID::Branch)";
295 if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)";
296 if (Inst.isCompare) OS << "|(1<<MCID::Compare)";
297 if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)";
298 if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)";
299 if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)";
300 if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)";
301 if (Inst.isCall) OS << "|(1<<MCID::Call)";
302 if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)";
303 if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)";
304 if (Inst.mayStore) OS << "|(1<<MCID::MayStore)";
305 if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)";
306 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
307 if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)";
308 if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)";
309 if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
310 if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)";
311 if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
312 if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
313 if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)";
314 if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
315 if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)";
316 if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)";
317 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
318 if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
320 // Emit all of the target-specific flags...
321 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
322 if (!TSF) throw "no TSFlags?";
324 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
325 if (BitInit *Bit = dynamic_cast<BitInit*>(TSF->getBit(i)))
326 Value |= uint64_t(Bit->getValue()) << i;
328 throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
334 // Emit the implicit uses and defs lists...
335 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
339 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
341 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
345 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
347 // Emit the operand info.
348 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
349 if (OperandInfo.empty())
352 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
354 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
357 // emitEnums - Print out enum values for all of the instructions.
358 void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
359 EmitSourceFileHeader("Target Instruction Enum Values", OS);
361 OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
362 OS << "#undef GET_INSTRINFO_ENUM\n";
364 OS << "namespace llvm {\n\n";
366 CodeGenTarget Target(Records);
368 // We must emit the PHI opcode first...
369 std::string Namespace = Target.getInstNamespace();
371 if (Namespace.empty()) {
372 fprintf(stderr, "No instructions defined!\n");
376 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
377 Target.getInstructionsByEnumValue();
379 OS << "namespace " << Namespace << " {\n";
381 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
382 OS << " " << NumberedInstructions[i]->TheDef->getName()
383 << "\t= " << i << ",\n";
385 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
387 OS << "} // End llvm namespace \n";
389 OS << "#endif // GET_INSTRINFO_ENUM\n\n";