1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
22 void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
23 unsigned Num, std::ostream &OS) const {
24 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
25 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
26 OS << getQualifiedName(Uses[i]) << ", ";
30 std::vector<std::string>
31 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
32 std::vector<std::string> Result;
34 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
35 // Handle aggregate operands and normal operands the same way by expanding
36 // either case into a list of operands for this op.
37 std::vector<CodeGenInstruction::OperandInfo> OperandList;
39 // This might be a multiple operand thing. Targets like X86 have
40 // registers in their multi-operand operands. It may also be an anonymous
41 // operand, which has a single operand, but no declared class for the
43 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
45 if (!MIOI || MIOI->getNumArgs() == 0) {
46 // Single, anonymous, operand.
47 OperandList.push_back(Inst.OperandList[i]);
49 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
50 OperandList.push_back(Inst.OperandList[i]);
52 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
53 OperandList.back().Rec = OpR;
57 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
58 Record *OpR = OperandList[j].Rec;
61 if (OpR->isSubClassOf("RegisterClass"))
62 Res += getQualifiedName(OpR) + "RegClassID, ";
65 // Fill in applicable flags.
68 // Ptr value whose register class is resolved via callback.
69 if (OpR->getName() == "ptr_rc")
70 Res += "|M_LOOK_UP_PTR_REG_CLASS";
72 // Predicate operands. Check to see if the original unexpanded operand
73 // was of type PredicateOperand.
74 if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
75 Res += "|M_PREDICATE_OPERAND";
77 // Optional def operands. Check to see if the original unexpanded operand
78 // was of type OptionalDefOperand.
79 if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
80 Res += "|M_OPTIONAL_DEF_OPERAND";
82 // Fill in constraint info.
83 Res += ", " + Inst.OperandList[i].Constraints[j];
84 Result.push_back(Res);
92 // run - Emit the main instruction description records for the target...
93 void InstrInfoEmitter::run(std::ostream &OS) {
96 EmitSourceFileHeader("Target Instruction Descriptors", OS);
97 OS << "namespace llvm {\n\n";
100 const std::string &TargetName = Target.getName();
101 Record *InstrInfo = Target.getInstructionSet();
103 // Keep track of all of the def lists we have emitted already.
104 std::map<std::vector<Record*>, unsigned> EmittedLists;
105 unsigned ListNumber = 0;
107 // Emit all of the instruction's implicit uses and defs.
108 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
109 E = Target.inst_end(); II != E; ++II) {
110 Record *Inst = II->second.TheDef;
111 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
113 unsigned &IL = EmittedLists[Uses];
114 if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
116 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
118 unsigned &IL = EmittedLists[Defs];
119 if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
123 std::map<std::vector<std::string>, unsigned> OperandInfosEmitted;
124 unsigned OperandListNum = 0;
125 OperandInfosEmitted[std::vector<std::string>()] = ++OperandListNum;
127 // Emit all of the operand info records.
129 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
130 E = Target.inst_end(); II != E; ++II) {
131 std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
132 unsigned &N = OperandInfosEmitted[OperandInfo];
134 N = ++OperandListNum;
135 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
136 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
137 OS << "{ " << OperandInfo[i] << " }, ";
142 // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
144 OS << "\nstatic const TargetInstrDescriptor " << TargetName
146 std::vector<const CodeGenInstruction*> NumberedInstructions;
147 Target.getInstructionsByEnumValue(NumberedInstructions);
149 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
150 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
151 OperandInfosEmitted, OS);
153 OS << "} // End llvm namespace \n";
156 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
158 std::map<std::vector<Record*>, unsigned> &EmittedLists,
159 std::map<std::vector<std::string>, unsigned> &OpInfo,
162 if (!Inst.OperandList.empty())
163 // Each logical operand can be multiple MI operands.
164 MinOperands = Inst.OperandList.back().MIOperandNo +
165 Inst.OperandList.back().MINumOperands;
170 OS << Num << ",\t" << MinOperands << ",\t"
171 << Inst.NumDefs << ",\t\"";
173 if (Inst.Name.empty())
174 OS << Inst.TheDef->getName();
178 unsigned ItinClass = !IsItineraries ? 0 :
179 ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
181 OS << "\",\t" << ItinClass << ", 0";
183 // Try to determine (from the pattern), if the instruction is a store.
184 bool isStore = false;
185 if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
186 ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
187 if (LI && LI->getSize() > 0) {
188 DagInit *Dag = (DagInit *)LI->getElement(0);
189 DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
191 Record *Operator = OpDef->getDef();
192 if (Operator->isSubClassOf("SDNode")) {
193 const std::string Opcode = Operator->getValueAsString("Opcode");
194 if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
201 // Emit all of the target indepedent flags...
202 if (Inst.isReturn) OS << "|M_RET_FLAG";
203 if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
204 if (Inst.isIndirectBranch) OS << "|M_INDIRECT_FLAG";
205 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
206 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
207 if (Inst.isCall) OS << "|M_CALL_FLAG";
208 if (Inst.isLoad) OS << "|M_LOAD_FLAG";
209 if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
210 if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG";
211 if (Inst.isPredicable) OS << "|M_PREDICABLE";
212 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
213 if (Inst.isCommutable) OS << "|M_COMMUTABLE";
214 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
215 if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE";
216 if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE";
217 if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF";
218 if (Inst.usesCustomDAGSchedInserter)
219 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
220 if (Inst.hasVariableNumberOfOperands) OS << "|M_VARIABLE_OPS";
221 if (Inst.mayHaveSideEffects) OS << "|M_MAY_HAVE_SIDE_EFFECTS";
222 if (Inst.neverHasSideEffects) OS << "|M_NEVER_HAS_SIDE_EFFECTS";
225 // Emit all of the target-specific flags...
226 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
227 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
228 if (LI->getSize() != Shift->getSize())
229 throw "Lengths of " + InstrInfo->getName() +
230 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
232 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
233 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
234 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
238 // Emit the implicit uses and defs lists...
239 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
243 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
245 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
249 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
251 // Emit the operand info.
252 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
253 if (OperandInfo.empty())
256 OS << "OperandInfo" << OpInfo[OperandInfo];
258 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
262 bool operator()(const Record *Rec1, const Record *Rec2) const {
263 return Rec1->getName() < Rec2->getName();
266 void InstrInfoEmitter::GatherItinClasses() {
267 std::vector<Record*> DefList =
268 Records.getAllDerivedDefinitions("InstrItinClass");
269 IsItineraries = !DefList.empty();
271 if (!IsItineraries) return;
273 std::sort(DefList.begin(), DefList.end(), LessRecord());
275 for (unsigned i = 0, N = DefList.size(); i < N; i++) {
276 Record *Def = DefList[i];
277 ItinClassMap[Def->getName()] = i;
281 unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
282 return ItinClassMap[ItinName];
285 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
286 IntInit *ShiftInt, std::ostream &OS) {
287 if (Val == 0 || ShiftInt == 0)
288 throw std::string("Illegal value or shift amount in TargetInfo*!");
289 RecordVal *RV = R->getValue(Val->getValue());
290 int Shift = ShiftInt->getValue();
292 if (RV == 0 || RV->getValue() == 0) {
293 // This isn't an error if this is a builtin instruction.
294 if (R->getName() != "PHI" &&
295 R->getName() != "INLINEASM" &&
296 R->getName() != "LABEL" &&
297 R->getName() != "EXTRACT_SUBREG" &&
298 R->getName() != "INSERT_SUBREG")
299 throw R->getName() + " doesn't have a field named '" +
300 Val->getValue() + "'!";
304 Init *Value = RV->getValue();
305 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
306 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
308 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
309 // Convert the Bits to an integer to print...
310 Init *I = BI->convertInitializerTo(new IntRecTy());
312 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
313 if (II->getValue()) {
315 OS << "|(" << II->getValue() << "<<" << Shift << ")";
317 OS << "|" << II->getValue();
322 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
323 if (II->getValue()) {
325 OS << "|(" << II->getValue() << "<<" << Shift << ")";
327 OS << II->getValue();
332 std::cerr << "Unhandled initializer: " << *Val << "\n";
333 throw "In record '" + R->getName() + "' for TSFlag emission.";