1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
22 static void PrintDefList(const std::vector<Record*> &Uses,
23 unsigned Num, std::ostream &OS) {
24 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
25 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
26 OS << getQualifiedName(Uses[i]) << ", ";
30 //===----------------------------------------------------------------------===//
31 // Instruction Itinerary Information.
32 //===----------------------------------------------------------------------===//
34 struct RecordNameComparator {
35 bool operator()(const Record *Rec1, const Record *Rec2) const {
36 return Rec1->getName() < Rec2->getName();
40 void InstrInfoEmitter::GatherItinClasses() {
41 std::vector<Record*> DefList =
42 Records.getAllDerivedDefinitions("InstrItinClass");
43 std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
45 for (unsigned i = 0, N = DefList.size(); i < N; i++)
46 ItinClassMap[DefList[i]->getName()] = i;
49 unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
50 return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
53 //===----------------------------------------------------------------------===//
54 // Operand Info Emission.
55 //===----------------------------------------------------------------------===//
57 std::vector<std::string>
58 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
59 std::vector<std::string> Result;
61 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
62 // Handle aggregate operands and normal operands the same way by expanding
63 // either case into a list of operands for this op.
64 std::vector<CodeGenInstruction::OperandInfo> OperandList;
66 // This might be a multiple operand thing. Targets like X86 have
67 // registers in their multi-operand operands. It may also be an anonymous
68 // operand, which has a single operand, but no declared class for the
70 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
72 if (!MIOI || MIOI->getNumArgs() == 0) {
73 // Single, anonymous, operand.
74 OperandList.push_back(Inst.OperandList[i]);
76 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
77 OperandList.push_back(Inst.OperandList[i]);
79 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
80 OperandList.back().Rec = OpR;
84 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
85 Record *OpR = OperandList[j].Rec;
88 if (OpR->isSubClassOf("RegisterClass"))
89 Res += getQualifiedName(OpR) + "RegClassID, ";
92 // Fill in applicable flags.
95 // Ptr value whose register class is resolved via callback.
96 if (OpR->getName() == "ptr_rc")
97 Res += "|M_LOOK_UP_PTR_REG_CLASS";
99 // Predicate operands. Check to see if the original unexpanded operand
100 // was of type PredicateOperand.
101 if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
102 Res += "|M_PREDICATE_OPERAND";
104 // Optional def operands. Check to see if the original unexpanded operand
105 // was of type OptionalDefOperand.
106 if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
107 Res += "|M_OPTIONAL_DEF_OPERAND";
109 // Fill in constraint info.
110 Res += ", " + Inst.OperandList[i].Constraints[j];
111 Result.push_back(Res);
118 void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
119 OperandInfoMapTy &OperandInfoIDs) {
120 // ID #0 is for no operand info.
121 unsigned OperandListNum = 0;
122 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
125 const CodeGenTarget &Target = CDP.getTargetInfo();
126 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
127 E = Target.inst_end(); II != E; ++II) {
128 std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
129 unsigned &N = OperandInfoIDs[OperandInfo];
130 if (N != 0) continue;
132 N = ++OperandListNum;
133 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
134 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
135 OS << "{ " << OperandInfo[i] << " }, ";
140 //===----------------------------------------------------------------------===//
141 // Instruction Analysis
142 //===----------------------------------------------------------------------===//
144 void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
145 bool &isStore, bool &isLoad,
146 bool &NeverHasSideEffects) {
147 isStore = Inst.isStore;
148 isLoad = Inst.isLoad;
149 NeverHasSideEffects = Inst.neverHasSideEffects;
151 const TreePattern *Pattern = CDP.getInstruction(Inst.TheDef).getPattern();
152 if (Pattern == 0) return; // No pattern.
154 // FIXME: Change this to use pattern info.
155 if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
156 ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
157 if (LI && LI->getSize() > 0) {
158 DagInit *Dag = (DagInit *)LI->getElement(0);
159 DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
161 Record *Operator = OpDef->getDef();
162 if (Operator->isSubClassOf("SDNode")) {
163 const std::string Opcode = Operator->getValueAsString("Opcode");
164 if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
174 //===----------------------------------------------------------------------===//
176 //===----------------------------------------------------------------------===//
178 // run - Emit the main instruction description records for the target...
179 void InstrInfoEmitter::run(std::ostream &OS) {
182 EmitSourceFileHeader("Target Instruction Descriptors", OS);
183 OS << "namespace llvm {\n\n";
185 CodeGenTarget Target;
186 const std::string &TargetName = Target.getName();
187 Record *InstrInfo = Target.getInstructionSet();
189 // Keep track of all of the def lists we have emitted already.
190 std::map<std::vector<Record*>, unsigned> EmittedLists;
191 unsigned ListNumber = 0;
193 // Emit all of the instruction's implicit uses and defs.
194 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
195 E = Target.inst_end(); II != E; ++II) {
196 Record *Inst = II->second.TheDef;
197 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
199 unsigned &IL = EmittedLists[Uses];
200 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
202 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
204 unsigned &IL = EmittedLists[Defs];
205 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
209 OperandInfoMapTy OperandInfoIDs;
211 // Emit all of the operand info records.
212 EmitOperandInfo(OS, OperandInfoIDs);
214 // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
216 OS << "\nstatic const TargetInstrDescriptor " << TargetName
218 std::vector<const CodeGenInstruction*> NumberedInstructions;
219 Target.getInstructionsByEnumValue(NumberedInstructions);
221 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
222 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
225 OS << "} // End llvm namespace \n";
228 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
230 std::map<std::vector<Record*>, unsigned> &EmittedLists,
231 const OperandInfoMapTy &OpInfo,
233 // Determine properties of the instruction from its pattern.
234 bool isStore, isLoad, NeverHasSideEffects;
235 InferFromPattern(Inst, isStore, isLoad, NeverHasSideEffects);
237 if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
238 std::cerr << "error: Instruction '" << Inst.getName()
239 << "' is marked with 'mayHaveSideEffects', but it can never have them!\n";
244 if (!Inst.OperandList.empty())
245 // Each logical operand can be multiple MI operands.
246 MinOperands = Inst.OperandList.back().MIOperandNo +
247 Inst.OperandList.back().MINumOperands;
250 OS << Num << ",\t" << MinOperands << ",\t"
251 << Inst.NumDefs << ",\t\"" << Inst.getName();
252 OS << "\",\t" << getItinClassNumber(Inst.TheDef) << ", 0";
254 // Emit all of the target indepedent flags...
255 if (Inst.isReturn) OS << "|M_RET_FLAG";
256 if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
257 if (Inst.isIndirectBranch) OS << "|M_INDIRECT_FLAG";
258 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
259 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
260 if (Inst.isCall) OS << "|M_CALL_FLAG";
261 if (isLoad) OS << "|M_LOAD_FLAG";
262 if (isStore) OS << "|M_STORE_FLAG";
263 if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG";
264 if (Inst.isPredicable) OS << "|M_PREDICABLE";
265 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
266 if (Inst.isCommutable) OS << "|M_COMMUTABLE";
267 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
268 if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE";
269 if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE";
270 if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF";
271 if (Inst.usesCustomDAGSchedInserter)
272 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
273 if (Inst.hasVariableNumberOfOperands) OS << "|M_VARIABLE_OPS";
274 if (Inst.mayHaveSideEffects) OS << "|M_MAY_HAVE_SIDE_EFFECTS";
275 if (NeverHasSideEffects) OS << "|M_NEVER_HAS_SIDE_EFFECTS";
278 // Emit all of the target-specific flags...
279 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
280 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
281 if (LI->getSize() != Shift->getSize())
282 throw "Lengths of " + InstrInfo->getName() +
283 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
285 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
286 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
287 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
291 // Emit the implicit uses and defs lists...
292 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
296 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
298 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
302 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
304 // Emit the operand info.
305 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
306 if (OperandInfo.empty())
309 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
311 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
315 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
316 IntInit *ShiftInt, std::ostream &OS) {
317 if (Val == 0 || ShiftInt == 0)
318 throw std::string("Illegal value or shift amount in TargetInfo*!");
319 RecordVal *RV = R->getValue(Val->getValue());
320 int Shift = ShiftInt->getValue();
322 if (RV == 0 || RV->getValue() == 0) {
323 // This isn't an error if this is a builtin instruction.
324 if (R->getName() != "PHI" &&
325 R->getName() != "INLINEASM" &&
326 R->getName() != "LABEL" &&
327 R->getName() != "EXTRACT_SUBREG" &&
328 R->getName() != "INSERT_SUBREG")
329 throw R->getName() + " doesn't have a field named '" +
330 Val->getValue() + "'!";
334 Init *Value = RV->getValue();
335 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
336 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
338 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
339 // Convert the Bits to an integer to print...
340 Init *I = BI->convertInitializerTo(new IntRecTy());
342 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
343 if (II->getValue()) {
345 OS << "|(" << II->getValue() << "<<" << Shift << ")";
347 OS << "|" << II->getValue();
352 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
353 if (II->getValue()) {
355 OS << "|(" << II->getValue() << "<<" << Shift << ")";
357 OS << II->getValue();
362 std::cerr << "Unhandled initializer: " << *Val << "\n";
363 throw "In record '" + R->getName() + "' for TSFlag emission.";