1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/Target/TargetInstrInfo.h"
22 // runEnums - Print out enum values for all of the instructions.
23 void InstrInfoEmitter::runEnums(std::ostream &OS) {
24 EmitSourceFileHeader("Target Instruction Enum Values", OS);
25 OS << "namespace llvm {\n\n";
29 // We must emit the PHI opcode first...
30 std::string Namespace;
31 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
32 E = Target.inst_end(); II != E; ++II) {
33 if (II->second.Namespace != "TargetInstrInfo") {
34 Namespace = II->second.Namespace;
39 if (Namespace.empty()) {
40 std::cerr << "No instructions defined!\n";
44 std::vector<const CodeGenInstruction*> NumberedInstructions;
45 Target.getInstructionsByEnumValue(NumberedInstructions);
47 OS << "namespace " << Namespace << " {\n";
49 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
50 OS << " " << NumberedInstructions[i]->TheDef->getName()
51 << "\t= " << i << ",\n";
53 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
55 OS << "} // End llvm namespace \n";
58 void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
59 unsigned Num, std::ostream &OS) const {
60 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
61 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
62 OS << getQualifiedName(Uses[i]) << ", ";
66 static std::vector<std::pair<Record*, unsigned> >
67 GetOperandInfo(const CodeGenInstruction &Inst) {
68 std::vector<std::pair<Record*, unsigned> > Result;
69 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
70 if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
71 Result.push_back(std::make_pair(Inst.OperandList[i].Rec,
72 Inst.ConstraintsList[i]));
74 // This might be a multiple operand thing.
75 // Targets like X86 have registers in their multi-operand operands.
76 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
77 unsigned NumDefs = MIOI->getNumArgs();
78 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
80 Result.push_back(std::make_pair((Record*)0, Inst.ConstraintsList[i]));
82 DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
83 Result.push_back(std::make_pair(Def ? Def->getDef() : 0,
84 Inst.ConstraintsList[i]));
90 // For backward compatibility: isTwoAddress means operand 1 is tied to
92 if (Inst.isTwoAddress)
93 Result[1].second |= (0 << 16) | (1 << (unsigned)TargetInstrInfo::TIED_TO);
99 // run - Emit the main instruction description records for the target...
100 void InstrInfoEmitter::run(std::ostream &OS) {
103 EmitSourceFileHeader("Target Instruction Descriptors", OS);
104 OS << "namespace llvm {\n\n";
106 CodeGenTarget Target;
107 const std::string &TargetName = Target.getName();
108 Record *InstrInfo = Target.getInstructionSet();
110 // Keep track of all of the def lists we have emitted already.
111 std::map<std::vector<Record*>, unsigned> EmittedLists;
112 unsigned ListNumber = 0;
114 // Emit all of the instruction's implicit uses and defs.
115 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
116 E = Target.inst_end(); II != E; ++II) {
117 Record *Inst = II->second.TheDef;
118 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
120 unsigned &IL = EmittedLists[Uses];
121 if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
123 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
125 unsigned &IL = EmittedLists[Defs];
126 if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
130 std::map<std::vector<std::pair<Record*, unsigned> >, unsigned>
132 unsigned OperandListNum = 0;
133 OperandInfosEmitted[std::vector<std::pair<Record*, unsigned> >()] =
136 // Emit all of the operand info records.
138 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
139 E = Target.inst_end(); II != E; ++II) {
140 std::vector<std::pair<Record*, unsigned> > OperandInfo =
141 GetOperandInfo(II->second);
142 unsigned &N = OperandInfosEmitted[OperandInfo];
144 N = ++OperandListNum;
145 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
146 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
147 Record *RC = OperandInfo[i].first;
148 // FIXME: We only care about register operands for now.
149 if (RC && RC->isSubClassOf("RegisterClass"))
150 OS << "{ " << getQualifiedName(RC) << "RegClassID, 0, ";
151 else if (RC && RC->getName() == "ptr_rc")
152 // Ptr value whose register class is resolved via callback.
156 OS << OperandInfo[i].second << " }, ";
162 // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
164 OS << "\nstatic const TargetInstrDescriptor " << TargetName
166 std::vector<const CodeGenInstruction*> NumberedInstructions;
167 Target.getInstructionsByEnumValue(NumberedInstructions);
169 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
170 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
171 OperandInfosEmitted, OS);
173 OS << "} // End llvm namespace \n";
176 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
178 std::map<std::vector<Record*>, unsigned> &EmittedLists,
179 std::map<std::vector<std::pair<Record*,unsigned> >, unsigned> &OpInfo,
182 if (!Inst.OperandList.empty())
183 // Each logical operand can be multiple MI operands.
184 MinOperands = Inst.OperandList.back().MIOperandNo +
185 Inst.OperandList.back().MINumOperands;
190 if (Inst.Name.empty())
191 OS << Inst.TheDef->getName();
195 unsigned ItinClass = !IsItineraries ? 0 :
196 ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
198 OS << "\",\t" << MinOperands << ", " << ItinClass
201 // Try to determine (from the pattern), if the instruction is a store.
202 bool isStore = false;
203 if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
204 ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
205 if (LI && LI->getSize() > 0) {
206 DagInit *Dag = (DagInit *)LI->getElement(0);
207 DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
209 Record *Operator = OpDef->getDef();
210 if (Operator->isSubClassOf("SDNode")) {
211 const std::string Opcode = Operator->getValueAsString("Opcode");
212 if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
219 // Emit all of the target indepedent flags...
220 if (Inst.isReturn) OS << "|M_RET_FLAG";
221 if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
222 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
223 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
224 if (Inst.isCall) OS << "|M_CALL_FLAG";
225 if (Inst.isLoad) OS << "|M_LOAD_FLAG";
226 if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
227 if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
228 if (Inst.isPredicated) OS << "|M_PREDICATED";
229 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
230 if (Inst.isCommutable) OS << "|M_COMMUTABLE";
231 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
232 if (Inst.usesCustomDAGSchedInserter)
233 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
234 if (Inst.hasVariableNumberOfOperands)
235 OS << "|M_VARIABLE_OPS";
238 // Emit all of the target-specific flags...
239 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
240 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
241 if (LI->getSize() != Shift->getSize())
242 throw "Lengths of " + InstrInfo->getName() +
243 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
245 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
246 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
247 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
251 // Emit the implicit uses and defs lists...
252 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
256 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
258 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
262 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
264 // Emit the operand info.
265 std::vector<std::pair<Record*,unsigned> > OperandInfo = GetOperandInfo(Inst);
266 if (OperandInfo.empty())
269 OS << "OperandInfo" << OpInfo[OperandInfo];
271 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
275 bool operator()(const Record *Rec1, const Record *Rec2) const {
276 return Rec1->getName() < Rec2->getName();
279 void InstrInfoEmitter::GatherItinClasses() {
280 std::vector<Record*> DefList =
281 Records.getAllDerivedDefinitions("InstrItinClass");
282 IsItineraries = !DefList.empty();
284 if (!IsItineraries) return;
286 std::sort(DefList.begin(), DefList.end(), LessRecord());
288 for (unsigned i = 0, N = DefList.size(); i < N; i++) {
289 Record *Def = DefList[i];
290 ItinClassMap[Def->getName()] = i;
294 unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
295 return ItinClassMap[ItinName];
298 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
299 IntInit *ShiftInt, std::ostream &OS) {
300 if (Val == 0 || ShiftInt == 0)
301 throw std::string("Illegal value or shift amount in TargetInfo*!");
302 RecordVal *RV = R->getValue(Val->getValue());
303 int Shift = ShiftInt->getValue();
305 if (RV == 0 || RV->getValue() == 0) {
306 // This isn't an error if this is a builtin instruction.
307 if (R->getName() != "PHI" && R->getName() != "INLINEASM")
308 throw R->getName() + " doesn't have a field named '" +
309 Val->getValue() + "'!";
313 Init *Value = RV->getValue();
314 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
315 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
317 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
318 // Convert the Bits to an integer to print...
319 Init *I = BI->convertInitializerTo(new IntRecTy());
321 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
322 if (II->getValue()) {
324 OS << "|(" << II->getValue() << "<<" << Shift << ")";
326 OS << "|" << II->getValue();
331 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
332 if (II->getValue()) {
334 OS << "|(" << II->getValue() << "<<" << Shift << ")";
336 OS << II->getValue();
341 std::cerr << "Unhandled initializer: " << *Val << "\n";
342 throw "In record '" + R->getName() + "' for TSFlag emission.";