1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/Target/TargetInstrInfo.h"
22 // runEnums - Print out enum values for all of the instructions.
23 void InstrInfoEmitter::runEnums(std::ostream &OS) {
24 EmitSourceFileHeader("Target Instruction Enum Values", OS);
25 OS << "namespace llvm {\n\n";
29 // We must emit the PHI opcode first...
30 std::string Namespace;
31 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
32 E = Target.inst_end(); II != E; ++II) {
33 if (II->second.Namespace != "TargetInstrInfo") {
34 Namespace = II->second.Namespace;
39 if (Namespace.empty()) {
40 std::cerr << "No instructions defined!\n";
44 std::vector<const CodeGenInstruction*> NumberedInstructions;
45 Target.getInstructionsByEnumValue(NumberedInstructions);
47 OS << "namespace " << Namespace << " {\n";
49 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
50 OS << " " << NumberedInstructions[i]->TheDef->getName()
51 << "\t= " << i << ",\n";
53 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
55 OS << "} // End llvm namespace \n";
58 void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
59 unsigned Num, std::ostream &OS) const {
60 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
61 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
62 OS << getQualifiedName(Uses[i]) << ", ";
66 std::vector<std::string>
67 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
68 std::vector<std::string> Result;
69 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
70 if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
71 std::string OpStr = getQualifiedName(Inst.OperandList[i].Rec);
72 OpStr += "RegClassID, 0, ";
73 OpStr += Inst.OperandList[i].Constraint;
75 Result.push_back(OpStr);
77 // This might be a multiple operand thing. Targets like X86 have
78 // registers in their multi-operand operands. It may also be an anonymous
79 // operand, which has a single operand, but no declared class for the
81 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
83 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
85 if (MIOI && j < MIOI->getNumArgs())
86 if (DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j)))
92 if (OpR && OpR->isSubClassOf("RegisterClass"))
93 Res += getQualifiedName(OpR) + "RegClassID, ";
97 // Fill in applicable flags.
100 // Ptr value whose register class is resolved via callback.
101 if (OpR && OpR->getName() == "ptr_rc")
102 Res += "|M_LOOK_UP_PTR_REG_CLASS";
104 // Predicate operands.
105 if (j == 0 && Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
106 Res += "|M_PREDICATE_OPERAND";
108 // fill in constraint info.
109 Res += ", " + Inst.OperandList[i].Constraint;
111 Result.push_back(Res);
120 // run - Emit the main instruction description records for the target...
121 void InstrInfoEmitter::run(std::ostream &OS) {
124 EmitSourceFileHeader("Target Instruction Descriptors", OS);
125 OS << "namespace llvm {\n\n";
127 CodeGenTarget Target;
128 const std::string &TargetName = Target.getName();
129 Record *InstrInfo = Target.getInstructionSet();
131 // Keep track of all of the def lists we have emitted already.
132 std::map<std::vector<Record*>, unsigned> EmittedLists;
133 unsigned ListNumber = 0;
135 // Emit all of the instruction's implicit uses and defs.
136 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
137 E = Target.inst_end(); II != E; ++II) {
138 Record *Inst = II->second.TheDef;
139 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
141 unsigned &IL = EmittedLists[Uses];
142 if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
144 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
146 unsigned &IL = EmittedLists[Defs];
147 if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
151 std::map<std::vector<std::string>, unsigned> OperandInfosEmitted;
152 unsigned OperandListNum = 0;
153 OperandInfosEmitted[std::vector<std::string>()] = ++OperandListNum;
155 // Emit all of the operand info records.
157 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
158 E = Target.inst_end(); II != E; ++II) {
159 std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
160 unsigned &N = OperandInfosEmitted[OperandInfo];
162 N = ++OperandListNum;
163 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
164 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
165 OS << "{ " << OperandInfo[i] << " }, ";
170 // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
172 OS << "\nstatic const TargetInstrDescriptor " << TargetName
174 std::vector<const CodeGenInstruction*> NumberedInstructions;
175 Target.getInstructionsByEnumValue(NumberedInstructions);
177 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
178 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
179 OperandInfosEmitted, OS);
181 OS << "} // End llvm namespace \n";
184 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
186 std::map<std::vector<Record*>, unsigned> &EmittedLists,
187 std::map<std::vector<std::string>, unsigned> &OpInfo,
190 if (!Inst.OperandList.empty())
191 // Each logical operand can be multiple MI operands.
192 MinOperands = Inst.OperandList.back().MIOperandNo +
193 Inst.OperandList.back().MINumOperands;
198 if (Inst.Name.empty())
199 OS << Inst.TheDef->getName();
203 unsigned ItinClass = !IsItineraries ? 0 :
204 ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
206 OS << "\",\t" << MinOperands << ", " << ItinClass
209 // Try to determine (from the pattern), if the instruction is a store.
210 bool isStore = false;
211 if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
212 ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
213 if (LI && LI->getSize() > 0) {
214 DagInit *Dag = (DagInit *)LI->getElement(0);
215 DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
217 Record *Operator = OpDef->getDef();
218 if (Operator->isSubClassOf("SDNode")) {
219 const std::string Opcode = Operator->getValueAsString("Opcode");
220 if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
227 // Emit all of the target indepedent flags...
228 if (Inst.isReturn) OS << "|M_RET_FLAG";
229 if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
230 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
231 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
232 if (Inst.isCall) OS << "|M_CALL_FLAG";
233 if (Inst.isLoad) OS << "|M_LOAD_FLAG";
234 if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
235 if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
236 if (Inst.isPredicated) OS << "|M_PREDICATED";
237 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
238 if (Inst.isCommutable) OS << "|M_COMMUTABLE";
239 if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
240 if (Inst.usesCustomDAGSchedInserter)
241 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
242 if (Inst.hasVariableNumberOfOperands)
243 OS << "|M_VARIABLE_OPS";
246 // Emit all of the target-specific flags...
247 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
248 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
249 if (LI->getSize() != Shift->getSize())
250 throw "Lengths of " + InstrInfo->getName() +
251 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
253 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
254 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
255 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
259 // Emit the implicit uses and defs lists...
260 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
264 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
266 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
270 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
272 // Emit the operand info.
273 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
274 if (OperandInfo.empty())
277 OS << "OperandInfo" << OpInfo[OperandInfo];
279 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
283 bool operator()(const Record *Rec1, const Record *Rec2) const {
284 return Rec1->getName() < Rec2->getName();
287 void InstrInfoEmitter::GatherItinClasses() {
288 std::vector<Record*> DefList =
289 Records.getAllDerivedDefinitions("InstrItinClass");
290 IsItineraries = !DefList.empty();
292 if (!IsItineraries) return;
294 std::sort(DefList.begin(), DefList.end(), LessRecord());
296 for (unsigned i = 0, N = DefList.size(); i < N; i++) {
297 Record *Def = DefList[i];
298 ItinClassMap[Def->getName()] = i;
302 unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
303 return ItinClassMap[ItinName];
306 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
307 IntInit *ShiftInt, std::ostream &OS) {
308 if (Val == 0 || ShiftInt == 0)
309 throw std::string("Illegal value or shift amount in TargetInfo*!");
310 RecordVal *RV = R->getValue(Val->getValue());
311 int Shift = ShiftInt->getValue();
313 if (RV == 0 || RV->getValue() == 0) {
314 // This isn't an error if this is a builtin instruction.
315 if (R->getName() != "PHI" && R->getName() != "INLINEASM")
316 throw R->getName() + " doesn't have a field named '" +
317 Val->getValue() + "'!";
321 Init *Value = RV->getValue();
322 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
323 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
325 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
326 // Convert the Bits to an integer to print...
327 Init *I = BI->convertInitializerTo(new IntRecTy());
329 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
330 if (II->getValue()) {
332 OS << "|(" << II->getValue() << "<<" << Shift << ")";
334 OS << "|" << II->getValue();
339 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
340 if (II->getValue()) {
342 OS << "|(" << II->getValue() << "<<" << Shift << ")";
344 OS << II->getValue();
349 std::cerr << "Unhandled initializer: " << *Val << "\n";
350 throw "In record '" + R->getName() + "' for TSFlag emission.";