1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
26 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
29 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
31 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
33 EmitSourceFileHeader("Target Register Enum Values", OS);
34 OS << "namespace llvm {\n\n";
36 if (!Namespace.empty())
37 OS << "namespace " << Namespace << " {\n";
38 OS << "enum {\n NoRegister,\n";
40 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
41 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
42 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
44 if (!Namespace.empty())
47 const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
48 if (!SubRegIndices.empty()) {
49 OS << "\n// Subregister indices\n";
50 Namespace = SubRegIndices[0]->getValueAsString("Namespace");
51 if (!Namespace.empty())
52 OS << "namespace " << Namespace << " {\n";
53 OS << "enum {\n NoSubRegister,\n";
54 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
55 OS << " " << SubRegIndices[i]->getName() << " = "
56 << SubRegIndices[i]->getValueAsInt("NumberHack") << ",\n";
57 OS << " NUM_TARGET_SUBREGS = " << SubRegIndices.size()+1 << "\n";
59 if (!Namespace.empty())
62 OS << "} // End llvm namespace \n";
65 void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
66 EmitSourceFileHeader("Register Information Header Fragment", OS);
68 const std::string &TargetName = Target.getName();
69 std::string ClassName = TargetName + "GenRegisterInfo";
71 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
72 OS << "#include <string>\n\n";
74 OS << "namespace llvm {\n\n";
76 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
77 << " explicit " << ClassName
78 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
79 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
80 << "unsigned Flavour) const;\n"
81 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
82 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
83 << " { return false; }\n"
84 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
85 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
88 const std::vector<CodeGenRegisterClass> &RegisterClasses =
89 Target.getRegisterClasses();
91 if (!RegisterClasses.empty()) {
92 OS << "namespace " << RegisterClasses[0].Namespace
93 << " { // Register classes\n";
96 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
98 OS << " " << RegisterClasses[i].getName() << "RegClassID";
103 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
104 const std::string &Name = RegisterClasses[i].getName();
106 // Output the register class definition.
107 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
108 << " " << Name << "Class();\n"
109 << RegisterClasses[i].MethodProtos << " };\n";
111 // Output the extern for the instance.
112 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
113 // Output the extern for the pointer to the instance (should remove).
114 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
115 << Name << "RegClass;\n";
117 OS << "} // end of namespace " << TargetName << "\n\n";
119 OS << "} // End llvm namespace \n";
122 bool isSubRegisterClass(const CodeGenRegisterClass &RC,
123 std::set<Record*> &RegSet) {
124 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
125 Record *Reg = RC.Elements[i];
126 if (!RegSet.count(Reg))
132 static void addSuperReg(Record *R, Record *S,
133 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
134 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
135 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
137 errs() << "Error: recursive sub-register relationship between"
138 << " register " << getQualifiedName(R)
139 << " and its sub-registers?\n";
142 if (!SuperRegs[R].insert(S).second)
144 SubRegs[S].insert(R);
145 Aliases[R].insert(S);
146 Aliases[S].insert(R);
147 if (SuperRegs.count(S))
148 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
149 E = SuperRegs[S].end(); I != E; ++I)
150 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
153 static void addSubSuperReg(Record *R, Record *S,
154 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
155 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
156 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
158 errs() << "Error: recursive sub-register relationship between"
159 << " register " << getQualifiedName(R)
160 << " and its sub-registers?\n";
164 if (!SubRegs[R].insert(S).second)
166 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
167 Aliases[R].insert(S);
168 Aliases[S].insert(R);
169 if (SubRegs.count(S))
170 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
171 E = SubRegs[S].end(); I != E; ++I)
172 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
175 class RegisterSorter {
177 std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
180 RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
181 : RegisterSubRegs(RS) {}
183 bool operator()(Record *RegA, Record *RegB) {
184 // B is sub-register of A.
185 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
189 // RegisterInfoEmitter::run - Main register file description emitter.
191 void RegisterInfoEmitter::run(raw_ostream &OS) {
192 CodeGenTarget Target;
193 EmitSourceFileHeader("Register Information Source Fragment", OS);
195 OS << "namespace llvm {\n\n";
197 // Start out by emitting each of the register classes... to do this, we build
198 // a set of registers which belong to a register class, this is to ensure that
199 // each register is only in a single register class.
201 const std::vector<CodeGenRegisterClass> &RegisterClasses =
202 Target.getRegisterClasses();
204 // Loop over all of the register classes... emitting each one.
205 OS << "namespace { // Register classes...\n";
207 // RegClassesBelongedTo - Keep track of which register classes each reg
209 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
211 // Emit the register enum value arrays for each RegisterClass
212 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
213 const CodeGenRegisterClass &RC = RegisterClasses[rc];
215 // Give the register class a legal C name if it's anonymous.
216 std::string Name = RC.TheDef->getName();
218 // Emit the register list now.
219 OS << " // " << Name << " Register Class...\n"
220 << " static const unsigned " << Name
222 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
223 Record *Reg = RC.Elements[i];
224 OS << getQualifiedName(Reg) << ", ";
226 // Keep track of which regclasses this register is in.
227 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
232 // Emit the ValueType arrays for each RegisterClass
233 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
234 const CodeGenRegisterClass &RC = RegisterClasses[rc];
236 // Give the register class a legal C name if it's anonymous.
237 std::string Name = RC.TheDef->getName() + "VTs";
239 // Emit the register list now.
241 << " Register Class Value Types...\n"
242 << " static const EVT " << Name
244 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
245 OS << getEnumName(RC.VTs[i]) << ", ";
246 OS << "MVT::Other\n };\n\n";
248 OS << "} // end anonymous namespace\n\n";
250 // Now that all of the structs have been emitted, emit the instances.
251 if (!RegisterClasses.empty()) {
252 OS << "namespace " << RegisterClasses[0].Namespace
253 << " { // Register class instances\n";
254 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
255 OS << " " << RegisterClasses[i].getName() << "Class\t"
256 << RegisterClasses[i].getName() << "RegClass;\n";
258 std::map<unsigned, std::set<unsigned> > SuperClassMap;
259 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
262 unsigned NumSubRegIndices = Target.getSubRegIndices().size();
264 if (NumSubRegIndices) {
265 // Emit the sub-register classes for each RegisterClass
266 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
267 const CodeGenRegisterClass &RC = RegisterClasses[rc];
268 std::vector<Record*> SRC(NumSubRegIndices);
269 for (DenseMap<Record*,Record*>::const_iterator
270 i = RC.SubRegClasses.begin(),
271 e = RC.SubRegClasses.end(); i != e; ++i) {
273 unsigned idx = Target.getSubRegIndexNo(i->first);
274 SRC.at(idx-1) = i->second;
276 // Find the register class number of i->second for SuperRegClassMap.
277 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
278 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
279 if (RC2.TheDef == i->second) {
280 SuperRegClassMap[rc2].insert(rc);
286 // Give the register class a legal C name if it's anonymous.
287 std::string Name = RC.TheDef->getName();
290 << " Sub-register Classes...\n"
291 << " static const TargetRegisterClass* const "
292 << Name << "SubRegClasses[] = {\n ";
294 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
298 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
305 // Emit the super-register classes for each RegisterClass
306 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
307 const CodeGenRegisterClass &RC = RegisterClasses[rc];
309 // Give the register class a legal C name if it's anonymous.
310 std::string Name = RC.TheDef->getName();
313 << " Super-register Classes...\n"
314 << " static const TargetRegisterClass* const "
315 << Name << "SuperRegClasses[] = {\n ";
318 std::map<unsigned, std::set<unsigned> >::iterator I =
319 SuperRegClassMap.find(rc);
320 if (I != SuperRegClassMap.end()) {
321 for (std::set<unsigned>::iterator II = I->second.begin(),
322 EE = I->second.end(); II != EE; ++II) {
323 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
326 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
331 OS << (!Empty ? ", " : "") << "NULL";
335 // No subregindices in this target
336 OS << " static const TargetRegisterClass* const "
337 << "NullRegClasses[] = { NULL };\n\n";
340 // Emit the sub-classes array for each RegisterClass
341 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
342 const CodeGenRegisterClass &RC = RegisterClasses[rc];
344 // Give the register class a legal C name if it's anonymous.
345 std::string Name = RC.TheDef->getName();
347 std::set<Record*> RegSet;
348 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
349 Record *Reg = RC.Elements[i];
354 << " Register Class sub-classes...\n"
355 << " static const TargetRegisterClass* const "
356 << Name << "Subclasses[] = {\n ";
359 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
360 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
362 // RC2 is a sub-class of RC if it is a valid replacement for any
363 // instruction operand where an RC register is required. It must satisfy
366 // 1. All RC2 registers are also in RC.
367 // 2. The RC2 spill size must not be smaller that the RC spill size.
368 // 3. RC2 spill alignment must be compatible with RC.
370 // Sub-classes are used to determine if a virtual register can be used
371 // as an instruction operand, or if it must be copied first.
373 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
374 (RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) ||
375 RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
378 if (!Empty) OS << ", ";
379 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
382 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
383 SuperClassMap.find(rc2);
384 if (SCMI == SuperClassMap.end()) {
385 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
386 SCMI = SuperClassMap.find(rc2);
388 SCMI->second.insert(rc);
391 OS << (!Empty ? ", " : "") << "NULL";
395 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
396 const CodeGenRegisterClass &RC = RegisterClasses[rc];
398 // Give the register class a legal C name if it's anonymous.
399 std::string Name = RC.TheDef->getName();
402 << " Register Class super-classes...\n"
403 << " static const TargetRegisterClass* const "
404 << Name << "Superclasses[] = {\n ";
407 std::map<unsigned, std::set<unsigned> >::iterator I =
408 SuperClassMap.find(rc);
409 if (I != SuperClassMap.end()) {
410 for (std::set<unsigned>::iterator II = I->second.begin(),
411 EE = I->second.end(); II != EE; ++II) {
412 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
413 if (!Empty) OS << ", ";
414 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
419 OS << (!Empty ? ", " : "") << "NULL";
424 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
425 const CodeGenRegisterClass &RC = RegisterClasses[i];
426 OS << RC.MethodBodies << "\n";
427 OS << RC.getName() << "Class::" << RC.getName()
428 << "Class() : TargetRegisterClass("
429 << RC.getName() + "RegClassID" << ", "
430 << '\"' << RC.getName() << "\", "
431 << RC.getName() + "VTs" << ", "
432 << RC.getName() + "Subclasses" << ", "
433 << RC.getName() + "Superclasses" << ", "
434 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
436 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
438 << RC.SpillSize/8 << ", "
439 << RC.SpillAlignment/8 << ", "
440 << RC.CopyCost << ", "
441 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
448 OS << "\nnamespace {\n";
449 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
450 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
451 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
455 // Emit register sub-registers / super-registers, aliases...
456 std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
457 std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
458 std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
459 std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
460 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
461 DwarfRegNumsMapTy DwarfRegNums;
463 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
465 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
466 Record *R = Regs[i].TheDef;
467 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
468 // Add information that R aliases all of the elements in the list... and
469 // that everything in the list aliases R.
470 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
472 if (RegisterAliases[R].count(Reg))
473 errs() << "Warning: register alias between " << getQualifiedName(R)
474 << " and " << getQualifiedName(Reg)
475 << " specified multiple times!\n";
476 RegisterAliases[R].insert(Reg);
478 if (RegisterAliases[Reg].count(R))
479 errs() << "Warning: register alias between " << getQualifiedName(R)
480 << " and " << getQualifiedName(Reg)
481 << " specified multiple times!\n";
482 RegisterAliases[Reg].insert(R);
486 // Process sub-register sets.
487 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
488 Record *R = Regs[i].TheDef;
489 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
490 // Process sub-register set and add aliases information.
491 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
492 Record *SubReg = LI[j];
493 if (RegisterSubRegs[R].count(SubReg))
494 errs() << "Warning: register " << getQualifiedName(SubReg)
495 << " specified as a sub-register of " << getQualifiedName(R)
496 << " multiple times!\n";
497 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
502 // Print the SubregHashTable, a simple quadratically probed
503 // hash table for determining if a register is a subregister
504 // of another register.
505 unsigned NumSubRegs = 0;
506 std::map<Record*, unsigned> RegNo;
507 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
508 RegNo[Regs[i].TheDef] = i;
509 NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
512 unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
513 unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
514 std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
516 unsigned hashMisses = 0;
518 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
519 Record* R = Regs[i].TheDef;
520 for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
521 E = RegisterSubRegs[R].end(); I != E; ++I) {
523 // We have to increase the indices of both registers by one when
524 // computing the hash because, in the generated code, there
525 // will be an extra empty slot at register 0.
526 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
527 unsigned ProbeAmt = 2;
528 while (SubregHashTable[index*2] != ~0U &&
529 SubregHashTable[index*2+1] != ~0U) {
530 index = (index + ProbeAmt) & (SubregHashTableSize-1);
536 SubregHashTable[index*2] = i;
537 SubregHashTable[index*2+1] = RegNo[RJ];
541 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
543 if (SubregHashTableSize) {
544 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
546 OS << " const unsigned SubregHashTable[] = { ";
547 for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
549 // Insert spaces for nice formatting.
552 if (SubregHashTable[2*i] != ~0U) {
553 OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
554 << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
556 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
560 unsigned Idx = SubregHashTableSize*2-2;
561 if (SubregHashTable[Idx] != ~0U) {
563 << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
564 << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
566 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
569 OS << " const unsigned SubregHashTableSize = "
570 << SubregHashTableSize << ";\n";
572 OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
573 << " const unsigned SubregHashTableSize = 1;\n";
576 delete [] SubregHashTable;
579 // Print the SuperregHashTable, a simple quadratically probed
580 // hash table for determining if a register is a super-register
581 // of another register.
582 unsigned NumSupRegs = 0;
584 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
585 RegNo[Regs[i].TheDef] = i;
586 NumSupRegs += RegisterSuperRegs[Regs[i].TheDef].size();
589 unsigned SuperregHashTableSize = 2 * NextPowerOf2(2 * NumSupRegs);
590 unsigned* SuperregHashTable = new unsigned[2 * SuperregHashTableSize];
591 std::fill(SuperregHashTable, SuperregHashTable + 2 * SuperregHashTableSize, ~0U);
595 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
596 Record* R = Regs[i].TheDef;
597 for (std::set<Record*>::iterator I = RegisterSuperRegs[R].begin(),
598 E = RegisterSuperRegs[R].end(); I != E; ++I) {
600 // We have to increase the indices of both registers by one when
601 // computing the hash because, in the generated code, there
602 // will be an extra empty slot at register 0.
603 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SuperregHashTableSize-1);
604 unsigned ProbeAmt = 2;
605 while (SuperregHashTable[index*2] != ~0U &&
606 SuperregHashTable[index*2+1] != ~0U) {
607 index = (index + ProbeAmt) & (SuperregHashTableSize-1);
613 SuperregHashTable[index*2] = i;
614 SuperregHashTable[index*2+1] = RegNo[RJ];
618 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
620 if (SuperregHashTableSize) {
621 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
623 OS << " const unsigned SuperregHashTable[] = { ";
624 for (unsigned i = 0; i < SuperregHashTableSize - 1; ++i) {
626 // Insert spaces for nice formatting.
629 if (SuperregHashTable[2*i] != ~0U) {
630 OS << getQualifiedName(Regs[SuperregHashTable[2*i]].TheDef) << ", "
631 << getQualifiedName(Regs[SuperregHashTable[2*i+1]].TheDef) << ", \n";
633 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
637 unsigned Idx = SuperregHashTableSize*2-2;
638 if (SuperregHashTable[Idx] != ~0U) {
640 << getQualifiedName(Regs[SuperregHashTable[Idx]].TheDef) << ", "
641 << getQualifiedName(Regs[SuperregHashTable[Idx+1]].TheDef) << " };\n";
643 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
646 OS << " const unsigned SuperregHashTableSize = "
647 << SuperregHashTableSize << ";\n";
649 OS << " const unsigned SuperregHashTable[] = { ~0U, ~0U };\n"
650 << " const unsigned SuperregHashTableSize = 1;\n";
653 delete [] SuperregHashTable;
656 // Print the AliasHashTable, a simple quadratically probed
657 // hash table for determining if a register aliases another register.
658 unsigned NumAliases = 0;
660 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
661 RegNo[Regs[i].TheDef] = i;
662 NumAliases += RegisterAliases[Regs[i].TheDef].size();
665 unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
666 unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
667 std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
671 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
672 Record* R = Regs[i].TheDef;
673 for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
674 E = RegisterAliases[R].end(); I != E; ++I) {
676 // We have to increase the indices of both registers by one when
677 // computing the hash because, in the generated code, there
678 // will be an extra empty slot at register 0.
679 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
680 unsigned ProbeAmt = 2;
681 while (AliasesHashTable[index*2] != ~0U &&
682 AliasesHashTable[index*2+1] != ~0U) {
683 index = (index + ProbeAmt) & (AliasesHashTableSize-1);
689 AliasesHashTable[index*2] = i;
690 AliasesHashTable[index*2+1] = RegNo[RJ];
694 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
696 if (AliasesHashTableSize) {
697 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
699 OS << " const unsigned AliasesHashTable[] = { ";
700 for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
702 // Insert spaces for nice formatting.
705 if (AliasesHashTable[2*i] != ~0U) {
706 OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
707 << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
709 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
713 unsigned Idx = AliasesHashTableSize*2-2;
714 if (AliasesHashTable[Idx] != ~0U) {
716 << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
717 << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
719 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
722 OS << " const unsigned AliasesHashTableSize = "
723 << AliasesHashTableSize << ";\n";
725 OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
726 << " const unsigned AliasesHashTableSize = 1;\n";
729 delete [] AliasesHashTable;
731 if (!RegisterAliases.empty())
732 OS << "\n\n // Register Alias Sets...\n";
734 // Emit the empty alias list
735 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
736 // Loop over all of the registers which have aliases, emitting the alias list
738 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
739 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
740 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
741 for (std::set<Record*>::iterator ASI = I->second.begin(),
742 E = I->second.end(); ASI != E; ++ASI)
743 OS << getQualifiedName(*ASI) << ", ";
747 if (!RegisterSubRegs.empty())
748 OS << "\n\n // Register Sub-registers Sets...\n";
750 // Emit the empty sub-registers list
751 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
752 // Loop over all of the registers which have sub-registers, emitting the
753 // sub-registers list to memory.
754 for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
755 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
756 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
757 std::vector<Record*> SubRegsVector;
758 for (std::set<Record*>::iterator ASI = I->second.begin(),
759 E = I->second.end(); ASI != E; ++ASI)
760 SubRegsVector.push_back(*ASI);
761 RegisterSorter RS(RegisterSubRegs);
762 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
763 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
764 OS << getQualifiedName(SubRegsVector[i]) << ", ";
768 if (!RegisterSuperRegs.empty())
769 OS << "\n\n // Register Super-registers Sets...\n";
771 // Emit the empty super-registers list
772 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
773 // Loop over all of the registers which have super-registers, emitting the
774 // super-registers list to memory.
775 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
776 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
777 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
779 std::vector<Record*> SuperRegsVector;
780 for (std::set<Record*>::iterator ASI = I->second.begin(),
781 E = I->second.end(); ASI != E; ++ASI)
782 SuperRegsVector.push_back(*ASI);
783 RegisterSorter RS(RegisterSubRegs);
784 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
785 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
786 OS << getQualifiedName(SuperRegsVector[i]) << ", ";
790 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
791 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
793 // Now that register alias and sub-registers sets have been emitted, emit the
794 // register descriptors now.
795 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
796 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
797 const CodeGenRegister &Reg = Registers[i];
799 OS << Reg.getName() << "\",\t";
800 if (RegisterAliases.count(Reg.TheDef))
801 OS << Reg.getName() << "_AliasSet,\t";
803 OS << "Empty_AliasSet,\t";
804 if (RegisterSubRegs.count(Reg.TheDef))
805 OS << Reg.getName() << "_SubRegsSet,\t";
807 OS << "Empty_SubRegsSet,\t";
808 if (RegisterSuperRegs.count(Reg.TheDef))
809 OS << Reg.getName() << "_SuperRegsSet },\n";
811 OS << "Empty_SuperRegsSet },\n";
813 OS << " };\n"; // End of register descriptors...
814 OS << "}\n\n"; // End of anonymous namespace...
816 std::string ClassName = Target.getName() + "GenRegisterInfo";
818 // Calculate the mapping of subregister+index pairs to physical registers.
819 std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
820 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
821 int subRegIndex = SubRegs[i]->getValueAsInt("index");
822 std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
823 std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
825 if (From.size() != To.size()) {
826 errs() << "Error: register list and sub-register list not of equal length"
827 << " in SubRegSet\n";
831 // For each entry in from/to vectors, insert the to register at index
832 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
833 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
836 // Emit the subregister + index mapping function based on the information
838 OS << "unsigned " << ClassName
839 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
840 << " switch (RegNo) {\n"
841 << " default:\n return 0;\n";
842 for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
843 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
844 OS << " case " << getQualifiedName(I->first) << ":\n";
845 OS << " switch (Index) {\n";
846 OS << " default: return 0;\n";
847 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
848 OS << " case " << (I->second)[i].first << ": return "
849 << getQualifiedName((I->second)[i].second) << ";\n";
850 OS << " };\n" << " break;\n";
853 OS << " return 0;\n";
856 OS << "unsigned " << ClassName
857 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
858 << " switch (RegNo) {\n"
859 << " default:\n return 0;\n";
860 for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
861 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
862 OS << " case " << getQualifiedName(I->first) << ":\n";
863 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
864 OS << " if (SubRegNo == "
865 << getQualifiedName((I->second)[i].second)
866 << ") return " << (I->second)[i].first << ";\n";
867 OS << " return 0;\n";
870 OS << " return 0;\n";
873 // Emit the constructor of the class...
874 OS << ClassName << "::" << ClassName
875 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
876 << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
877 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
878 << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
879 << " SubregHashTable, SubregHashTableSize,\n"
880 << " SuperregHashTable, SuperregHashTableSize,\n"
881 << " AliasesHashTable, AliasesHashTableSize) {\n"
884 // Collect all information about dwarf register numbers
886 // First, just pull all provided information to the map
887 unsigned maxLength = 0;
888 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
889 Record *Reg = Registers[i].TheDef;
890 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
891 maxLength = std::max((size_t)maxLength, RegNums.size());
892 if (DwarfRegNums.count(Reg))
893 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
894 << "specified multiple times\n";
895 DwarfRegNums[Reg] = RegNums;
898 // Now we know maximal length of number list. Append -1's, where needed
899 for (DwarfRegNumsMapTy::iterator
900 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
901 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
902 I->second.push_back(-1);
904 // Emit information about the dwarf register numbers.
905 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
906 << "unsigned Flavour) const {\n"
907 << " switch (Flavour) {\n"
909 << " assert(0 && \"Unknown DWARF flavour\");\n"
912 for (unsigned i = 0, e = maxLength; i != e; ++i) {
913 OS << " case " << i << ":\n"
914 << " switch (RegNum) {\n"
916 << " assert(0 && \"Invalid RegNum\");\n"
919 // Sort by name to get a stable order.
922 for (DwarfRegNumsMapTy::iterator
923 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
924 int RegNo = I->second[i];
926 OS << " case " << getQualifiedName(I->first) << ":\n"
927 << " return " << RegNo << ";\n";
929 OS << " case " << getQualifiedName(I->first) << ":\n"
930 << " assert(0 && \"Invalid register for this mode\");\n"
938 OS << "} // End llvm namespace \n";