1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
25 // runEnums - Print out enum values for all of the registers.
26 void RegisterInfoEmitter::runEnums(std::ostream &OS) {
28 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
30 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
32 EmitSourceFileHeader("Target Register Enum Values", OS);
33 OS << "namespace llvm {\n\n";
35 if (!Namespace.empty())
36 OS << "namespace " << Namespace << " {\n";
37 OS << " enum {\n NoRegister,\n";
39 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
40 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
43 if (!Namespace.empty())
45 OS << "} // End llvm namespace \n";
48 void RegisterInfoEmitter::runHeader(std::ostream &OS) {
49 EmitSourceFileHeader("Register Information Header Fragment", OS);
51 const std::string &TargetName = Target.getName();
52 std::string ClassName = TargetName + "GenRegisterInfo";
54 OS << "#include \"llvm/Target/MRegisterInfo.h\"\n\n";
56 OS << "namespace llvm {\n\n";
58 OS << "struct " << ClassName << " : public MRegisterInfo {\n"
60 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
61 << " const unsigned* getCalleeSaveRegs() const;\n"
64 const std::vector<CodeGenRegisterClass> &RegisterClasses =
65 Target.getRegisterClasses();
67 if (!RegisterClasses.empty()) {
68 OS << "namespace " << RegisterClasses[0].Namespace
69 << " { // Register classes\n";
70 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
71 const std::string &Name = RegisterClasses[i].getName();
73 // Output the register class definition.
74 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
75 << " " << Name << "Class();\n"
76 << RegisterClasses[i].MethodProtos << " };\n";
78 // Output the extern for the instance.
79 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
80 // Output the extern for the pointer to the instance (should remove).
81 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
82 << Name << "RegClass;\n";
84 OS << "} // end of namespace " << TargetName << "\n\n";
86 OS << "} // End llvm namespace \n";
89 // RegisterInfoEmitter::run - Main register file description emitter.
91 void RegisterInfoEmitter::run(std::ostream &OS) {
93 EmitSourceFileHeader("Register Information Source Fragment", OS);
95 OS << "namespace llvm {\n\n";
97 // Start out by emitting each of the register classes... to do this, we build
98 // a set of registers which belong to a register class, this is to ensure that
99 // each register is only in a single register class.
101 const std::vector<CodeGenRegisterClass> &RegisterClasses =
102 Target.getRegisterClasses();
104 // Loop over all of the register classes... emitting each one.
105 OS << "namespace { // Register classes...\n";
107 // RegClassesBelongedTo - Keep track of which register classes each reg
109 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
111 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
112 const CodeGenRegisterClass &RC = RegisterClasses[rc];
114 // Give the register class a legal C name if it's anonymous.
115 std::string Name = RC.TheDef->getName();
117 // Emit the register list now.
118 OS << " // " << Name << " Register Class...\n const unsigned " << Name
120 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
121 Record *Reg = RC.Elements[i];
122 OS << getQualifiedName(Reg) << ", ";
124 // Keep track of which regclasses this register is in.
125 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
129 OS << "} // end anonymous namespace\n\n";
131 // Now that all of the structs have been emitted, emit the instances.
132 if (!RegisterClasses.empty()) {
133 OS << "namespace " << RegisterClasses[0].Namespace
134 << " { // Register class instances\n";
135 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
136 OS << " " << RegisterClasses[i].getName() << "Class\t"
137 << RegisterClasses[i].getName() << "RegClass;\n";
139 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
140 const CodeGenRegisterClass &RC = RegisterClasses[i];
141 OS << RC.MethodBodies << "\n";
142 OS << RC.getName() << "Class::" << RC.getName()
143 << "Class() : TargetRegisterClass(" << RC.SpillSize/8 << ", "
144 << RC.SpillAlignment/8 << ", " << RC.getName() << ", "
145 << RC.getName() << " + " << RC.Elements.size() << ") {}\n";
151 OS << "\nnamespace {\n";
152 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
153 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
154 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
158 // Emit register class aliases...
159 std::map<Record*, std::set<Record*> > RegisterAliases;
160 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
162 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
163 Record *R = Regs[i].TheDef;
164 ListInit *LI = Regs[i].TheDef->getValueAsListInit("Aliases");
165 // Add information that R aliases all of the elements in the list... and
166 // that everything in the list aliases R.
167 for (unsigned j = 0, e = LI->getSize(); j != e; ++j) {
168 DefInit *Reg = dynamic_cast<DefInit*>(LI->getElement(j));
169 if (!Reg) throw "ERROR: Alias list element is not a def!";
170 if (RegisterAliases[R].count(Reg->getDef()))
171 std::cerr << "Warning: register alias between " << getQualifiedName(R)
172 << " and " << getQualifiedName(Reg->getDef())
173 << " specified multiple times!\n";
174 RegisterAliases[R].insert(Reg->getDef());
176 if (RegisterAliases[Reg->getDef()].count(R))
177 std::cerr << "Warning: register alias between " << getQualifiedName(R)
178 << " and " << getQualifiedName(Reg->getDef())
179 << " specified multiple times!\n";
180 RegisterAliases[Reg->getDef()].insert(R);
184 if (!RegisterAliases.empty())
185 OS << "\n\n // Register Alias Sets...\n";
187 // Emit the empty alias list
188 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
189 // Loop over all of the registers which have aliases, emitting the alias list
191 for (std::map<Record*, std::set<Record*> >::iterator
192 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
193 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
194 for (std::set<Record*>::iterator ASI = I->second.begin(),
195 E = I->second.end(); ASI != E; ++ASI)
196 OS << getQualifiedName(*ASI) << ", ";
200 OS << "\n const MRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
201 OS << " { \"NOREG\",\t0,\t\t0,\t0 },\n";
204 // Now that register alias sets have been emitted, emit the register
206 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
207 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
208 const CodeGenRegister &Reg = Registers[i];
210 if (!Reg.TheDef->getValueAsString("Name").empty())
211 OS << Reg.TheDef->getValueAsString("Name");
215 if (RegisterAliases.count(Reg.TheDef))
216 OS << Reg.getName() << "_AliasSet,\t";
218 OS << "Empty_AliasSet,\t";
220 // Figure out what the size and alignment of the spill slots are for this
221 // reg. This may be explicitly declared in the register, or it may be
222 // inferred from the register classes it is part of.
223 std::multimap<Record*, const CodeGenRegisterClass*>::iterator I, E;
224 tie(I, E) = RegClassesBelongedTo.equal_range(Reg.TheDef);
225 unsigned SpillSize = Reg.DeclaredSpillSize;
226 unsigned SpillAlign = Reg.DeclaredSpillAlignment;
227 for (; I != E; ++I) { // For each reg class this belongs to.
228 const CodeGenRegisterClass *RC = I->second;
229 SpillSize = std::max(SpillSize, RC->SpillSize);
230 SpillAlign = std::max(SpillAlign, RC->SpillAlignment);
233 OS << SpillSize << ", " << SpillAlign << " },\n";
235 OS << " };\n"; // End of register descriptors...
236 OS << "}\n\n"; // End of anonymous namespace...
238 std::string ClassName = Target.getName() + "GenRegisterInfo";
240 // Emit the constructor of the class...
241 OS << ClassName << "::" << ClassName
242 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
243 << " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1
244 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
245 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
247 // Emit the getCalleeSaveRegs method...
248 OS << "const unsigned* " << ClassName << "::getCalleeSaveRegs() const {\n"
249 << " static const unsigned CalleeSaveRegs[] = {\n ";
251 const std::vector<Record*> &CSR = Target.getCalleeSavedRegisters();
252 for (unsigned i = 0, e = CSR.size(); i != e; ++i)
253 OS << getQualifiedName(CSR[i]) << ", ";
254 OS << " 0\n };\n return CalleeSaveRegs;\n}\n\n";
255 OS << "} // End llvm namespace \n";