1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Streams.h"
26 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(std::ostream &OS) {
29 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
31 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
33 EmitSourceFileHeader("Target Register Enum Values", OS);
34 OS << "namespace llvm {\n\n";
36 if (!Namespace.empty())
37 OS << "namespace " << Namespace << " {\n";
38 OS << " enum {\n NoRegister,\n";
40 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
41 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
42 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
44 if (!Namespace.empty())
46 OS << "} // End llvm namespace \n";
49 void RegisterInfoEmitter::runHeader(std::ostream &OS) {
50 EmitSourceFileHeader("Register Information Header Fragment", OS);
52 const std::string &TargetName = Target.getName();
53 std::string ClassName = TargetName + "GenRegisterInfo";
55 OS << "#include \"llvm/Target/MRegisterInfo.h\"\n";
56 OS << "#include <string>\n\n";
58 OS << "namespace llvm {\n\n";
60 OS << "struct " << ClassName << " : public MRegisterInfo {\n"
62 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
63 << " int getDwarfRegNum(unsigned RegNum) const;\n"
66 const std::vector<CodeGenRegisterClass> &RegisterClasses =
67 Target.getRegisterClasses();
69 if (!RegisterClasses.empty()) {
70 OS << "namespace " << RegisterClasses[0].Namespace
71 << " { // Register classes\n";
74 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
76 OS << " " << RegisterClasses[i].getName() << "RegClassID";
81 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
82 const std::string &Name = RegisterClasses[i].getName();
84 // Output the register class definition.
85 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
86 << " " << Name << "Class();\n"
87 << RegisterClasses[i].MethodProtos << " };\n";
89 // Output the extern for the instance.
90 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
91 // Output the extern for the pointer to the instance (should remove).
92 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
93 << Name << "RegClass;\n";
95 OS << "} // end of namespace " << TargetName << "\n\n";
97 OS << "} // End llvm namespace \n";
100 bool isSubRegisterClass(const CodeGenRegisterClass &RC,
101 std::set<Record*> &RegSet) {
102 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
103 Record *Reg = RC.Elements[i];
104 if (!RegSet.count(Reg))
110 static void addSubReg(Record *R, Record *S,
111 std::map<Record*, std::set<Record*> > &SubRegs,
112 std::map<Record*, std::set<Record*> > &Aliases,
113 RegisterInfoEmitter &RIE) {
115 cerr << "Error: recursive sub-register relationship between"
116 << " register " << RIE.getQualifiedName(R)
117 << " and its sub-registers?\n";
121 if (!SubRegs[R].insert(S).second)
123 Aliases[R].insert(S);
124 Aliases[S].insert(R);
125 if (SubRegs.count(S))
126 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
127 E = SubRegs[S].end(); I != E; ++I)
128 addSubReg(R, *I, SubRegs, Aliases, RIE);
131 // RegisterInfoEmitter::run - Main register file description emitter.
133 void RegisterInfoEmitter::run(std::ostream &OS) {
134 CodeGenTarget Target;
135 EmitSourceFileHeader("Register Information Source Fragment", OS);
137 OS << "namespace llvm {\n\n";
139 // Start out by emitting each of the register classes... to do this, we build
140 // a set of registers which belong to a register class, this is to ensure that
141 // each register is only in a single register class.
143 const std::vector<CodeGenRegisterClass> &RegisterClasses =
144 Target.getRegisterClasses();
146 // Loop over all of the register classes... emitting each one.
147 OS << "namespace { // Register classes...\n";
149 // RegClassesBelongedTo - Keep track of which register classes each reg
151 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
153 // Emit the register enum value arrays for each RegisterClass
154 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
155 const CodeGenRegisterClass &RC = RegisterClasses[rc];
157 // Give the register class a legal C name if it's anonymous.
158 std::string Name = RC.TheDef->getName();
160 // Emit the register list now.
161 OS << " // " << Name << " Register Class...\n"
162 << " static const unsigned " << Name
164 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
165 Record *Reg = RC.Elements[i];
166 OS << getQualifiedName(Reg) << ", ";
168 // Keep track of which regclasses this register is in.
169 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
174 // Emit the ValueType arrays for each RegisterClass
175 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
176 const CodeGenRegisterClass &RC = RegisterClasses[rc];
178 // Give the register class a legal C name if it's anonymous.
179 std::string Name = RC.TheDef->getName() + "VTs";
181 // Emit the register list now.
183 << " Register Class Value Types...\n"
184 << " static const MVT::ValueType " << Name
186 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
187 OS << RC.VTs[i] << ", ";
188 OS << "MVT::Other\n };\n\n";
190 OS << "} // end anonymous namespace\n\n";
192 // Now that all of the structs have been emitted, emit the instances.
193 if (!RegisterClasses.empty()) {
194 OS << "namespace " << RegisterClasses[0].Namespace
195 << " { // Register class instances\n";
196 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
197 OS << " " << RegisterClasses[i].getName() << "Class\t"
198 << RegisterClasses[i].getName() << "RegClass;\n";
200 std::map<unsigned, std::set<unsigned> > SuperClassMap;
202 // Emit the sub-classes array for each RegisterClass
203 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
204 const CodeGenRegisterClass &RC = RegisterClasses[rc];
206 // Give the register class a legal C name if it's anonymous.
207 std::string Name = RC.TheDef->getName();
209 std::set<Record*> RegSet;
210 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
211 Record *Reg = RC.Elements[i];
216 << " Register Class sub-classes...\n"
217 << " static const TargetRegisterClass* const "
218 << Name << "Subclasses [] = {\n ";
221 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
222 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
223 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
224 RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
227 if (!Empty) OS << ", ";
228 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
231 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
232 SuperClassMap.find(rc2);
233 if (SCMI == SuperClassMap.end()) {
234 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
235 SCMI = SuperClassMap.find(rc2);
237 SCMI->second.insert(rc);
240 OS << (!Empty ? ", " : "") << "NULL";
244 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
245 const CodeGenRegisterClass &RC = RegisterClasses[rc];
247 // Give the register class a legal C name if it's anonymous.
248 std::string Name = RC.TheDef->getName();
251 << " Register Class super-classes...\n"
252 << " static const TargetRegisterClass* const "
253 << Name << "Superclasses [] = {\n ";
256 std::map<unsigned, std::set<unsigned> >::iterator I =
257 SuperClassMap.find(rc);
258 if (I != SuperClassMap.end()) {
259 for (std::set<unsigned>::iterator II = I->second.begin(),
260 EE = I->second.end(); II != EE; ++II) {
261 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
262 if (!Empty) OS << ", ";
263 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
268 OS << (!Empty ? ", " : "") << "NULL";
273 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
274 const CodeGenRegisterClass &RC = RegisterClasses[i];
275 OS << RC.MethodBodies << "\n";
276 OS << RC.getName() << "Class::" << RC.getName()
277 << "Class() : TargetRegisterClass("
278 << RC.getName() + "RegClassID" << ", "
279 << RC.getName() + "VTs" << ", "
280 << RC.getName() + "Subclasses" << ", "
281 << RC.getName() + "Superclasses" << ", "
282 << RC.SpillSize/8 << ", "
283 << RC.SpillAlignment/8 << ", " << RC.getName() << ", "
284 << RC.getName() << " + " << RC.Elements.size() << ") {}\n";
290 OS << "\nnamespace {\n";
291 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
292 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
293 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
297 // Emit register sub-registers / aliases...
298 std::map<Record*, std::set<Record*> > RegisterSubRegs;
299 std::map<Record*, std::set<Record*> > RegisterAliases;
300 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
302 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
303 Record *R = Regs[i].TheDef;
304 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
305 // Add information that R aliases all of the elements in the list... and
306 // that everything in the list aliases R.
307 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
309 if (RegisterAliases[R].count(Reg))
310 cerr << "Warning: register alias between " << getQualifiedName(R)
311 << " and " << getQualifiedName(Reg)
312 << " specified multiple times!\n";
313 RegisterAliases[R].insert(Reg);
315 if (RegisterAliases[Reg].count(R))
316 cerr << "Warning: register alias between " << getQualifiedName(R)
317 << " and " << getQualifiedName(Reg)
318 << " specified multiple times!\n";
319 RegisterAliases[Reg].insert(R);
323 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
324 Record *R = Regs[i].TheDef;
325 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
326 // Process sub-register set and add aliases information.
327 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
328 Record *SubReg = LI[j];
329 if (RegisterSubRegs[R].count(SubReg))
330 cerr << "Warning: register " << getQualifiedName(SubReg)
331 << " specified as a sub-register of " << getQualifiedName(R)
332 << " multiple times!\n";
333 addSubReg(R, SubReg, RegisterSubRegs, RegisterAliases, *this);
337 if (!RegisterAliases.empty())
338 OS << "\n\n // Register Alias Sets...\n";
340 // Emit the empty alias list
341 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
342 // Loop over all of the registers which have aliases, emitting the alias list
344 for (std::map<Record*, std::set<Record*> >::iterator
345 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
346 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
347 for (std::set<Record*>::iterator ASI = I->second.begin(),
348 E = I->second.end(); ASI != E; ++ASI)
349 OS << getQualifiedName(*ASI) << ", ";
353 if (!RegisterSubRegs.empty())
354 OS << "\n\n // Register Sub-registers Sets...\n";
356 // Emit the empty sub-registers list
357 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
358 // Loop over all of the registers which have sub-registers, emitting the
359 // sub-registers list to memory.
360 for (std::map<Record*, std::set<Record*> >::iterator
361 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
362 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
363 for (std::set<Record*>::iterator ASI = I->second.begin(),
364 E = I->second.end(); ASI != E; ++ASI)
365 OS << getQualifiedName(*ASI) << ", ";
368 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
369 OS << " { \"NOREG\",\t0,\t0 },\n";
372 // Now that register alias and sub-registers sets have been emitted, emit the
373 // register descriptors now.
374 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
375 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
376 const CodeGenRegister &Reg = Registers[i];
378 if (!Reg.TheDef->getValueAsString("Name").empty())
379 OS << Reg.TheDef->getValueAsString("Name");
383 if (RegisterAliases.count(Reg.TheDef))
384 OS << Reg.getName() << "_AliasSet,\t";
386 OS << "Empty_AliasSet,\t";
387 if (RegisterSubRegs.count(Reg.TheDef))
388 OS << Reg.getName() << "_SubRegsSet },\n";
390 OS << "Empty_SubRegsSet },\n";
392 OS << " };\n"; // End of register descriptors...
393 OS << "}\n\n"; // End of anonymous namespace...
395 std::string ClassName = Target.getName() + "GenRegisterInfo";
397 // Emit the constructor of the class...
398 OS << ClassName << "::" << ClassName
399 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
400 << " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1
401 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
402 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
404 // Emit information about the dwarf register numbers.
405 OS << "int " << ClassName << "::getDwarfRegNum(unsigned RegNum) const {\n";
406 OS << " static const int DwarfRegNums[] = { -1, // NoRegister";
407 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
408 if (!(i % 16)) OS << "\n ";
409 const CodeGenRegister &Reg = Registers[i];
410 int DwarfRegNum = Reg.TheDef->getValueAsInt("DwarfNumber");
412 if ((i + 1) != e) OS << ", ";
415 OS << " assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) &&\n";
416 OS << " \"RegNum exceeds number of registers\");\n";
417 OS << " return DwarfRegNums[RegNum];\n";
420 OS << "} // End llvm namespace \n";