1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
19 #include "llvm/TableGen/Record.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/Support/Format.h"
28 // runEnums - Print out enum values for all of the registers.
30 RegisterInfoEmitter::runEnums(raw_ostream &OS,
31 CodeGenTarget &Target, CodeGenRegBank &Bank) {
32 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
34 // Register enums are stored as uint16_t in the tables. Make sure we'll fit
35 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
37 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
39 EmitSourceFileHeader("Target Register Enum Values", OS);
41 OS << "\n#ifdef GET_REGINFO_ENUM\n";
42 OS << "#undef GET_REGINFO_ENUM\n";
44 OS << "namespace llvm {\n\n";
46 OS << "class MCRegisterClass;\n"
47 << "extern const MCRegisterClass " << Namespace
48 << "MCRegisterClasses[];\n\n";
50 if (!Namespace.empty())
51 OS << "namespace " << Namespace << " {\n";
52 OS << "enum {\n NoRegister,\n";
54 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
55 OS << " " << Registers[i]->getName() << " = " <<
56 Registers[i]->EnumValue << ",\n";
57 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
58 "Register enum value mismatch!");
59 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
61 if (!Namespace.empty())
64 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
65 if (!RegisterClasses.empty()) {
67 // RegisterClass enums are stored as uint16_t in the tables.
68 assert(RegisterClasses.size() <= 0xffff &&
69 "Too many register classes to fit in tables");
71 OS << "\n// Register classes\n";
72 if (!Namespace.empty())
73 OS << "namespace " << Namespace << " {\n";
75 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
77 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
81 if (!Namespace.empty())
85 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
86 // If the only definition is the default NoRegAltName, we don't need to
88 if (RegAltNameIndices.size() > 1) {
89 OS << "\n// Register alternate name indices\n";
90 if (!Namespace.empty())
91 OS << "namespace " << Namespace << " {\n";
93 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
94 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
95 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
97 if (!Namespace.empty())
101 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
102 if (!SubRegIndices.empty()) {
103 OS << "\n// Subregister indices\n";
104 std::string Namespace =
105 SubRegIndices[0]->getNamespace();
106 if (!Namespace.empty())
107 OS << "namespace " << Namespace << " {\n";
108 OS << "enum {\n NoSubRegister,\n";
109 for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
110 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
111 OS << " NUM_TARGET_NAMED_SUBREGS\n};\n";
112 if (!Namespace.empty())
116 OS << "} // End llvm namespace \n";
117 OS << "#endif // GET_REGINFO_ENUM\n\n";
121 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
122 const std::vector<CodeGenRegister*> &Regs,
125 // Collect all information about dwarf register numbers
126 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
127 DwarfRegNumsMapTy DwarfRegNums;
129 // First, just pull all provided information to the map
130 unsigned maxLength = 0;
131 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
132 Record *Reg = Regs[i]->TheDef;
133 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
134 maxLength = std::max((size_t)maxLength, RegNums.size());
135 if (DwarfRegNums.count(Reg))
136 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
137 << "specified multiple times\n";
138 DwarfRegNums[Reg] = RegNums;
144 // Now we know maximal length of number list. Append -1's, where needed
145 for (DwarfRegNumsMapTy::iterator
146 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
147 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
148 I->second.push_back(-1);
150 // Emit reverse information about the dwarf register numbers.
151 for (unsigned j = 0; j < 2; ++j) {
154 OS << "DwarfFlavour";
159 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
161 for (unsigned i = 0, e = maxLength; i != e; ++i) {
162 OS << " case " << i << ":\n";
163 for (DwarfRegNumsMapTy::iterator
164 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
165 int DwarfRegNo = I->second[i];
171 OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
172 << getQualifiedName(I->first) << ", ";
184 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
185 Record *Reg = Regs[i]->TheDef;
186 const RecordVal *V = Reg->getValue("DwarfAlias");
187 if (!V || !V->getValue())
190 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
191 Record *Alias = DI->getDef();
192 DwarfRegNums[Reg] = DwarfRegNums[Alias];
195 // Emit information about the dwarf register numbers.
196 for (unsigned j = 0; j < 2; ++j) {
199 OS << "DwarfFlavour";
204 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
206 for (unsigned i = 0, e = maxLength; i != e; ++i) {
207 OS << " case " << i << ":\n";
208 // Sort by name to get a stable order.
209 for (DwarfRegNumsMapTy::iterator
210 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
211 int RegNo = I->second[i];
212 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
218 OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
232 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
233 // Width is the number of bits per hex number.
234 static void printBitVectorAsHex(raw_ostream &OS,
235 const BitVector &Bits,
237 assert(Width <= 32 && "Width too large");
238 unsigned Digits = (Width + 3) / 4;
239 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
241 for (unsigned j = 0; j != Width && i + j != e; ++j)
242 Value |= Bits.test(i + j) << j;
243 OS << format("0x%0*x, ", Digits, Value);
247 // Helper to emit a set of bits into a constant byte array.
248 class BitVectorEmitter {
251 void add(unsigned v) {
252 if (v >= Values.size())
253 Values.resize(((v/8)+1)*8); // Round up to the next byte.
257 void print(raw_ostream &OS) {
258 printBitVectorAsHex(OS, Values, 8);
263 // runMCDesc - Print out MC register descriptions.
266 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
267 CodeGenRegBank &RegBank) {
268 EmitSourceFileHeader("MC Register Information", OS);
270 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
271 OS << "#undef GET_REGINFO_MC_DESC\n";
273 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
274 RegBank.computeOverlaps(Overlaps);
276 OS << "namespace llvm {\n\n";
278 const std::string &TargetName = Target.getName();
280 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
282 OS << "extern const uint16_t " << TargetName << "RegOverlaps[] = {\n";
284 // Emit an overlap list for all registers.
285 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
286 const CodeGenRegister *Reg = Regs[i];
287 const CodeGenRegister::Set &O = Overlaps[Reg];
288 // Move Reg to the front so TRI::getAliasSet can share the list.
289 OS << " /* " << Reg->getName() << "_Overlaps */ "
290 << getQualifiedName(Reg->TheDef) << ", ";
291 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
294 OS << getQualifiedName((*I)->TheDef) << ", ";
299 OS << "extern const uint16_t " << TargetName << "SubRegsSet[] = {\n";
300 // Emit the empty sub-registers list
301 OS << " /* Empty_SubRegsSet */ 0,\n";
302 // Loop over all of the registers which have sub-registers, emitting the
303 // sub-registers list to memory.
304 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
305 const CodeGenRegister &Reg = *Regs[i];
306 if (Reg.getSubRegs().empty())
308 // getSubRegs() orders by SubRegIndex. We want a topological order.
309 SetVector<CodeGenRegister*> SR;
310 Reg.addSubRegsPreOrder(SR, RegBank);
311 OS << " /* " << Reg.getName() << "_SubRegsSet */ ";
312 for (unsigned j = 0, je = SR.size(); j != je; ++j)
313 OS << getQualifiedName(SR[j]->TheDef) << ", ";
318 OS << "extern const uint16_t " << TargetName << "SuperRegsSet[] = {\n";
319 // Emit the empty super-registers list
320 OS << " /* Empty_SuperRegsSet */ 0,\n";
321 // Loop over all of the registers which have super-registers, emitting the
322 // super-registers list to memory.
323 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
324 const CodeGenRegister &Reg = *Regs[i];
325 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
328 OS << " /* " << Reg.getName() << "_SuperRegsSet */ ";
329 for (unsigned j = 0, je = SR.size(); j != je; ++j)
330 OS << getQualifiedName(SR[j]->TheDef) << ", ";
335 OS << "extern const MCRegisterDesc " << TargetName
336 << "RegDesc[] = { // Descriptors\n";
337 OS << " { \"NOREG\", 0, 0, 0 },\n";
339 // Now that register alias and sub-registers sets have been emitted, emit the
340 // register descriptors now.
341 unsigned OverlapsIndex = 0;
342 unsigned SubRegIndex = 1; // skip 1 for empty set
343 unsigned SuperRegIndex = 1; // skip 1 for empty set
344 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
345 const CodeGenRegister *Reg = Regs[i];
347 OS << Reg->getName() << "\", /* " << Reg->getName() << "_Overlaps */ "
348 << OverlapsIndex << ", ";
349 OverlapsIndex += Overlaps[Reg].size() + 1;
350 if (!Reg->getSubRegs().empty()) {
351 OS << "/* " << Reg->getName() << "_SubRegsSet */ " << SubRegIndex
353 // FIXME not very nice to recalculate this
354 SetVector<CodeGenRegister*> SR;
355 Reg->addSubRegsPreOrder(SR, RegBank);
356 SubRegIndex += SR.size() + 1;
358 OS << "/* Empty_SubRegsSet */ 0, ";
359 if (!Reg->getSuperRegs().empty()) {
360 OS << "/* " << Reg->getName() << "_SuperRegsSet */ " << SuperRegIndex;
361 SuperRegIndex += Reg->getSuperRegs().size() + 1;
363 OS << "/* Empty_SuperRegsSet */ 0";
366 OS << "};\n\n"; // End of register descriptors...
368 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
370 // Loop over all of the register classes... emitting each one.
371 OS << "namespace { // Register classes...\n";
373 // Emit the register enum value arrays for each RegisterClass
374 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
375 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
376 ArrayRef<Record*> Order = RC.getOrder();
378 // Give the register class a legal C name if it's anonymous.
379 std::string Name = RC.getName();
381 // Emit the register list now.
382 OS << " // " << Name << " Register Class...\n"
383 << " const uint16_t " << Name
385 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
386 Record *Reg = Order[i];
387 OS << getQualifiedName(Reg) << ", ";
391 OS << " // " << Name << " Bit set.\n"
392 << " const uint8_t " << Name
394 BitVectorEmitter BVE;
395 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
396 Record *Reg = Order[i];
397 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
405 OS << "extern const MCRegisterClass " << TargetName
406 << "MCRegisterClasses[] = {\n";
408 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
409 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
411 // Asserts to make sure values will fit in table assuming types from
413 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
414 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
415 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
417 OS << " { " << '\"' << RC.getName() << "\", "
418 << RC.getName() << ", " << RC.getName() << "Bits, "
419 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
420 << RC.getQualifiedName() + "RegClassID" << ", "
421 << RC.SpillSize/8 << ", "
422 << RC.SpillAlignment/8 << ", "
423 << RC.CopyCost << ", "
424 << RC.Allocatable << " },\n";
429 // Emit the data table for getSubReg().
430 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
431 if (SubRegIndices.size()) {
432 OS << "const uint16_t " << TargetName << "SubRegTable[]["
433 << SubRegIndices.size() << "] = {\n";
434 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
435 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
436 OS << " /* " << Regs[i]->TheDef->getName() << " */\n";
442 for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
443 // FIXME: We really should keep this to 80 columns...
444 CodeGenRegister::SubRegMap::const_iterator SubReg =
445 SRM.find(SubRegIndices[j]);
446 if (SubReg != SRM.end())
447 OS << getQualifiedName(SubReg->second->TheDef);
453 OS << "}" << (i != e ? "," : "") << "\n";
456 OS << "const uint16_t *get" << TargetName
457 << "SubRegTable() {\n return (const uint16_t *)" << TargetName
458 << "SubRegTable;\n}\n\n";
461 // MCRegisterInfo initialization routine.
462 OS << "static inline void Init" << TargetName
463 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
464 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
465 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
466 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
467 << RegisterClasses.size() << ", " << TargetName << "RegOverlaps, "
468 << TargetName << "SubRegsSet, " << TargetName << "SuperRegsSet, ";
469 if (SubRegIndices.size() != 0)
470 OS << "(uint16_t*)" << TargetName << "SubRegTable, "
471 << SubRegIndices.size() << ");\n\n";
473 OS << "NULL, 0);\n\n";
475 EmitRegMapping(OS, Regs, false);
479 OS << "} // End llvm namespace \n";
480 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
484 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
485 CodeGenRegBank &RegBank) {
486 EmitSourceFileHeader("Register Information Header Fragment", OS);
488 OS << "\n#ifdef GET_REGINFO_HEADER\n";
489 OS << "#undef GET_REGINFO_HEADER\n";
491 const std::string &TargetName = Target.getName();
492 std::string ClassName = TargetName + "GenRegisterInfo";
494 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
495 OS << "#include <string>\n\n";
497 OS << "namespace llvm {\n\n";
499 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
500 << " explicit " << ClassName
501 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
502 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
503 << " { return false; }\n"
504 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
505 << " const TargetRegisterClass *"
506 "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
507 << " const TargetRegisterClass *getMatchingSuperRegClass("
508 "const TargetRegisterClass*, const TargetRegisterClass*, "
512 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
514 if (!RegisterClasses.empty()) {
515 OS << "namespace " << RegisterClasses[0]->Namespace
516 << " { // Register classes\n";
518 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
519 const CodeGenRegisterClass &RC = *RegisterClasses[i];
520 const std::string &Name = RC.getName();
522 // Output the extern for the instance.
523 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
524 // Output the extern for the pointer to the instance (should remove).
525 OS << " static const TargetRegisterClass * const " << Name
526 << "RegisterClass = &" << Name << "RegClass;\n";
528 OS << "} // end of namespace " << TargetName << "\n\n";
530 OS << "} // End llvm namespace \n";
531 OS << "#endif // GET_REGINFO_HEADER\n\n";
535 // runTargetDesc - Output the target register and register file descriptions.
538 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
539 CodeGenRegBank &RegBank){
540 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
542 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
543 OS << "#undef GET_REGINFO_TARGET_DESC\n";
545 OS << "namespace llvm {\n\n";
547 // Get access to MCRegisterClass data.
548 OS << "extern const MCRegisterClass " << Target.getName()
549 << "MCRegisterClasses[];\n";
551 // Start out by emitting each of the register classes.
552 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
554 // Collect all registers belonging to any allocatable class.
555 std::set<Record*> AllocatableRegs;
557 // Collect allocatable registers.
558 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
559 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
560 ArrayRef<Record*> Order = RC.getOrder();
563 AllocatableRegs.insert(Order.begin(), Order.end());
566 OS << "namespace { // Register classes...\n";
568 // Emit the ValueType arrays for each RegisterClass
569 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
570 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
572 // Give the register class a legal C name if it's anonymous.
573 std::string Name = RC.getName() + "VTs";
575 // Emit the register list now.
577 << " Register Class Value Types...\n"
578 << " const MVT::SimpleValueType " << Name
580 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
581 OS << getEnumName(RC.VTs[i]) << ", ";
582 OS << "MVT::Other\n };\n\n";
584 OS << "} // end anonymous namespace\n\n";
586 // Now that all of the structs have been emitted, emit the instances.
587 if (!RegisterClasses.empty()) {
588 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
590 OS << "\nstatic const TargetRegisterClass *const "
591 << "NullRegClasses[] = { NULL };\n\n";
593 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
595 if (NumSubRegIndices) {
596 // Compute the super-register classes for each RegisterClass
597 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
598 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
599 for (DenseMap<Record*,Record*>::const_iterator
600 i = RC.SubRegClasses.begin(),
601 e = RC.SubRegClasses.end(); i != e; ++i) {
602 // Find the register class number of i->second for SuperRegClassMap.
603 const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
604 assert(RC2 && "Invalid register class in SubRegClasses");
605 SuperRegClassMap[RC2->EnumValue].insert(rc);
609 // Emit the super-register classes for each RegisterClass
610 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
611 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
613 // Give the register class a legal C name if it's anonymous.
614 std::string Name = RC.getName();
617 << " Super-register Classes...\n"
618 << "static const TargetRegisterClass *const "
619 << Name << "SuperRegClasses[] = {\n ";
622 std::map<unsigned, std::set<unsigned> >::iterator I =
623 SuperRegClassMap.find(rc);
624 if (I != SuperRegClassMap.end()) {
625 for (std::set<unsigned>::iterator II = I->second.begin(),
626 EE = I->second.end(); II != EE; ++II) {
627 const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
630 OS << "&" << RC2.getQualifiedName() << "RegClass";
635 OS << (!Empty ? ", " : "") << "NULL";
640 // Emit the sub-classes array for each RegisterClass
641 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
642 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
644 // Give the register class a legal C name if it's anonymous.
645 std::string Name = RC.getName();
647 OS << "static const uint32_t " << Name << "SubclassMask[] = {\n ";
648 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
652 // Emit NULL terminated super-class lists.
653 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
654 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
655 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
657 // Skip classes without supers. We can reuse NullRegClasses.
661 OS << "static const TargetRegisterClass *const "
662 << RC.getName() << "Superclasses[] = {\n";
663 for (unsigned i = 0; i != Supers.size(); ++i)
664 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
665 OS << " NULL\n};\n\n";
669 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
670 const CodeGenRegisterClass &RC = *RegisterClasses[i];
671 if (!RC.AltOrderSelect.empty()) {
672 OS << "\nstatic inline unsigned " << RC.getName()
673 << "AltOrderSelect(const MachineFunction &MF) {"
674 << RC.AltOrderSelect << "}\n\n"
675 << "static ArrayRef<uint16_t> " << RC.getName()
676 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
677 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
678 ArrayRef<Record*> Elems = RC.getOrder(oi);
679 if (!Elems.empty()) {
680 OS << " static const uint16_t AltOrder" << oi << "[] = {";
681 for (unsigned elem = 0; elem != Elems.size(); ++elem)
682 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
686 OS << " const MCRegisterClass &MCR = " << Target.getName()
687 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
688 << " const ArrayRef<uint16_t> Order[] = {\n"
689 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
690 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
691 if (RC.getOrder(oi).empty())
692 OS << "),\n ArrayRef<uint16_t>(";
694 OS << "),\n makeArrayRef(AltOrder" << oi;
695 OS << ")\n };\n const unsigned Select = " << RC.getName()
696 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
697 << ");\n return Order[Select];\n}\n";
701 // Now emit the actual value-initialized register class instances.
702 OS << "namespace " << RegisterClasses[0]->Namespace
703 << " { // Register class instances\n";
705 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
706 const CodeGenRegisterClass &RC = *RegisterClasses[i];
707 OS << " extern const TargetRegisterClass "
708 << RegisterClasses[i]->getName() << "RegClass = {\n "
709 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
711 << RC.getName() << "VTs,\n "
712 << RC.getName() << "SubclassMask,\n ";
713 if (RC.getSuperClasses().empty())
714 OS << "NullRegClasses,\n ";
716 OS << RC.getName() << "Superclasses,\n ";
717 OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
719 if (RC.AltOrderSelect.empty())
722 OS << RC.getName() << "GetRawAllocationOrder\n";
729 OS << "\nnamespace {\n";
730 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
731 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
732 OS << " &" << RegisterClasses[i]->getQualifiedName()
735 OS << "}\n"; // End of anonymous namespace...
737 // Emit extra information about registers.
738 const std::string &TargetName = Target.getName();
739 OS << "\n static const TargetRegisterInfoDesc "
740 << TargetName << "RegInfoDesc[] = "
741 << "{ // Extra Descriptors\n";
742 OS << " { 0, 0 },\n";
744 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
745 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
746 const CodeGenRegister &Reg = *Regs[i];
748 OS << Reg.CostPerUse << ", "
749 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
751 OS << " };\n"; // End of register descriptors...
754 // Calculate the mapping of subregister+index pairs to physical registers.
755 // This will also create further anonymous indices.
756 unsigned NamedIndices = RegBank.getNumNamedIndices();
758 // Emit SubRegIndex names, skipping 0
759 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
760 OS << "\n static const char *const " << TargetName
761 << "SubRegIndexTable[] = { \"";
762 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
763 OS << SubRegIndices[i]->getName();
769 // Emit names of the anonymous subreg indices.
770 if (SubRegIndices.size() > NamedIndices) {
772 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
773 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
781 std::string ClassName = Target.getName() + "GenRegisterInfo";
783 // Emit composeSubRegIndices
784 OS << "unsigned " << ClassName
785 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
786 << " switch (IdxA) {\n"
787 << " default:\n return IdxB;\n";
788 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
790 for (unsigned j = 0; j != e; ++j) {
791 if (CodeGenSubRegIndex *Comp =
792 SubRegIndices[i]->compose(SubRegIndices[j])) {
794 OS << " case " << SubRegIndices[i]->getQualifiedName()
795 << ": switch(IdxB) {\n default: return IdxB;\n";
798 OS << " case " << SubRegIndices[j]->getQualifiedName()
799 << ": return " << Comp->getQualifiedName() << ";\n";
807 // Emit getSubClassWithSubReg.
808 OS << "const TargetRegisterClass *" << ClassName
809 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
811 if (SubRegIndices.empty()) {
812 OS << " assert(Idx == 0 && \"Target has no sub-registers\");\n"
815 // Use the smallest type that can hold a regclass ID with room for a
817 if (RegisterClasses.size() < UINT8_MAX)
818 OS << " static const uint8_t Table[";
819 else if (RegisterClasses.size() < UINT16_MAX)
820 OS << " static const uint16_t Table[";
822 throw "Too many register classes.";
823 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
824 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
825 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
826 OS << " {\t// " << RC.getName() << "\n";
827 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
828 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
829 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
830 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
831 << " -> " << SRC->getName() << "\n";
833 OS << " 0,\t// " << Idx->getName() << "\n";
837 OS << " };\n assert(RC && \"Missing regclass\");\n"
838 << " if (!Idx) return RC;\n --Idx;\n"
839 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
840 << " unsigned TV = Table[RC->getID()][Idx];\n"
841 << " return TV ? getRegClass(TV - 1) : 0;\n";
845 // Emit getMatchingSuperRegClass.
846 OS << "const TargetRegisterClass *" << ClassName
847 << "::getMatchingSuperRegClass(const TargetRegisterClass *A,"
848 " const TargetRegisterClass *B, unsigned Idx) const {\n";
849 if (SubRegIndices.empty()) {
850 OS << " llvm_unreachable(\"Target has no sub-registers\");\n";
852 // We need to find the largest sub-class of A such that every register has
853 // an Idx sub-register in B. Map (B, Idx) to a bit-vector of
854 // super-register classes that map into B. Then compute the largest common
855 // sub-class with A by taking advantage of the register class ordering,
856 // like getCommonSubClass().
858 // Bitvector table is NumRCs x NumSubIndexes x BVWords, where BVWords is
859 // the number of 32-bit words required to represent all register classes.
860 const unsigned BVWords = (RegisterClasses.size()+31)/32;
861 BitVector BV(RegisterClasses.size());
863 OS << " static const uint32_t Table[" << RegisterClasses.size()
864 << "][" << SubRegIndices.size() << "][" << BVWords << "] = {\n";
865 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
866 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
867 OS << " {\t// " << RC.getName() << "\n";
868 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
869 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
871 RC.getSuperRegClasses(Idx, BV);
873 printBitVectorAsHex(OS, BV, 32);
874 OS << "},\t// " << Idx->getName() << '\n';
878 OS << " };\n assert(A && B && \"Missing regclass\");\n"
880 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
881 << " const uint32_t *TV = Table[B->getID()][Idx];\n"
882 << " const uint32_t *SC = A->getSubClassMask();\n"
883 << " for (unsigned i = 0; i != " << BVWords << "; ++i)\n"
884 << " if (unsigned Common = TV[i] & SC[i])\n"
885 << " return getRegClass(32*i + CountTrailingZeros_32(Common));\n"
890 // Emit the constructor of the class...
891 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
892 OS << "extern const uint16_t " << TargetName << "RegOverlaps[];\n";
893 OS << "extern const uint16_t " << TargetName << "SubRegsSet[];\n";
894 OS << "extern const uint16_t " << TargetName << "SuperRegsSet[];\n";
895 if (SubRegIndices.size() != 0)
896 OS << "extern const uint16_t *get" << TargetName
897 << "SubRegTable();\n";
899 OS << ClassName << "::\n" << ClassName
900 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
901 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
902 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
903 << " " << TargetName << "SubRegIndexTable) {\n"
904 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
905 << Regs.size()+1 << ", RA,\n " << TargetName
906 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
907 << " " << TargetName << "RegOverlaps, "
908 << TargetName << "SubRegsSet, " << TargetName << "SuperRegsSet,\n"
910 if (SubRegIndices.size() != 0)
911 OS << "get" << TargetName << "SubRegTable(), "
912 << SubRegIndices.size() << ");\n\n";
914 OS << "NULL, 0);\n\n";
916 EmitRegMapping(OS, Regs, true);
921 // Emit CalleeSavedRegs information.
922 std::vector<Record*> CSRSets =
923 Records.getAllDerivedDefinitions("CalleeSavedRegs");
924 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
925 Record *CSRSet = CSRSets[i];
926 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
927 assert(Regs && "Cannot expand CalleeSavedRegs instance");
929 // Emit the *_SaveList list of callee-saved registers.
930 OS << "static const uint16_t " << CSRSet->getName()
931 << "_SaveList[] = { ";
932 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
933 OS << getQualifiedName((*Regs)[r]) << ", ";
936 // Emit the *_RegMask bit mask of call-preserved registers.
937 OS << "static const uint32_t " << CSRSet->getName()
938 << "_RegMask[] = { ";
939 printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
944 OS << "} // End llvm namespace \n";
945 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
948 void RegisterInfoEmitter::run(raw_ostream &OS) {
949 CodeGenTarget Target(Records);
950 CodeGenRegBank &RegBank = Target.getRegBank();
951 RegBank.computeDerivedInfo();
953 runEnums(OS, Target, RegBank);
954 runMCDesc(OS, Target, RegBank);
955 runTargetHeader(OS, Target, RegBank);
956 runTargetDesc(OS, Target, RegBank);