1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "CodeGenRegisters.h"
17 #include "CodeGenTarget.h"
18 #include "SequenceToOffsetTable.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/Support/Format.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
33 class RegisterInfoEmitter {
34 RecordKeeper &Records;
36 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
38 // runEnums - Print out enum values for all of the registers.
39 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
41 // runMCDesc - Print out MC register descriptions.
42 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
44 // runTargetHeader - Emit a header fragment for the register info emitter.
45 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
46 CodeGenRegBank &Bank);
48 // runTargetDesc - Output the target register and register file descriptions.
49 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
50 CodeGenRegBank &Bank);
52 // run - Output the register file description.
53 void run(raw_ostream &o);
56 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
58 void EmitRegMappingTables(raw_ostream &o,
59 const std::deque<CodeGenRegister> &Regs,
61 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
62 const std::string &ClassName);
63 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
64 const std::string &ClassName);
66 } // End anonymous namespace
68 // runEnums - Print out enum values for all of the registers.
69 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
70 CodeGenTarget &Target, CodeGenRegBank &Bank) {
71 const auto &Registers = Bank.getRegisters();
73 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
74 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
76 std::string Namespace =
77 Registers.front().TheDef->getValueAsString("Namespace");
79 emitSourceFileHeader("Target Register Enum Values", OS);
81 OS << "\n#ifdef GET_REGINFO_ENUM\n";
82 OS << "#undef GET_REGINFO_ENUM\n";
84 OS << "namespace llvm {\n\n";
86 OS << "class MCRegisterClass;\n"
87 << "extern const MCRegisterClass " << Namespace
88 << "MCRegisterClasses[];\n\n";
90 if (!Namespace.empty())
91 OS << "namespace " << Namespace << " {\n";
92 OS << "enum {\n NoRegister,\n";
94 for (const auto &Reg : Registers)
95 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
96 assert(Registers.size() == Registers.back().EnumValue &&
97 "Register enum value mismatch!");
98 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
100 if (!Namespace.empty())
103 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
104 if (!RegisterClasses.empty()) {
106 // RegisterClass enums are stored as uint16_t in the tables.
107 assert(RegisterClasses.size() <= 0xffff &&
108 "Too many register classes to fit in tables");
110 OS << "\n// Register classes\n";
111 if (!Namespace.empty())
112 OS << "namespace " << Namespace << " {\n";
114 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
116 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
120 if (!Namespace.empty())
124 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
125 // If the only definition is the default NoRegAltName, we don't need to
127 if (RegAltNameIndices.size() > 1) {
128 OS << "\n// Register alternate name indices\n";
129 if (!Namespace.empty())
130 OS << "namespace " << Namespace << " {\n";
132 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
133 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
134 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
136 if (!Namespace.empty())
140 auto &SubRegIndices = Bank.getSubRegIndices();
141 if (!SubRegIndices.empty()) {
142 OS << "\n// Subregister indices\n";
143 std::string Namespace = SubRegIndices.front().getNamespace();
144 if (!Namespace.empty())
145 OS << "namespace " << Namespace << " {\n";
146 OS << "enum {\n NoSubRegister,\n";
148 for (const auto &Idx : SubRegIndices)
149 OS << " " << Idx.getName() << ",\t// " << ++i << "\n";
150 OS << " NUM_TARGET_SUBREGS\n};\n";
151 if (!Namespace.empty())
155 OS << "} // End llvm namespace\n";
156 OS << "#endif // GET_REGINFO_ENUM\n\n";
159 static void printInt(raw_ostream &OS, int Val) {
163 static const char *getMinimalTypeForRange(uint64_t Range) {
164 assert(Range < 0xFFFFFFFFULL && "Enum too large");
172 void RegisterInfoEmitter::
173 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
174 const std::string &ClassName) {
175 unsigned NumRCs = RegBank.getRegClasses().size();
176 unsigned NumSets = RegBank.getNumRegPressureSets();
178 OS << "/// Get the weight in units of pressure for this register class.\n"
179 << "const RegClassWeight &" << ClassName << "::\n"
180 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
181 << " static const RegClassWeight RCWeightTable[] = {\n";
182 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
183 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
184 const CodeGenRegister::Set &Regs = RC.getMembers();
188 std::vector<unsigned> RegUnits;
189 RC.buildRegUnitSet(RegUnits);
190 OS << " {" << (*Regs.begin())->getWeight(RegBank)
191 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
193 OS << "}, \t// " << RC.getName() << "\n";
196 << " return RCWeightTable[RC->getID()];\n"
199 // Reasonable targets (not ARMv7) have unit weight for all units, so don't
200 // bother generating a table.
201 bool RegUnitsHaveUnitWeight = true;
202 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
203 UnitIdx < UnitEnd; ++UnitIdx) {
204 if (RegBank.getRegUnit(UnitIdx).Weight > 1)
205 RegUnitsHaveUnitWeight = false;
207 OS << "/// Get the weight in units of pressure for this register unit.\n"
208 << "unsigned " << ClassName << "::\n"
209 << "getRegUnitWeight(unsigned RegUnit) const {\n"
210 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
211 << " && \"invalid register unit\");\n";
212 if (!RegUnitsHaveUnitWeight) {
213 OS << " static const uint8_t RUWeightTable[] = {\n ";
214 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
215 UnitIdx < UnitEnd; ++UnitIdx) {
216 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
217 assert(RU.Weight < 256 && "RegUnit too heavy");
218 OS << RU.Weight << ", ";
221 << " return RUWeightTable[RegUnit];\n";
224 OS << " // All register units have unit weight.\n"
230 << "// Get the number of dimensions of register pressure.\n"
231 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
232 << " return " << NumSets << ";\n}\n\n";
234 OS << "// Get the name of this register unit pressure set.\n"
235 << "const char *" << ClassName << "::\n"
236 << "getRegPressureSetName(unsigned Idx) const {\n"
237 << " static const char *PressureNameTable[] = {\n";
238 unsigned MaxRegUnitWeight = 0;
239 for (unsigned i = 0; i < NumSets; ++i ) {
240 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
241 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight);
242 OS << " \"" << RegUnits.Name << "\",\n";
244 OS << " nullptr };\n"
245 << " return PressureNameTable[Idx];\n"
248 OS << "// Get the register unit pressure limit for this dimension.\n"
249 << "// This limit must be adjusted dynamically for reserved registers.\n"
250 << "unsigned " << ClassName << "::\n"
251 << "getRegPressureSetLimit(unsigned Idx) const {\n"
252 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight)
253 << " PressureLimitTable[] = {\n";
254 for (unsigned i = 0; i < NumSets; ++i ) {
255 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
256 OS << " " << RegUnits.Weight << ", \t// " << i << ": "
257 << RegUnits.Name << "\n";
260 << " return PressureLimitTable[Idx];\n"
263 SequenceToOffsetTable<std::vector<int>> PSetsSeqs;
265 // This table may be larger than NumRCs if some register units needed a list
266 // of unit sets that did not correspond to a register class.
267 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
268 std::vector<std::vector<int>> PSets(NumRCUnitSets);
270 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) {
271 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
272 PSets[i].reserve(PSetIDs.size());
273 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
274 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
275 PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order);
277 std::sort(PSets[i].begin(), PSets[i].end());
278 PSetsSeqs.add(PSets[i]);
283 OS << "/// Table of pressure sets per register class or unit.\n"
284 << "static const int RCSetsTable[] = {\n";
285 PSetsSeqs.emit(OS, printInt, "-1");
288 OS << "/// Get the dimensions of register pressure impacted by this "
289 << "register class.\n"
290 << "/// Returns a -1 terminated array of pressure set IDs\n"
291 << "const int* " << ClassName << "::\n"
292 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
293 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
294 << " RCSetStartTable[] = {\n ";
295 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
296 OS << PSetsSeqs.get(PSets[i]) << ",";
299 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"
302 OS << "/// Get the dimensions of register pressure impacted by this "
303 << "register unit.\n"
304 << "/// Returns a -1 terminated array of pressure set IDs\n"
305 << "const int* " << ClassName << "::\n"
306 << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
307 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
308 << " && \"invalid register unit\");\n";
309 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
310 << " RUSetStartTable[] = {\n ";
311 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
312 UnitIdx < UnitEnd; ++UnitIdx) {
313 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])
317 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n"
321 void RegisterInfoEmitter::EmitRegMappingTables(
322 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
323 // Collect all information about dwarf register numbers
324 typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy;
325 DwarfRegNumsMapTy DwarfRegNums;
327 // First, just pull all provided information to the map
328 unsigned maxLength = 0;
329 for (auto &RE : Regs) {
330 Record *Reg = RE.TheDef;
331 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
332 maxLength = std::max((size_t)maxLength, RegNums.size());
333 if (DwarfRegNums.count(Reg))
334 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
335 getQualifiedName(Reg) + "specified multiple times");
336 DwarfRegNums[Reg] = RegNums;
342 // Now we know maximal length of number list. Append -1's, where needed
343 for (DwarfRegNumsMapTy::iterator
344 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
345 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
346 I->second.push_back(-1);
348 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
350 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
352 // Emit reverse information about the dwarf register numbers.
353 for (unsigned j = 0; j < 2; ++j) {
354 for (unsigned i = 0, e = maxLength; i != e; ++i) {
355 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
356 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
357 OS << i << "Dwarf2L[]";
362 // Store the mapping sorted by the LLVM reg num so lookup can be done
363 // with a binary search.
364 std::map<uint64_t, Record*> Dwarf2LMap;
365 for (DwarfRegNumsMapTy::iterator
366 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
367 int DwarfRegNo = I->second[i];
370 Dwarf2LMap[DwarfRegNo] = I->first;
373 for (std::map<uint64_t, Record*>::iterator
374 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
375 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
383 // We have to store the size in a const global, it's used in multiple
385 OS << "extern const unsigned " << Namespace
386 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
388 OS << " = array_lengthof(" << Namespace
389 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
396 for (auto &RE : Regs) {
397 Record *Reg = RE.TheDef;
398 const RecordVal *V = Reg->getValue("DwarfAlias");
399 if (!V || !V->getValue())
402 DefInit *DI = cast<DefInit>(V->getValue());
403 Record *Alias = DI->getDef();
404 DwarfRegNums[Reg] = DwarfRegNums[Alias];
407 // Emit information about the dwarf register numbers.
408 for (unsigned j = 0; j < 2; ++j) {
409 for (unsigned i = 0, e = maxLength; i != e; ++i) {
410 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
411 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
412 OS << i << "L2Dwarf[]";
415 // Store the mapping sorted by the Dwarf reg num so lookup can be done
416 // with a binary search.
417 for (DwarfRegNumsMapTy::iterator
418 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
419 int RegNo = I->second[i];
420 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
423 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
431 // We have to store the size in a const global, it's used in multiple
433 OS << "extern const unsigned " << Namespace
434 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
436 OS << " = array_lengthof(" << Namespace
437 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";
444 void RegisterInfoEmitter::EmitRegMapping(
445 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
446 // Emit the initializer so the tables from EmitRegMappingTables get wired up
447 // to the MCRegisterInfo object.
448 unsigned maxLength = 0;
449 for (auto &RE : Regs) {
450 Record *Reg = RE.TheDef;
451 maxLength = std::max((size_t)maxLength,
452 Reg->getValueAsListOfInts("DwarfNumbers").size());
458 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
460 // Emit reverse information about the dwarf register numbers.
461 for (unsigned j = 0; j < 2; ++j) {
464 OS << "DwarfFlavour";
469 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
471 for (unsigned i = 0, e = maxLength; i != e; ++i) {
472 OS << " case " << i << ":\n";
477 raw_string_ostream(Tmp) << Namespace
478 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
480 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
491 // Emit information about the dwarf register numbers.
492 for (unsigned j = 0; j < 2; ++j) {
495 OS << "DwarfFlavour";
500 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
502 for (unsigned i = 0, e = maxLength; i != e; ++i) {
503 OS << " case " << i << ":\n";
508 raw_string_ostream(Tmp) << Namespace
509 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
511 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
523 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
524 // Width is the number of bits per hex number.
525 static void printBitVectorAsHex(raw_ostream &OS,
526 const BitVector &Bits,
528 assert(Width <= 32 && "Width too large");
529 unsigned Digits = (Width + 3) / 4;
530 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
532 for (unsigned j = 0; j != Width && i + j != e; ++j)
533 Value |= Bits.test(i + j) << j;
534 OS << format("0x%0*x, ", Digits, Value);
538 // Helper to emit a set of bits into a constant byte array.
539 class BitVectorEmitter {
542 void add(unsigned v) {
543 if (v >= Values.size())
544 Values.resize(((v/8)+1)*8); // Round up to the next byte.
548 void print(raw_ostream &OS) {
549 printBitVectorAsHex(OS, Values, 8);
553 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
554 OS << getEnumName(VT);
557 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
558 OS << Idx->EnumValue;
561 // Differentially encoded register and regunit lists allow for better
562 // compression on regular register banks. The sequence is computed from the
563 // differential list as:
566 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
568 // The initial value depends on the specific list. The list is terminated by a
569 // 0 differential which means we can't encode repeated elements.
571 typedef SmallVector<uint16_t, 4> DiffVec;
573 // Differentially encode a sequence of numbers into V. The starting value and
574 // terminating 0 are not added to V, so it will have the same size as List.
576 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) {
577 assert(V.empty() && "Clear DiffVec before diffEncode.");
578 uint16_t Val = uint16_t(InitVal);
579 for (unsigned i = 0; i != List.size(); ++i) {
580 uint16_t Cur = List[i];
581 V.push_back(Cur - Val);
587 template<typename Iter>
589 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {
590 assert(V.empty() && "Clear DiffVec before diffEncode.");
591 uint16_t Val = uint16_t(InitVal);
592 for (Iter I = Begin; I != End; ++I) {
593 uint16_t Cur = (*I)->EnumValue;
594 V.push_back(Cur - Val);
600 static void printDiff16(raw_ostream &OS, uint16_t Val) {
604 // Try to combine Idx's compose map into Vec if it is compatible.
605 // Return false if it's not possible.
606 static bool combine(const CodeGenSubRegIndex *Idx,
607 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) {
608 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();
609 for (CodeGenSubRegIndex::CompMap::const_iterator
610 I = Map.begin(), E = Map.end(); I != E; ++I) {
611 CodeGenSubRegIndex *&Entry = Vec[I->first->EnumValue - 1];
612 if (Entry && Entry != I->second)
616 // All entries are compatible. Make it so.
617 for (CodeGenSubRegIndex::CompMap::const_iterator
618 I = Map.begin(), E = Map.end(); I != E; ++I)
619 Vec[I->first->EnumValue - 1] = I->second;
624 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
625 CodeGenRegBank &RegBank,
626 const std::string &ClName) {
627 const auto &SubRegIndices = RegBank.getSubRegIndices();
628 OS << "unsigned " << ClName
629 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
631 // Many sub-register indexes are composition-compatible, meaning that
633 // compose(IdxA, IdxB) == compose(IdxA', IdxB)
635 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.
636 // The illegal entries can be use as wildcards to compress the table further.
638 // Map each Sub-register index to a compatible table row.
639 SmallVector<unsigned, 4> RowMap;
640 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows;
642 auto SubRegIndicesSize =
643 std::distance(SubRegIndices.begin(), SubRegIndices.end());
644 for (const auto &Idx : SubRegIndices) {
645 unsigned Found = ~0u;
646 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
647 if (combine(&Idx, Rows[r])) {
654 Rows.resize(Found + 1);
655 Rows.back().resize(SubRegIndicesSize);
656 combine(&Idx, Rows.back());
658 RowMap.push_back(Found);
661 // Output the row map if there is multiple rows.
662 if (Rows.size() > 1) {
663 OS << " static const " << getMinimalTypeForRange(Rows.size()) << " RowMap["
664 << SubRegIndicesSize << "] = {\n ";
665 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
666 OS << RowMap[i] << ", ";
671 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1)
672 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n";
673 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
675 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
677 OS << Rows[r][i]->EnumValue << ", ";
684 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n"
685 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";
687 OS << " return Rows[RowMap[IdxA]][IdxB];\n";
689 OS << " return Rows[0][IdxB];\n";
694 // runMCDesc - Print out MC register descriptions.
697 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
698 CodeGenRegBank &RegBank) {
699 emitSourceFileHeader("MC Register Information", OS);
701 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
702 OS << "#undef GET_REGINFO_MC_DESC\n";
704 const auto &Regs = RegBank.getRegisters();
706 auto &SubRegIndices = RegBank.getSubRegIndices();
707 // The lists of sub-registers and super-registers go in the same array. That
708 // allows us to share suffixes.
709 typedef std::vector<const CodeGenRegister*> RegVec;
711 // Differentially encoded lists.
712 SequenceToOffsetTable<DiffVec> DiffSeqs;
713 SmallVector<DiffVec, 4> SubRegLists(Regs.size());
714 SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
715 SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
716 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
718 // Keep track of sub-register names as well. These are not differentially
720 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
721 SequenceToOffsetTable<SubRegIdxVec, CodeGenSubRegIndex::Less> SubRegIdxSeqs;
722 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
724 SequenceToOffsetTable<std::string> RegStrings;
726 // Precompute register lists for the SequenceToOffsetTable.
728 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
729 const auto &Reg = *I;
730 RegStrings.add(Reg.getName());
732 // Compute the ordered sub-register list.
733 SetVector<const CodeGenRegister*> SR;
734 Reg.addSubRegsPreOrder(SR, RegBank);
735 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end());
736 DiffSeqs.add(SubRegLists[i]);
738 // Compute the corresponding sub-register indexes.
739 SubRegIdxVec &SRIs = SubRegIdxLists[i];
740 for (unsigned j = 0, je = SR.size(); j != je; ++j)
741 SRIs.push_back(Reg.getSubRegIndex(SR[j]));
742 SubRegIdxSeqs.add(SRIs);
744 // Super-registers are already computed.
745 const RegVec &SuperRegList = Reg.getSuperRegs();
746 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(),
748 DiffSeqs.add(SuperRegLists[i]);
750 // Differentially encode the register unit list, seeded by register number.
751 // First compute a scale factor that allows more diff-lists to be reused:
756 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
757 // value for the differential decoder is the register number multiplied by
760 // Check the neighboring registers for arithmetic progressions.
761 unsigned ScaleA = ~0u, ScaleB = ~0u;
762 ArrayRef<unsigned> RUs = Reg.getNativeRegUnits();
763 if (I != Regs.begin() &&
764 std::prev(I)->getNativeRegUnits().size() == RUs.size())
765 ScaleB = RUs.front() - std::prev(I)->getNativeRegUnits().front();
766 if (std::next(I) != Regs.end() &&
767 std::next(I)->getNativeRegUnits().size() == RUs.size())
768 ScaleA = std::next(I)->getNativeRegUnits().front() - RUs.front();
769 unsigned Scale = std::min(ScaleB, ScaleA);
770 // Default the scale to 0 if it can't be encoded in 4 bits.
773 RegUnitInitScale[i] = Scale;
774 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs));
778 // Compute the final layout of the sequence table.
780 SubRegIdxSeqs.layout();
782 OS << "namespace llvm {\n\n";
784 const std::string &TargetName = Target.getName();
786 // Emit the shared table of differential lists.
787 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
788 DiffSeqs.emit(OS, printDiff16);
791 // Emit the table of sub-register indexes.
792 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
793 SubRegIdxSeqs.emit(OS, printSubRegIndex);
796 // Emit the table of sub-register index sizes.
797 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
798 << TargetName << "SubRegIdxRanges[] = {\n";
799 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
800 for (const auto &Idx : SubRegIndices) {
801 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// "
802 << Idx.getName() << "\n";
806 // Emit the string table.
808 OS << "extern const char " << TargetName << "RegStrings[] = {\n";
809 RegStrings.emit(OS, printChar);
812 OS << "extern const MCRegisterDesc " << TargetName
813 << "RegDesc[] = { // Descriptors\n";
814 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n";
816 // Emit the register descriptors now.
818 for (const auto &Reg : Regs) {
819 OS << " { " << RegStrings.get(Reg.getName()) << ", "
820 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i])
821 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
822 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << " },\n";
825 OS << "};\n\n"; // End of register descriptors...
827 // Emit the table of register unit roots. Each regunit has one or two root
829 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
830 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
831 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
832 assert(!Roots.empty() && "All regunits must have a root register.");
833 assert(Roots.size() <= 2 && "More than two roots not supported yet.");
834 OS << " { " << getQualifiedName(Roots.front()->TheDef);
835 for (unsigned r = 1; r != Roots.size(); ++r)
836 OS << ", " << getQualifiedName(Roots[r]->TheDef);
841 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
843 // Loop over all of the register classes... emitting each one.
844 OS << "namespace { // Register classes...\n";
846 SequenceToOffsetTable<std::string> RegClassStrings;
848 // Emit the register enum value arrays for each RegisterClass
849 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
850 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
851 ArrayRef<Record*> Order = RC.getOrder();
853 // Give the register class a legal C name if it's anonymous.
854 std::string Name = RC.getName();
856 RegClassStrings.add(Name);
858 // Emit the register list now.
859 OS << " // " << Name << " Register Class...\n"
860 << " const MCPhysReg " << Name
862 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
863 Record *Reg = Order[i];
864 OS << getQualifiedName(Reg) << ", ";
868 OS << " // " << Name << " Bit set.\n"
869 << " const uint8_t " << Name
871 BitVectorEmitter BVE;
872 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
873 Record *Reg = Order[i];
874 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
882 RegClassStrings.layout();
883 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n";
884 RegClassStrings.emit(OS, printChar);
887 OS << "extern const MCRegisterClass " << TargetName
888 << "MCRegisterClasses[] = {\n";
890 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
891 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
893 // Asserts to make sure values will fit in table assuming types from
895 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
896 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
897 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
899 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, "
900 << RegClassStrings.get(RC.getName()) << ", "
901 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
902 << RC.getQualifiedName() + "RegClassID" << ", "
903 << RC.SpillSize/8 << ", "
904 << RC.SpillAlignment/8 << ", "
905 << RC.CopyCost << ", "
906 << RC.Allocatable << " },\n";
911 EmitRegMappingTables(OS, Regs, false);
913 // Emit Reg encoding table
914 OS << "extern const uint16_t " << TargetName;
915 OS << "RegEncodingTable[] = {\n";
916 // Add entry for NoRegister
918 for (const auto &RE : Regs) {
919 Record *Reg = RE.TheDef;
920 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
922 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
923 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
924 Value |= (uint64_t)B->getValue() << b;
926 OS << " " << Value << ",\n";
928 OS << "};\n"; // End of HW encoding table
930 // MCRegisterInfo initialization routine.
931 OS << "static inline void Init" << TargetName
932 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
933 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) "
935 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
936 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
937 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
938 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
939 << TargetName << "RegStrings, " << TargetName << "RegClassStrings, "
940 << TargetName << "SubRegIdxLists, "
941 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
942 << TargetName << "SubRegIdxRanges, " << TargetName
943 << "RegEncodingTable);\n\n";
945 EmitRegMapping(OS, Regs, false);
949 OS << "} // End llvm namespace\n";
950 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
954 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
955 CodeGenRegBank &RegBank) {
956 emitSourceFileHeader("Register Information Header Fragment", OS);
958 OS << "\n#ifdef GET_REGINFO_HEADER\n";
959 OS << "#undef GET_REGINFO_HEADER\n";
961 const std::string &TargetName = Target.getName();
962 std::string ClassName = TargetName + "GenRegisterInfo";
964 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
966 OS << "namespace llvm {\n\n";
968 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
969 << " explicit " << ClassName
970 << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
971 << " bool needsStackRealignment(const MachineFunction &) const override\n"
972 << " { return false; }\n";
973 if (!RegBank.getSubRegIndices().empty()) {
974 OS << " unsigned composeSubRegIndicesImpl"
975 << "(unsigned, unsigned) const override;\n"
976 << " const TargetRegisterClass *getSubClassWithSubReg"
977 << "(const TargetRegisterClass*, unsigned) const override;\n";
979 OS << " const RegClassWeight &getRegClassWeight("
980 << "const TargetRegisterClass *RC) const override;\n"
981 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
982 << " unsigned getNumRegPressureSets() const override;\n"
983 << " const char *getRegPressureSetName(unsigned Idx) const override;\n"
984 << " unsigned getRegPressureSetLimit(unsigned Idx) const override;\n"
985 << " const int *getRegClassPressureSets("
986 << "const TargetRegisterClass *RC) const override;\n"
987 << " const int *getRegUnitPressureSets("
988 << "unsigned RegUnit) const override;\n"
991 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
993 if (!RegisterClasses.empty()) {
994 OS << "namespace " << RegisterClasses[0]->Namespace
995 << " { // Register classes\n";
997 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
998 const CodeGenRegisterClass &RC = *RegisterClasses[i];
999 const std::string &Name = RC.getName();
1001 // Output the extern for the instance.
1002 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
1004 OS << "} // end of namespace " << TargetName << "\n\n";
1006 OS << "} // End llvm namespace\n";
1007 OS << "#endif // GET_REGINFO_HEADER\n\n";
1011 // runTargetDesc - Output the target register and register file descriptions.
1014 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
1015 CodeGenRegBank &RegBank){
1016 emitSourceFileHeader("Target Register and Register Classes Information", OS);
1018 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
1019 OS << "#undef GET_REGINFO_TARGET_DESC\n";
1021 OS << "namespace llvm {\n\n";
1023 // Get access to MCRegisterClass data.
1024 OS << "extern const MCRegisterClass " << Target.getName()
1025 << "MCRegisterClasses[];\n";
1027 // Start out by emitting each of the register classes.
1028 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
1029 const auto &SubRegIndices = RegBank.getSubRegIndices();
1031 // Collect all registers belonging to any allocatable class.
1032 std::set<Record*> AllocatableRegs;
1034 // Collect allocatable registers.
1035 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1036 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1037 ArrayRef<Record*> Order = RC.getOrder();
1040 AllocatableRegs.insert(Order.begin(), Order.end());
1043 // Build a shared array of value types.
1044 SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs;
1045 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
1046 VTSeqs.add(RegisterClasses[rc]->VTs);
1048 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
1049 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
1052 // Emit SubRegIndex names, skipping 0.
1053 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
1055 for (const auto &Idx : SubRegIndices) {
1056 OS << Idx.getName();
1061 // Emit SubRegIndex lane masks, including 0.
1062 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n";
1063 for (const auto &Idx : SubRegIndices) {
1064 OS << format(" 0x%08x, // ", Idx.LaneMask) << Idx.getName() << '\n';
1070 // Now that all of the structs have been emitted, emit the instances.
1071 if (!RegisterClasses.empty()) {
1072 OS << "\nstatic const TargetRegisterClass *const "
1073 << "NullRegClasses[] = { nullptr };\n\n";
1075 // Emit register class bit mask tables. The first bit mask emitted for a
1076 // register class, RC, is the set of sub-classes, including RC itself.
1078 // If RC has super-registers, also create a list of subreg indices and bit
1079 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
1080 // SuperRC, that satisfies:
1082 // For all SuperReg in SuperRC: SuperReg:Idx in RC
1084 // The 0-terminated list of subreg indices starts at:
1086 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1088 // The corresponding bitmasks follow the sub-class mask in memory. Each
1089 // mask has RCMaskWords uint32_t entries.
1091 // Every bit mask present in the list has at least one bit set.
1093 // Compress the sub-reg index lists.
1094 typedef std::vector<const CodeGenSubRegIndex*> IdxList;
1095 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
1096 SequenceToOffsetTable<IdxList, CodeGenSubRegIndex::Less> SuperRegIdxSeqs;
1097 BitVector MaskBV(RegisterClasses.size());
1099 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1100 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1101 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
1102 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1104 // Emit super-reg class masks for any relevant SubRegIndices that can
1106 IdxList &SRIList = SuperRegIdxLists[rc];
1107 for (auto &Idx : SubRegIndices) {
1109 RC.getSuperRegClasses(&Idx, MaskBV);
1112 SRIList.push_back(&Idx);
1114 printBitVectorAsHex(OS, MaskBV, 32);
1115 OS << "// " << Idx.getName();
1117 SuperRegIdxSeqs.add(SRIList);
1121 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
1122 SuperRegIdxSeqs.layout();
1123 SuperRegIdxSeqs.emit(OS, printSubRegIndex);
1126 // Emit NULL terminated super-class lists.
1127 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1128 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1129 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
1131 // Skip classes without supers. We can reuse NullRegClasses.
1135 OS << "static const TargetRegisterClass *const "
1136 << RC.getName() << "Superclasses[] = {\n";
1137 for (unsigned i = 0; i != Supers.size(); ++i)
1138 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
1139 OS << " nullptr\n};\n\n";
1143 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
1144 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1145 if (!RC.AltOrderSelect.empty()) {
1146 OS << "\nstatic inline unsigned " << RC.getName()
1147 << "AltOrderSelect(const MachineFunction &MF) {"
1148 << RC.AltOrderSelect << "}\n\n"
1149 << "static ArrayRef<MCPhysReg> " << RC.getName()
1150 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
1151 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
1152 ArrayRef<Record*> Elems = RC.getOrder(oi);
1153 if (!Elems.empty()) {
1154 OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
1155 for (unsigned elem = 0; elem != Elems.size(); ++elem)
1156 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
1160 OS << " const MCRegisterClass &MCR = " << Target.getName()
1161 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
1162 << " const ArrayRef<MCPhysReg> Order[] = {\n"
1163 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
1164 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
1165 if (RC.getOrder(oi).empty())
1166 OS << "),\n ArrayRef<MCPhysReg>(";
1168 OS << "),\n makeArrayRef(AltOrder" << oi;
1169 OS << ")\n };\n const unsigned Select = " << RC.getName()
1170 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
1171 << ");\n return Order[Select];\n}\n";
1175 // Now emit the actual value-initialized register class instances.
1176 OS << "\nnamespace " << RegisterClasses[0]->Namespace
1177 << " { // Register class instances\n";
1179 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
1180 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1181 OS << " extern const TargetRegisterClass "
1182 << RegisterClasses[i]->getName() << "RegClass = {\n "
1183 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
1184 << "RegClassID],\n "
1185 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
1186 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + "
1187 << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n ";
1188 if (RC.getSuperClasses().empty())
1189 OS << "NullRegClasses,\n ";
1191 OS << RC.getName() << "Superclasses,\n ";
1192 if (RC.AltOrderSelect.empty())
1195 OS << RC.getName() << "GetRawAllocationOrder\n";
1202 OS << "\nnamespace {\n";
1203 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
1204 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
1205 OS << " &" << RegisterClasses[i]->getQualifiedName()
1208 OS << "}\n"; // End of anonymous namespace...
1210 // Emit extra information about registers.
1211 const std::string &TargetName = Target.getName();
1212 OS << "\nstatic const TargetRegisterInfoDesc "
1213 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
1214 OS << " { 0, 0 },\n";
1216 const auto &Regs = RegBank.getRegisters();
1217 for (const auto &Reg : Regs) {
1219 OS << Reg.CostPerUse << ", "
1220 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
1222 OS << "};\n"; // End of register descriptors...
1225 std::string ClassName = Target.getName() + "GenRegisterInfo";
1227 auto SubRegIndicesSize =
1228 std::distance(SubRegIndices.begin(), SubRegIndices.end());
1230 if (!SubRegIndices.empty())
1231 emitComposeSubRegIndices(OS, RegBank, ClassName);
1233 // Emit getSubClassWithSubReg.
1234 if (!SubRegIndices.empty()) {
1235 OS << "const TargetRegisterClass *" << ClassName
1236 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1238 // Use the smallest type that can hold a regclass ID with room for a
1240 if (RegisterClasses.size() < UINT8_MAX)
1241 OS << " static const uint8_t Table[";
1242 else if (RegisterClasses.size() < UINT16_MAX)
1243 OS << " static const uint16_t Table[";
1245 PrintFatalError("Too many register classes.");
1246 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
1247 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
1248 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
1249 OS << " {\t// " << RC.getName() << "\n";
1250 for (auto &Idx : SubRegIndices) {
1251 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx))
1252 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
1253 << " -> " << SRC->getName() << "\n";
1255 OS << " 0,\t// " << Idx.getName() << "\n";
1259 OS << " };\n assert(RC && \"Missing regclass\");\n"
1260 << " if (!Idx) return RC;\n --Idx;\n"
1261 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"
1262 << " unsigned TV = Table[RC->getID()][Idx];\n"
1263 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
1266 EmitRegUnitPressure(OS, RegBank, ClassName);
1268 // Emit the constructor of the class...
1269 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1270 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
1271 OS << "extern const char " << TargetName << "RegStrings[];\n";
1272 OS << "extern const char " << TargetName << "RegClassStrings[];\n";
1273 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
1274 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
1275 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
1276 << TargetName << "SubRegIdxRanges[];\n";
1277 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1279 EmitRegMappingTables(OS, Regs, true);
1281 OS << ClassName << "::\n" << ClassName
1282 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
1283 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1284 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1285 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x";
1286 OS.write_hex(RegBank.CoveringLanes);
1288 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
1289 << ", RA, PC,\n " << TargetName
1290 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1291 << " " << TargetName << "RegUnitRoots,\n"
1292 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1293 << " " << TargetName << "RegDiffLists,\n"
1294 << " " << TargetName << "RegStrings,\n"
1295 << " " << TargetName << "RegClassStrings,\n"
1296 << " " << TargetName << "SubRegIdxLists,\n"
1297 << " " << SubRegIndicesSize + 1 << ",\n"
1298 << " " << TargetName << "SubRegIdxRanges,\n"
1299 << " " << TargetName << "RegEncodingTable);\n\n";
1301 EmitRegMapping(OS, Regs, true);
1306 // Emit CalleeSavedRegs information.
1307 std::vector<Record*> CSRSets =
1308 Records.getAllDerivedDefinitions("CalleeSavedRegs");
1309 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1310 Record *CSRSet = CSRSets[i];
1311 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1312 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1314 // Emit the *_SaveList list of callee-saved registers.
1315 OS << "static const MCPhysReg " << CSRSet->getName()
1316 << "_SaveList[] = { ";
1317 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1318 OS << getQualifiedName((*Regs)[r]) << ", ";
1321 // Emit the *_RegMask bit mask of call-preserved registers.
1322 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1324 // Check for an optional OtherPreserved set.
1325 // Add those registers to RegMask, but not to SaveList.
1326 if (DagInit *OPDag =
1327 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
1328 SetTheory::RecSet OPSet;
1329 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
1330 Covered |= RegBank.computeCoveredRegisters(
1331 ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
1334 OS << "static const uint32_t " << CSRSet->getName()
1335 << "_RegMask[] = { ";
1336 printBitVectorAsHex(OS, Covered, 32);
1341 OS << "} // End llvm namespace\n";
1342 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1345 void RegisterInfoEmitter::run(raw_ostream &OS) {
1346 CodeGenTarget Target(Records);
1347 CodeGenRegBank &RegBank = Target.getRegBank();
1348 RegBank.computeDerivedInfo();
1350 runEnums(OS, Target, RegBank);
1351 runMCDesc(OS, Target, RegBank);
1352 runTargetHeader(OS, Target, RegBank);
1353 runTargetDesc(OS, Target, RegBank);
1358 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
1359 RegisterInfoEmitter(RK).run(OS);
1362 } // End llvm namespace