1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Streams.h"
27 // runEnums - Print out enum values for all of the registers.
28 void RegisterInfoEmitter::runEnums(std::ostream &OS) {
30 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
32 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
34 EmitSourceFileHeader("Target Register Enum Values", OS);
35 OS << "namespace llvm {\n\n";
37 if (!Namespace.empty())
38 OS << "namespace " << Namespace << " {\n";
39 OS << " enum {\n NoRegister,\n";
41 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
42 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
43 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
45 if (!Namespace.empty())
47 OS << "} // End llvm namespace \n";
50 void RegisterInfoEmitter::runHeader(std::ostream &OS) {
51 EmitSourceFileHeader("Register Information Header Fragment", OS);
53 const std::string &TargetName = Target.getName();
54 std::string ClassName = TargetName + "GenRegisterInfo";
56 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
57 OS << "#include <string>\n\n";
59 OS << "namespace llvm {\n\n";
61 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
62 << " explicit " << ClassName
63 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
64 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
65 << "unsigned Flavour) const;\n"
66 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
67 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
68 << " { return false; }\n"
69 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
72 const std::vector<CodeGenRegisterClass> &RegisterClasses =
73 Target.getRegisterClasses();
75 if (!RegisterClasses.empty()) {
76 OS << "namespace " << RegisterClasses[0].Namespace
77 << " { // Register classes\n";
80 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
82 OS << " " << RegisterClasses[i].getName() << "RegClassID";
87 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
88 const std::string &Name = RegisterClasses[i].getName();
90 // Output the register class definition.
91 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
92 << " " << Name << "Class();\n"
93 << RegisterClasses[i].MethodProtos << " };\n";
95 // Output the extern for the instance.
96 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
97 // Output the extern for the pointer to the instance (should remove).
98 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
99 << Name << "RegClass;\n";
101 OS << "} // end of namespace " << TargetName << "\n\n";
103 OS << "} // End llvm namespace \n";
106 bool isSubRegisterClass(const CodeGenRegisterClass &RC,
107 std::set<Record*> &RegSet) {
108 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
109 Record *Reg = RC.Elements[i];
110 if (!RegSet.count(Reg))
116 static void addSuperReg(Record *R, Record *S,
117 std::map<Record*, std::set<Record*> > &SubRegs,
118 std::map<Record*, std::set<Record*> > &SuperRegs,
119 std::map<Record*, std::set<Record*> > &Aliases) {
121 cerr << "Error: recursive sub-register relationship between"
122 << " register " << getQualifiedName(R)
123 << " and its sub-registers?\n";
126 if (!SuperRegs[R].insert(S).second)
128 SubRegs[S].insert(R);
129 Aliases[R].insert(S);
130 Aliases[S].insert(R);
131 if (SuperRegs.count(S))
132 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
133 E = SuperRegs[S].end(); I != E; ++I)
134 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
137 static void addSubSuperReg(Record *R, Record *S,
138 std::map<Record*, std::set<Record*> > &SubRegs,
139 std::map<Record*, std::set<Record*> > &SuperRegs,
140 std::map<Record*, std::set<Record*> > &Aliases) {
142 cerr << "Error: recursive sub-register relationship between"
143 << " register " << getQualifiedName(R)
144 << " and its sub-registers?\n";
148 if (!SubRegs[R].insert(S).second)
150 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
151 Aliases[R].insert(S);
152 Aliases[S].insert(R);
153 if (SubRegs.count(S))
154 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
155 E = SubRegs[S].end(); I != E; ++I)
156 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
159 class RegisterSorter {
161 std::map<Record*, std::set<Record*> > &RegisterSubRegs;
164 RegisterSorter(std::map<Record*, std::set<Record*> > &RS)
165 : RegisterSubRegs(RS) {};
167 bool operator()(Record *RegA, Record *RegB) {
168 // B is sub-register of A.
169 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
173 // RegisterInfoEmitter::run - Main register file description emitter.
175 void RegisterInfoEmitter::run(std::ostream &OS) {
176 CodeGenTarget Target;
177 EmitSourceFileHeader("Register Information Source Fragment", OS);
179 OS << "namespace llvm {\n\n";
181 // Start out by emitting each of the register classes... to do this, we build
182 // a set of registers which belong to a register class, this is to ensure that
183 // each register is only in a single register class.
185 const std::vector<CodeGenRegisterClass> &RegisterClasses =
186 Target.getRegisterClasses();
188 // Loop over all of the register classes... emitting each one.
189 OS << "namespace { // Register classes...\n";
191 // RegClassesBelongedTo - Keep track of which register classes each reg
193 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
195 // Emit the register enum value arrays for each RegisterClass
196 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
197 const CodeGenRegisterClass &RC = RegisterClasses[rc];
199 // Give the register class a legal C name if it's anonymous.
200 std::string Name = RC.TheDef->getName();
202 // Emit the register list now.
203 OS << " // " << Name << " Register Class...\n"
204 << " static const unsigned " << Name
206 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
207 Record *Reg = RC.Elements[i];
208 OS << getQualifiedName(Reg) << ", ";
210 // Keep track of which regclasses this register is in.
211 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
216 // Emit the ValueType arrays for each RegisterClass
217 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
218 const CodeGenRegisterClass &RC = RegisterClasses[rc];
220 // Give the register class a legal C name if it's anonymous.
221 std::string Name = RC.TheDef->getName() + "VTs";
223 // Emit the register list now.
225 << " Register Class Value Types...\n"
226 << " static const MVT " << Name
228 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
229 OS << getEnumName(RC.VTs[i]) << ", ";
230 OS << "MVT::Other\n };\n\n";
232 OS << "} // end anonymous namespace\n\n";
234 // Now that all of the structs have been emitted, emit the instances.
235 if (!RegisterClasses.empty()) {
236 OS << "namespace " << RegisterClasses[0].Namespace
237 << " { // Register class instances\n";
238 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
239 OS << " " << RegisterClasses[i].getName() << "Class\t"
240 << RegisterClasses[i].getName() << "RegClass;\n";
242 std::map<unsigned, std::set<unsigned> > SuperClassMap;
243 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
246 // Emit the sub-register classes for each RegisterClass
247 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
248 const CodeGenRegisterClass &RC = RegisterClasses[rc];
250 // Give the register class a legal C name if it's anonymous.
251 std::string Name = RC.TheDef->getName();
254 << " Sub-register Classess...\n"
255 << " static const TargetRegisterClass* const "
256 << Name << "SubRegClasses [] = {\n ";
260 for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size();
261 subrc != subrcMax; ++subrc) {
262 unsigned rc2 = 0, e2 = RegisterClasses.size();
263 for (; rc2 != e2; ++rc2) {
264 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
265 if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
268 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
271 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
272 SuperRegClassMap.find(rc2);
273 if (SCMI == SuperRegClassMap.end()) {
274 SuperRegClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
275 SCMI = SuperRegClassMap.find(rc2);
277 SCMI->second.insert(rc);
282 throw "Register Class member '" +
283 RC.SubRegClasses[subrc]->getName() +
284 "' is not a valid RegisterClass!";
287 OS << (!Empty ? ", " : "") << "NULL";
291 // Emit the super-register classes for each RegisterClass
292 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
293 const CodeGenRegisterClass &RC = RegisterClasses[rc];
295 // Give the register class a legal C name if it's anonymous.
296 std::string Name = RC.TheDef->getName();
299 << " Super-register Classess...\n"
300 << " static const TargetRegisterClass* const "
301 << Name << "SuperRegClasses [] = {\n ";
304 std::map<unsigned, std::set<unsigned> >::iterator I =
305 SuperRegClassMap.find(rc);
306 if (I != SuperRegClassMap.end()) {
307 for (std::set<unsigned>::iterator II = I->second.begin(),
308 EE = I->second.end(); II != EE; ++II) {
309 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
312 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
317 OS << (!Empty ? ", " : "") << "NULL";
321 // Emit the sub-classes array for each RegisterClass
322 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
323 const CodeGenRegisterClass &RC = RegisterClasses[rc];
325 // Give the register class a legal C name if it's anonymous.
326 std::string Name = RC.TheDef->getName();
328 std::set<Record*> RegSet;
329 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
330 Record *Reg = RC.Elements[i];
335 << " Register Class sub-classes...\n"
336 << " static const TargetRegisterClass* const "
337 << Name << "Subclasses [] = {\n ";
340 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
341 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
342 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
343 RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
346 if (!Empty) OS << ", ";
347 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
350 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
351 SuperClassMap.find(rc2);
352 if (SCMI == SuperClassMap.end()) {
353 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
354 SCMI = SuperClassMap.find(rc2);
356 SCMI->second.insert(rc);
359 OS << (!Empty ? ", " : "") << "NULL";
363 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
364 const CodeGenRegisterClass &RC = RegisterClasses[rc];
366 // Give the register class a legal C name if it's anonymous.
367 std::string Name = RC.TheDef->getName();
370 << " Register Class super-classes...\n"
371 << " static const TargetRegisterClass* const "
372 << Name << "Superclasses [] = {\n ";
375 std::map<unsigned, std::set<unsigned> >::iterator I =
376 SuperClassMap.find(rc);
377 if (I != SuperClassMap.end()) {
378 for (std::set<unsigned>::iterator II = I->second.begin(),
379 EE = I->second.end(); II != EE; ++II) {
380 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
381 if (!Empty) OS << ", ";
382 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
387 OS << (!Empty ? ", " : "") << "NULL";
392 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
393 const CodeGenRegisterClass &RC = RegisterClasses[i];
394 OS << RC.MethodBodies << "\n";
395 OS << RC.getName() << "Class::" << RC.getName()
396 << "Class() : TargetRegisterClass("
397 << RC.getName() + "RegClassID" << ", "
398 << RC.getName() + "VTs" << ", "
399 << RC.getName() + "Subclasses" << ", "
400 << RC.getName() + "Superclasses" << ", "
401 << RC.getName() + "SubRegClasses" << ", "
402 << RC.getName() + "SuperRegClasses" << ", "
403 << RC.SpillSize/8 << ", "
404 << RC.SpillAlignment/8 << ", "
405 << RC.CopyCost << ", "
406 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
413 OS << "\nnamespace {\n";
414 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
415 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
416 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
420 // Emit register sub-registers / super-registers, aliases...
421 std::map<Record*, std::set<Record*> > RegisterSubRegs;
422 std::map<Record*, std::set<Record*> > RegisterSuperRegs;
423 std::map<Record*, std::set<Record*> > RegisterAliases;
424 std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
425 std::map<Record*, std::vector<int> > DwarfRegNums;
427 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
429 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
430 Record *R = Regs[i].TheDef;
431 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
432 // Add information that R aliases all of the elements in the list... and
433 // that everything in the list aliases R.
434 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
436 if (RegisterAliases[R].count(Reg))
437 cerr << "Warning: register alias between " << getQualifiedName(R)
438 << " and " << getQualifiedName(Reg)
439 << " specified multiple times!\n";
440 RegisterAliases[R].insert(Reg);
442 if (RegisterAliases[Reg].count(R))
443 cerr << "Warning: register alias between " << getQualifiedName(R)
444 << " and " << getQualifiedName(Reg)
445 << " specified multiple times!\n";
446 RegisterAliases[Reg].insert(R);
450 // Process sub-register sets.
451 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
452 Record *R = Regs[i].TheDef;
453 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
454 // Process sub-register set and add aliases information.
455 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
456 Record *SubReg = LI[j];
457 if (RegisterSubRegs[R].count(SubReg))
458 cerr << "Warning: register " << getQualifiedName(SubReg)
459 << " specified as a sub-register of " << getQualifiedName(R)
460 << " multiple times!\n";
461 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
466 if (!RegisterAliases.empty())
467 OS << "\n\n // Register Alias Sets...\n";
469 // Emit the empty alias list
470 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
471 // Loop over all of the registers which have aliases, emitting the alias list
473 for (std::map<Record*, std::set<Record*> >::iterator
474 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
475 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
476 for (std::set<Record*>::iterator ASI = I->second.begin(),
477 E = I->second.end(); ASI != E; ++ASI)
478 OS << getQualifiedName(*ASI) << ", ";
482 if (!RegisterSubRegs.empty())
483 OS << "\n\n // Register Sub-registers Sets...\n";
485 // Emit the empty sub-registers list
486 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
487 // Loop over all of the registers which have sub-registers, emitting the
488 // sub-registers list to memory.
489 for (std::map<Record*, std::set<Record*> >::iterator
490 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
491 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
492 std::vector<Record*> SubRegsVector;
493 for (std::set<Record*>::iterator ASI = I->second.begin(),
494 E = I->second.end(); ASI != E; ++ASI)
495 SubRegsVector.push_back(*ASI);
496 RegisterSorter RS(RegisterSubRegs);
497 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
498 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
499 OS << getQualifiedName(SubRegsVector[i]) << ", ";
503 if (!RegisterSuperRegs.empty())
504 OS << "\n\n // Register Super-registers Sets...\n";
506 // Emit the empty super-registers list
507 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
508 // Loop over all of the registers which have super-registers, emitting the
509 // super-registers list to memory.
510 for (std::map<Record*, std::set<Record*> >::iterator
511 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
512 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
514 std::vector<Record*> SuperRegsVector;
515 for (std::set<Record*>::iterator ASI = I->second.begin(),
516 E = I->second.end(); ASI != E; ++ASI)
517 SuperRegsVector.push_back(*ASI);
518 RegisterSorter RS(RegisterSubRegs);
519 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
520 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
521 OS << getQualifiedName(SuperRegsVector[i]) << ", ";
525 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
526 OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n";
528 // Now that register alias and sub-registers sets have been emitted, emit the
529 // register descriptors now.
530 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
531 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
532 const CodeGenRegister &Reg = Registers[i];
534 if (!Reg.TheDef->getValueAsString("AsmName").empty())
535 OS << Reg.TheDef->getValueAsString("AsmName");
539 if (!Reg.TheDef->getValueAsString("Name").empty()) {
540 OS << Reg.TheDef->getValueAsString("Name");
542 // Default to "name".
543 if (!Reg.TheDef->getValueAsString("AsmName").empty())
544 OS << Reg.TheDef->getValueAsString("AsmName");
549 if (RegisterAliases.count(Reg.TheDef))
550 OS << Reg.getName() << "_AliasSet,\t";
552 OS << "Empty_AliasSet,\t";
553 if (RegisterSubRegs.count(Reg.TheDef))
554 OS << Reg.getName() << "_SubRegsSet,\t";
556 OS << "Empty_SubRegsSet,\t";
557 if (RegisterSuperRegs.count(Reg.TheDef))
558 OS << Reg.getName() << "_SuperRegsSet },\n";
560 OS << "Empty_SuperRegsSet },\n";
562 OS << " };\n"; // End of register descriptors...
563 OS << "}\n\n"; // End of anonymous namespace...
565 std::string ClassName = Target.getName() + "GenRegisterInfo";
567 // Calculate the mapping of subregister+index pairs to physical registers.
568 std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
569 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
570 int subRegIndex = SubRegs[i]->getValueAsInt("index");
571 std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
572 std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
574 if (From.size() != To.size()) {
575 cerr << "Error: register list and sub-register list not of equal length"
576 << " in SubRegSet\n";
580 // For each entry in from/to vectors, insert the to register at index
581 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
582 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
585 // Emit the subregister + index mapping function based on the information
587 OS << "unsigned " << ClassName
588 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
589 << " switch (RegNo) {\n"
590 << " default: abort(); break;\n";
591 for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
592 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
593 OS << " case " << getQualifiedName(I->first) << ":\n";
594 OS << " switch (Index) {\n";
595 OS << " default: abort(); break;\n";
596 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
597 OS << " case " << (I->second)[i].first << ": return "
598 << getQualifiedName((I->second)[i].second) << ";\n";
599 OS << " }; break;\n";
602 OS << " return 0;\n";
605 // Emit the constructor of the class...
606 OS << ClassName << "::" << ClassName
607 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
608 << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
609 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
610 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
612 // Collect all information about dwarf register numbers
614 // First, just pull all provided information to the map
615 unsigned maxLength = 0;
616 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
617 Record *Reg = Registers[i].TheDef;
618 std::vector<int> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
619 maxLength = std::max((size_t)maxLength, RegNums.size());
620 if (DwarfRegNums.count(Reg))
621 cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
622 << "specified multiple times\n";
623 DwarfRegNums[Reg] = RegNums;
626 // Now we know maximal length of number list. Append -1's, where needed
627 for (std::map<Record*, std::vector<int> >::iterator
628 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
629 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
630 I->second.push_back(-1);
632 // Emit information about the dwarf register numbers.
633 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
634 << "unsigned Flavour) const {\n"
635 << " switch (Flavour) {\n"
637 << " assert(0 && \"Unknown DWARF flavour\");\n"
640 for (unsigned i = 0, e = maxLength; i != e; ++i) {
641 OS << " case " << i << ":\n"
642 << " switch (RegNum) {\n"
644 << " assert(0 && \"Invalid RegNum\");\n"
647 for (std::map<Record*, std::vector<int> >::iterator
648 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
649 int RegNo = I->second[i];
651 OS << " case " << getQualifiedName(I->first) << ":\n"
652 << " return " << RegNo << ";\n";
654 OS << " case " << getQualifiedName(I->first) << ":\n"
655 << " assert(0 && \"Invalid register for this mode\");\n"
663 OS << "} // End llvm namespace \n";