1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
19 #include "llvm/TableGen/Record.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/Support/Format.h"
28 // runEnums - Print out enum values for all of the registers.
30 RegisterInfoEmitter::runEnums(raw_ostream &OS,
31 CodeGenTarget &Target, CodeGenRegBank &Bank) {
32 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
34 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
36 EmitSourceFileHeader("Target Register Enum Values", OS);
38 OS << "\n#ifdef GET_REGINFO_ENUM\n";
39 OS << "#undef GET_REGINFO_ENUM\n";
41 OS << "namespace llvm {\n\n";
43 OS << "class MCRegisterClass;\n"
44 << "extern const MCRegisterClass " << Namespace
45 << "MCRegisterClasses[];\n\n";
47 if (!Namespace.empty())
48 OS << "namespace " << Namespace << " {\n";
49 OS << "enum {\n NoRegister,\n";
51 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
52 OS << " " << Registers[i]->getName() << " = " <<
53 Registers[i]->EnumValue << ",\n";
54 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
55 "Register enum value mismatch!");
56 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
58 if (!Namespace.empty())
61 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
62 if (!RegisterClasses.empty()) {
63 OS << "\n// Register classes\n";
64 if (!Namespace.empty())
65 OS << "namespace " << Namespace << " {\n";
67 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
69 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
73 if (!Namespace.empty())
77 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
78 // If the only definition is the default NoRegAltName, we don't need to
80 if (RegAltNameIndices.size() > 1) {
81 OS << "\n// Register alternate name indices\n";
82 if (!Namespace.empty())
83 OS << "namespace " << Namespace << " {\n";
85 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
86 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
87 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
89 if (!Namespace.empty())
93 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
94 if (!SubRegIndices.empty()) {
95 OS << "\n// Subregister indices\n";
96 std::string Namespace =
97 SubRegIndices[0]->getNamespace();
98 if (!Namespace.empty())
99 OS << "namespace " << Namespace << " {\n";
100 OS << "enum {\n NoSubRegister,\n";
101 for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
102 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
103 OS << " NUM_TARGET_NAMED_SUBREGS\n};\n";
104 if (!Namespace.empty())
108 OS << "} // End llvm namespace \n";
109 OS << "#endif // GET_REGINFO_ENUM\n\n";
113 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
114 const std::vector<CodeGenRegister*> &Regs,
117 // Collect all information about dwarf register numbers
118 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
119 DwarfRegNumsMapTy DwarfRegNums;
121 // First, just pull all provided information to the map
122 unsigned maxLength = 0;
123 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
124 Record *Reg = Regs[i]->TheDef;
125 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
126 maxLength = std::max((size_t)maxLength, RegNums.size());
127 if (DwarfRegNums.count(Reg))
128 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
129 << "specified multiple times\n";
130 DwarfRegNums[Reg] = RegNums;
136 // Now we know maximal length of number list. Append -1's, where needed
137 for (DwarfRegNumsMapTy::iterator
138 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
139 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
140 I->second.push_back(-1);
142 // Emit reverse information about the dwarf register numbers.
143 for (unsigned j = 0; j < 2; ++j) {
146 OS << "DwarfFlavour";
151 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
153 for (unsigned i = 0, e = maxLength; i != e; ++i) {
154 OS << " case " << i << ":\n";
155 for (DwarfRegNumsMapTy::iterator
156 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
157 int DwarfRegNo = I->second[i];
163 OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
164 << getQualifiedName(I->first) << ", ";
176 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
177 Record *Reg = Regs[i]->TheDef;
178 const RecordVal *V = Reg->getValue("DwarfAlias");
179 if (!V || !V->getValue())
182 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
183 Record *Alias = DI->getDef();
184 DwarfRegNums[Reg] = DwarfRegNums[Alias];
187 // Emit information about the dwarf register numbers.
188 for (unsigned j = 0; j < 2; ++j) {
191 OS << "DwarfFlavour";
196 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
198 for (unsigned i = 0, e = maxLength; i != e; ++i) {
199 OS << " case " << i << ":\n";
200 // Sort by name to get a stable order.
201 for (DwarfRegNumsMapTy::iterator
202 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
203 int RegNo = I->second[i];
204 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
210 OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
224 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
225 // Width is the number of bits per hex number.
226 static void printBitVectorAsHex(raw_ostream &OS,
227 const BitVector &Bits,
229 assert(Width <= 32 && "Width too large");
230 unsigned Digits = (Width + 3) / 4;
231 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
233 for (unsigned j = 0; j != Width && i + j != e; ++j)
234 Value |= Bits.test(i + j) << j;
235 OS << format("0x%0*x, ", Digits, Value);
239 // Helper to emit a set of bits into a constant byte array.
240 class BitVectorEmitter {
243 void add(unsigned v) {
244 if (v >= Values.size())
245 Values.resize(((v/8)+1)*8); // Round up to the next byte.
249 void print(raw_ostream &OS) {
250 printBitVectorAsHex(OS, Values, 8);
255 // runMCDesc - Print out MC register descriptions.
258 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
259 CodeGenRegBank &RegBank) {
260 EmitSourceFileHeader("MC Register Information", OS);
262 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
263 OS << "#undef GET_REGINFO_MC_DESC\n";
265 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
266 RegBank.computeOverlaps(Overlaps);
268 OS << "namespace llvm {\n\n";
270 const std::string &TargetName = Target.getName();
272 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
274 OS << "extern const unsigned " << TargetName << "RegOverlaps[] = {\n";
276 // Emit an overlap list for all registers.
277 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
278 const CodeGenRegister *Reg = Regs[i];
279 const CodeGenRegister::Set &O = Overlaps[Reg];
280 // Move Reg to the front so TRI::getAliasSet can share the list.
281 OS << " /* " << Reg->getName() << "_Overlaps */ "
282 << getQualifiedName(Reg->TheDef) << ", ";
283 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
286 OS << getQualifiedName((*I)->TheDef) << ", ";
291 OS << "extern const unsigned " << TargetName << "SubRegsSet[] = {\n";
292 // Emit the empty sub-registers list
293 OS << " /* Empty_SubRegsSet */ 0,\n";
294 // Loop over all of the registers which have sub-registers, emitting the
295 // sub-registers list to memory.
296 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
297 const CodeGenRegister &Reg = *Regs[i];
298 if (Reg.getSubRegs().empty())
300 // getSubRegs() orders by SubRegIndex. We want a topological order.
301 SetVector<CodeGenRegister*> SR;
302 Reg.addSubRegsPreOrder(SR, RegBank);
303 OS << " /* " << Reg.getName() << "_SubRegsSet */ ";
304 for (unsigned j = 0, je = SR.size(); j != je; ++j)
305 OS << getQualifiedName(SR[j]->TheDef) << ", ";
310 OS << "extern const unsigned " << TargetName << "SuperRegsSet[] = {\n";
311 // Emit the empty super-registers list
312 OS << " /* Empty_SuperRegsSet */ 0,\n";
313 // Loop over all of the registers which have super-registers, emitting the
314 // super-registers list to memory.
315 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
316 const CodeGenRegister &Reg = *Regs[i];
317 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
320 OS << " /* " << Reg.getName() << "_SuperRegsSet */ ";
321 for (unsigned j = 0, je = SR.size(); j != je; ++j)
322 OS << getQualifiedName(SR[j]->TheDef) << ", ";
327 OS << "extern const MCRegisterDesc " << TargetName
328 << "RegDesc[] = { // Descriptors\n";
329 OS << " { \"NOREG\", 0, 0, 0 },\n";
331 // Now that register alias and sub-registers sets have been emitted, emit the
332 // register descriptors now.
333 unsigned OverlapsIndex = 0;
334 unsigned SubRegIndex = 1; // skip 1 for empty set
335 unsigned SuperRegIndex = 1; // skip 1 for empty set
336 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
337 const CodeGenRegister *Reg = Regs[i];
339 OS << Reg->getName() << "\", /* " << Reg->getName() << "_Overlaps */ "
340 << OverlapsIndex << ", ";
341 OverlapsIndex += Overlaps[Reg].size() + 1;
342 if (!Reg->getSubRegs().empty()) {
343 OS << "/* " << Reg->getName() << "_SubRegsSet */ " << SubRegIndex
345 // FIXME not very nice to recalculate this
346 SetVector<CodeGenRegister*> SR;
347 Reg->addSubRegsPreOrder(SR, RegBank);
348 SubRegIndex += SR.size() + 1;
350 OS << "/* Empty_SubRegsSet */ 0, ";
351 if (!Reg->getSuperRegs().empty()) {
352 OS << "/* " << Reg->getName() << "_SuperRegsSet */ " << SuperRegIndex;
353 SuperRegIndex += Reg->getSuperRegs().size() + 1;
355 OS << "/* Empty_SuperRegsSet */ 0";
358 OS << "};\n\n"; // End of register descriptors...
360 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
362 // Loop over all of the register classes... emitting each one.
363 OS << "namespace { // Register classes...\n";
365 // Emit the register enum value arrays for each RegisterClass
366 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
367 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
368 ArrayRef<Record*> Order = RC.getOrder();
370 // Give the register class a legal C name if it's anonymous.
371 std::string Name = RC.getName();
373 // Emit the register list now.
374 OS << " // " << Name << " Register Class...\n"
375 << " const uint16_t " << Name
377 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
378 Record *Reg = Order[i];
379 OS << getQualifiedName(Reg) << ", ";
383 OS << " // " << Name << " Bit set.\n"
384 << " const uint8_t " << Name
386 BitVectorEmitter BVE;
387 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
388 Record *Reg = Order[i];
389 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
397 OS << "extern const MCRegisterClass " << TargetName
398 << "MCRegisterClasses[] = {\n";
400 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
401 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
402 OS << " { " << RC.getQualifiedName() + "RegClassID" << ", "
403 << '\"' << RC.getName() << "\", "
404 << RC.SpillSize/8 << ", "
405 << RC.SpillAlignment/8 << ", "
406 << RC.CopyCost << ", "
407 << RC.Allocatable << ", "
408 << RC.getName() << ", " << RC.getName() << "Bits, "
409 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits) },\n";
414 // Emit the data table for getSubReg().
415 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
416 if (SubRegIndices.size()) {
417 OS << "const uint16_t " << TargetName << "SubRegTable[]["
418 << SubRegIndices.size() << "] = {\n";
419 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
420 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
421 OS << " /* " << Regs[i]->TheDef->getName() << " */\n";
427 for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
428 // FIXME: We really should keep this to 80 columns...
429 CodeGenRegister::SubRegMap::const_iterator SubReg =
430 SRM.find(SubRegIndices[j]);
431 if (SubReg != SRM.end())
432 OS << getQualifiedName(SubReg->second->TheDef);
438 OS << "}" << (i != e ? "," : "") << "\n";
441 OS << "const uint16_t *get" << TargetName
442 << "SubRegTable() {\n return (const uint16_t *)" << TargetName
443 << "SubRegTable;\n}\n\n";
446 // MCRegisterInfo initialization routine.
447 OS << "static inline void Init" << TargetName
448 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
449 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
450 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
451 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
452 << RegisterClasses.size() << ", " << TargetName << "RegOverlaps, "
453 << TargetName << "SubRegsSet, " << TargetName << "SuperRegsSet, ";
454 if (SubRegIndices.size() != 0)
455 OS << "(uint16_t*)" << TargetName << "SubRegTable, "
456 << SubRegIndices.size() << ");\n\n";
458 OS << "NULL, 0);\n\n";
460 EmitRegMapping(OS, Regs, false);
464 OS << "} // End llvm namespace \n";
465 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
469 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
470 CodeGenRegBank &RegBank) {
471 EmitSourceFileHeader("Register Information Header Fragment", OS);
473 OS << "\n#ifdef GET_REGINFO_HEADER\n";
474 OS << "#undef GET_REGINFO_HEADER\n";
476 const std::string &TargetName = Target.getName();
477 std::string ClassName = TargetName + "GenRegisterInfo";
479 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
480 OS << "#include <string>\n\n";
482 OS << "namespace llvm {\n\n";
484 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
485 << " explicit " << ClassName
486 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
487 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
488 << " { return false; }\n"
489 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
490 << " const TargetRegisterClass *"
491 "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
492 << " const TargetRegisterClass *getMatchingSuperRegClass("
493 "const TargetRegisterClass*, const TargetRegisterClass*, "
497 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
499 if (!RegisterClasses.empty()) {
500 OS << "namespace " << RegisterClasses[0]->Namespace
501 << " { // Register classes\n";
503 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
504 const CodeGenRegisterClass &RC = *RegisterClasses[i];
505 const std::string &Name = RC.getName();
507 // Output the extern for the instance.
508 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
509 // Output the extern for the pointer to the instance (should remove).
510 OS << " static const TargetRegisterClass * const " << Name
511 << "RegisterClass = &" << Name << "RegClass;\n";
513 OS << "} // end of namespace " << TargetName << "\n\n";
515 OS << "} // End llvm namespace \n";
516 OS << "#endif // GET_REGINFO_HEADER\n\n";
520 // runTargetDesc - Output the target register and register file descriptions.
523 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
524 CodeGenRegBank &RegBank){
525 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
527 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
528 OS << "#undef GET_REGINFO_TARGET_DESC\n";
530 OS << "namespace llvm {\n\n";
532 // Get access to MCRegisterClass data.
533 OS << "extern const MCRegisterClass " << Target.getName()
534 << "MCRegisterClasses[];\n";
536 // Start out by emitting each of the register classes.
537 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
539 // Collect all registers belonging to any allocatable class.
540 std::set<Record*> AllocatableRegs;
542 // Collect allocatable registers.
543 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
544 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
545 ArrayRef<Record*> Order = RC.getOrder();
548 AllocatableRegs.insert(Order.begin(), Order.end());
551 OS << "namespace { // Register classes...\n";
553 // Emit the ValueType arrays for each RegisterClass
554 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
555 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
557 // Give the register class a legal C name if it's anonymous.
558 std::string Name = RC.getName() + "VTs";
560 // Emit the register list now.
562 << " Register Class Value Types...\n"
563 << " const MVT::SimpleValueType " << Name
565 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
566 OS << getEnumName(RC.VTs[i]) << ", ";
567 OS << "MVT::Other\n };\n\n";
569 OS << "} // end anonymous namespace\n\n";
571 // Now that all of the structs have been emitted, emit the instances.
572 if (!RegisterClasses.empty()) {
573 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
575 OS << "\nstatic const TargetRegisterClass *const "
576 << "NullRegClasses[] = { NULL };\n\n";
578 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
580 if (NumSubRegIndices) {
581 // Compute the super-register classes for each RegisterClass
582 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
583 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
584 for (DenseMap<Record*,Record*>::const_iterator
585 i = RC.SubRegClasses.begin(),
586 e = RC.SubRegClasses.end(); i != e; ++i) {
587 // Find the register class number of i->second for SuperRegClassMap.
588 const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
589 assert(RC2 && "Invalid register class in SubRegClasses");
590 SuperRegClassMap[RC2->EnumValue].insert(rc);
594 // Emit the super-register classes for each RegisterClass
595 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
596 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
598 // Give the register class a legal C name if it's anonymous.
599 std::string Name = RC.getName();
602 << " Super-register Classes...\n"
603 << "static const TargetRegisterClass *const "
604 << Name << "SuperRegClasses[] = {\n ";
607 std::map<unsigned, std::set<unsigned> >::iterator I =
608 SuperRegClassMap.find(rc);
609 if (I != SuperRegClassMap.end()) {
610 for (std::set<unsigned>::iterator II = I->second.begin(),
611 EE = I->second.end(); II != EE; ++II) {
612 const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
615 OS << "&" << RC2.getQualifiedName() << "RegClass";
620 OS << (!Empty ? ", " : "") << "NULL";
625 // Emit the sub-classes array for each RegisterClass
626 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
627 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
629 // Give the register class a legal C name if it's anonymous.
630 std::string Name = RC.getName();
632 OS << "static const unsigned " << Name << "SubclassMask[] = {\n ";
633 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
637 // Emit NULL terminated super-class lists.
638 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
639 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
640 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
642 // Skip classes without supers. We can reuse NullRegClasses.
646 OS << "static const TargetRegisterClass *const "
647 << RC.getName() << "Superclasses[] = {\n";
648 for (unsigned i = 0; i != Supers.size(); ++i)
649 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
650 OS << " NULL\n};\n\n";
654 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
655 const CodeGenRegisterClass &RC = *RegisterClasses[i];
656 if (!RC.AltOrderSelect.empty()) {
657 OS << "\nstatic inline unsigned " << RC.getName()
658 << "AltOrderSelect(const MachineFunction &MF) {"
659 << RC.AltOrderSelect << "}\n\n"
660 << "static ArrayRef<uint16_t> " << RC.getName()
661 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
662 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
663 ArrayRef<Record*> Elems = RC.getOrder(oi);
664 if (!Elems.empty()) {
665 OS << " static const uint16_t AltOrder" << oi << "[] = {";
666 for (unsigned elem = 0; elem != Elems.size(); ++elem)
667 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
671 OS << " const MCRegisterClass &MCR = " << Target.getName()
672 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
673 << " const ArrayRef<uint16_t> Order[] = {\n"
674 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
675 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
676 if (RC.getOrder(oi).empty())
677 OS << "),\n ArrayRef<uint16_t>(";
679 OS << "),\n makeArrayRef(AltOrder" << oi;
680 OS << ")\n };\n const unsigned Select = " << RC.getName()
681 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
682 << ");\n return Order[Select];\n}\n";
686 // Now emit the actual value-initialized register class instances.
687 OS << "namespace " << RegisterClasses[0]->Namespace
688 << " { // Register class instances\n";
690 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
691 const CodeGenRegisterClass &RC = *RegisterClasses[i];
692 OS << " extern const TargetRegisterClass "
693 << RegisterClasses[i]->getName() << "RegClass = {\n "
694 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
696 << RC.getName() << "VTs,\n "
697 << RC.getName() << "SubclassMask,\n ";
698 if (RC.getSuperClasses().empty())
699 OS << "NullRegClasses,\n ";
701 OS << RC.getName() << "Superclasses,\n ";
702 OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
704 if (RC.AltOrderSelect.empty())
707 OS << RC.getName() << "GetRawAllocationOrder\n";
714 OS << "\nnamespace {\n";
715 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
716 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
717 OS << " &" << RegisterClasses[i]->getQualifiedName()
720 OS << "}\n"; // End of anonymous namespace...
722 // Emit extra information about registers.
723 const std::string &TargetName = Target.getName();
724 OS << "\n static const TargetRegisterInfoDesc "
725 << TargetName << "RegInfoDesc[] = "
726 << "{ // Extra Descriptors\n";
727 OS << " { 0, 0 },\n";
729 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
730 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
731 const CodeGenRegister &Reg = *Regs[i];
733 OS << Reg.CostPerUse << ", "
734 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
736 OS << " };\n"; // End of register descriptors...
739 // Calculate the mapping of subregister+index pairs to physical registers.
740 // This will also create further anonymous indices.
741 unsigned NamedIndices = RegBank.getNumNamedIndices();
743 // Emit SubRegIndex names, skipping 0
744 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
745 OS << "\n static const char *const " << TargetName
746 << "SubRegIndexTable[] = { \"";
747 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
748 OS << SubRegIndices[i]->getName();
754 // Emit names of the anonymous subreg indices.
755 if (SubRegIndices.size() > NamedIndices) {
757 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
758 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
766 std::string ClassName = Target.getName() + "GenRegisterInfo";
768 // Emit composeSubRegIndices
769 OS << "unsigned " << ClassName
770 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
771 << " switch (IdxA) {\n"
772 << " default:\n return IdxB;\n";
773 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
775 for (unsigned j = 0; j != e; ++j) {
776 if (CodeGenSubRegIndex *Comp =
777 SubRegIndices[i]->compose(SubRegIndices[j])) {
779 OS << " case " << SubRegIndices[i]->getQualifiedName()
780 << ": switch(IdxB) {\n default: return IdxB;\n";
783 OS << " case " << SubRegIndices[j]->getQualifiedName()
784 << ": return " << Comp->getQualifiedName() << ";\n";
792 // Emit getSubClassWithSubReg.
793 OS << "const TargetRegisterClass *" << ClassName
794 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
796 if (SubRegIndices.empty()) {
797 OS << " assert(Idx == 0 && \"Target has no sub-registers\");\n"
800 // Use the smallest type that can hold a regclass ID with room for a
802 if (RegisterClasses.size() < UINT8_MAX)
803 OS << " static const uint8_t Table[";
804 else if (RegisterClasses.size() < UINT16_MAX)
805 OS << " static const uint16_t Table[";
807 throw "Too many register classes.";
808 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
809 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
810 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
811 OS << " {\t// " << RC.getName() << "\n";
812 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
813 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
814 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
815 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
816 << " -> " << SRC->getName() << "\n";
818 OS << " 0,\t// " << Idx->getName() << "\n";
822 OS << " };\n assert(RC && \"Missing regclass\");\n"
823 << " if (!Idx) return RC;\n --Idx;\n"
824 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
825 << " unsigned TV = Table[RC->getID()][Idx];\n"
826 << " return TV ? getRegClass(TV - 1) : 0;\n";
830 // Emit getMatchingSuperRegClass.
831 OS << "const TargetRegisterClass *" << ClassName
832 << "::getMatchingSuperRegClass(const TargetRegisterClass *A,"
833 " const TargetRegisterClass *B, unsigned Idx) const {\n";
834 if (SubRegIndices.empty()) {
835 OS << " llvm_unreachable(\"Target has no sub-registers\");\n";
837 // We need to find the largest sub-class of A such that every register has
838 // an Idx sub-register in B. Map (B, Idx) to a bit-vector of
839 // super-register classes that map into B. Then compute the largest common
840 // sub-class with A by taking advantage of the register class ordering,
841 // like getCommonSubClass().
843 // Bitvector table is NumRCs x NumSubIndexes x BVWords, where BVWords is
844 // the number of 32-bit words required to represent all register classes.
845 const unsigned BVWords = (RegisterClasses.size()+31)/32;
846 BitVector BV(RegisterClasses.size());
848 OS << " static const uint32_t Table[" << RegisterClasses.size()
849 << "][" << SubRegIndices.size() << "][" << BVWords << "] = {\n";
850 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
851 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
852 OS << " {\t// " << RC.getName() << "\n";
853 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
854 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
856 RC.getSuperRegClasses(Idx, BV);
858 printBitVectorAsHex(OS, BV, 32);
859 OS << "},\t// " << Idx->getName() << '\n';
863 OS << " };\n assert(A && B && \"Missing regclass\");\n"
865 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
866 << " const unsigned *TV = Table[B->getID()][Idx];\n"
867 << " const unsigned *SC = A->getSubClassMask();\n"
868 << " for (unsigned i = 0; i != " << BVWords << "; ++i)\n"
869 << " if (unsigned Common = TV[i] & SC[i])\n"
870 << " return getRegClass(32*i + CountTrailingZeros_32(Common));\n"
875 // Emit the constructor of the class...
876 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
877 OS << "extern const unsigned " << TargetName << "RegOverlaps[];\n";
878 OS << "extern const unsigned " << TargetName << "SubRegsSet[];\n";
879 OS << "extern const unsigned " << TargetName << "SuperRegsSet[];\n";
880 if (SubRegIndices.size() != 0)
881 OS << "extern const uint16_t *get" << TargetName
882 << "SubRegTable();\n";
884 OS << ClassName << "::\n" << ClassName
885 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
886 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
887 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
888 << " " << TargetName << "SubRegIndexTable) {\n"
889 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
890 << Regs.size()+1 << ", RA,\n " << TargetName
891 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
892 << " " << TargetName << "RegOverlaps, "
893 << TargetName << "SubRegsSet, " << TargetName << "SuperRegsSet,\n"
895 if (SubRegIndices.size() != 0)
896 OS << "get" << TargetName << "SubRegTable(), "
897 << SubRegIndices.size() << ");\n\n";
899 OS << "NULL, 0);\n\n";
901 EmitRegMapping(OS, Regs, true);
906 // Emit CalleeSavedRegs information.
907 std::vector<Record*> CSRSets =
908 Records.getAllDerivedDefinitions("CalleeSavedRegs");
909 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
910 Record *CSRSet = CSRSets[i];
911 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
912 assert(Regs && "Cannot expand CalleeSavedRegs instance");
914 // Emit the *_SaveList list of callee-saved registers.
915 OS << "static const uint16_t " << CSRSet->getName()
916 << "_SaveList[] = { ";
917 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
918 OS << getQualifiedName((*Regs)[r]) << ", ";
921 // Emit the *_RegMask bit mask of call-preserved registers.
922 OS << "static const uint32_t " << CSRSet->getName()
923 << "_RegMask[] = { ";
924 printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
929 OS << "} // End llvm namespace \n";
930 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
933 void RegisterInfoEmitter::run(raw_ostream &OS) {
934 CodeGenTarget Target(Records);
935 CodeGenRegBank &RegBank = Target.getRegBank();
936 RegBank.computeDerivedInfo();
938 runEnums(OS, Target, RegBank);
939 runMCDesc(OS, Target, RegBank);
940 runTargetHeader(OS, Target, RegBank);
941 runTargetDesc(OS, Target, RegBank);