1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Streams.h"
27 // runEnums - Print out enum values for all of the registers.
28 void RegisterInfoEmitter::runEnums(std::ostream &OS) {
30 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
32 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
34 EmitSourceFileHeader("Target Register Enum Values", OS);
35 OS << "namespace llvm {\n\n";
37 if (!Namespace.empty())
38 OS << "namespace " << Namespace << " {\n";
39 OS << " enum {\n NoRegister,\n";
41 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
42 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
43 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
45 if (!Namespace.empty())
47 OS << "} // End llvm namespace \n";
50 void RegisterInfoEmitter::runHeader(std::ostream &OS) {
51 EmitSourceFileHeader("Register Information Header Fragment", OS);
53 const std::string &TargetName = Target.getName();
54 std::string ClassName = TargetName + "GenRegisterInfo";
56 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
57 OS << "#include <string>\n\n";
59 OS << "namespace llvm {\n\n";
61 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
62 << " explicit " << ClassName
63 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
64 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
65 << "unsigned Flavour) const;\n"
66 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
67 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
68 << " { return false; }\n"
69 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
72 const std::vector<CodeGenRegisterClass> &RegisterClasses =
73 Target.getRegisterClasses();
75 if (!RegisterClasses.empty()) {
76 OS << "namespace " << RegisterClasses[0].Namespace
77 << " { // Register classes\n";
80 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
82 OS << " " << RegisterClasses[i].getName() << "RegClassID";
87 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
88 const std::string &Name = RegisterClasses[i].getName();
90 // Output the register class definition.
91 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
92 << " " << Name << "Class();\n"
93 << RegisterClasses[i].MethodProtos << " };\n";
95 // Output the extern for the instance.
96 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
97 // Output the extern for the pointer to the instance (should remove).
98 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
99 << Name << "RegClass;\n";
101 OS << "} // end of namespace " << TargetName << "\n\n";
103 OS << "} // End llvm namespace \n";
106 bool isSubRegisterClass(const CodeGenRegisterClass &RC,
107 std::set<Record*> &RegSet) {
108 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
109 Record *Reg = RC.Elements[i];
110 if (!RegSet.count(Reg))
116 static void addSuperReg(Record *R, Record *S,
117 std::map<Record*, std::set<Record*>,
118 LessRecord> &SubRegs,
119 std::map<Record*, std::set<Record*> > &SuperRegs,
120 std::map<Record*, std::set<Record*> > &Aliases) {
122 cerr << "Error: recursive sub-register relationship between"
123 << " register " << getQualifiedName(R)
124 << " and its sub-registers?\n";
127 if (!SuperRegs[R].insert(S).second)
129 SubRegs[S].insert(R);
130 Aliases[R].insert(S);
131 Aliases[S].insert(R);
132 if (SuperRegs.count(S))
133 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
134 E = SuperRegs[S].end(); I != E; ++I)
135 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
138 static void addSubSuperReg(Record *R, Record *S,
139 std::map<Record*, std::set<Record*>,
140 LessRecord> &SubRegs,
141 std::map<Record*, std::set<Record*> > &SuperRegs,
142 std::map<Record*, std::set<Record*> > &Aliases) {
144 cerr << "Error: recursive sub-register relationship between"
145 << " register " << getQualifiedName(R)
146 << " and its sub-registers?\n";
150 if (!SubRegs[R].insert(S).second)
152 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
153 Aliases[R].insert(S);
154 Aliases[S].insert(R);
155 if (SubRegs.count(S))
156 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
157 E = SubRegs[S].end(); I != E; ++I)
158 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
161 class RegisterSorter {
163 std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
166 RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
167 : RegisterSubRegs(RS) {};
169 bool operator()(Record *RegA, Record *RegB) {
170 // B is sub-register of A.
171 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
175 // RegisterInfoEmitter::run - Main register file description emitter.
177 void RegisterInfoEmitter::run(std::ostream &OS) {
178 CodeGenTarget Target;
179 EmitSourceFileHeader("Register Information Source Fragment", OS);
181 OS << "namespace llvm {\n\n";
183 // Start out by emitting each of the register classes... to do this, we build
184 // a set of registers which belong to a register class, this is to ensure that
185 // each register is only in a single register class.
187 const std::vector<CodeGenRegisterClass> &RegisterClasses =
188 Target.getRegisterClasses();
190 // Loop over all of the register classes... emitting each one.
191 OS << "namespace { // Register classes...\n";
193 // RegClassesBelongedTo - Keep track of which register classes each reg
195 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
197 // Emit the register enum value arrays for each RegisterClass
198 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
199 const CodeGenRegisterClass &RC = RegisterClasses[rc];
201 // Give the register class a legal C name if it's anonymous.
202 std::string Name = RC.TheDef->getName();
204 // Emit the register list now.
205 OS << " // " << Name << " Register Class...\n"
206 << " static const unsigned " << Name
208 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
209 Record *Reg = RC.Elements[i];
210 OS << getQualifiedName(Reg) << ", ";
212 // Keep track of which regclasses this register is in.
213 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
218 // Emit the ValueType arrays for each RegisterClass
219 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
220 const CodeGenRegisterClass &RC = RegisterClasses[rc];
222 // Give the register class a legal C name if it's anonymous.
223 std::string Name = RC.TheDef->getName() + "VTs";
225 // Emit the register list now.
227 << " Register Class Value Types...\n"
228 << " static const MVT " << Name
230 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
231 OS << getEnumName(RC.VTs[i]) << ", ";
232 OS << "MVT::Other\n };\n\n";
234 OS << "} // end anonymous namespace\n\n";
236 // Now that all of the structs have been emitted, emit the instances.
237 if (!RegisterClasses.empty()) {
238 OS << "namespace " << RegisterClasses[0].Namespace
239 << " { // Register class instances\n";
240 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
241 OS << " " << RegisterClasses[i].getName() << "Class\t"
242 << RegisterClasses[i].getName() << "RegClass;\n";
244 std::map<unsigned, std::set<unsigned> > SuperClassMap;
245 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
248 // Emit the sub-register classes for each RegisterClass
249 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
250 const CodeGenRegisterClass &RC = RegisterClasses[rc];
252 // Give the register class a legal C name if it's anonymous.
253 std::string Name = RC.TheDef->getName();
256 << " Sub-register Classess...\n"
257 << " static const TargetRegisterClass* const "
258 << Name << "SubRegClasses [] = {\n ";
262 for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size();
263 subrc != subrcMax; ++subrc) {
264 unsigned rc2 = 0, e2 = RegisterClasses.size();
265 for (; rc2 != e2; ++rc2) {
266 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
267 if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
270 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
273 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
274 SuperRegClassMap.find(rc2);
275 if (SCMI == SuperRegClassMap.end()) {
276 SuperRegClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
277 SCMI = SuperRegClassMap.find(rc2);
279 SCMI->second.insert(rc);
284 throw "Register Class member '" +
285 RC.SubRegClasses[subrc]->getName() +
286 "' is not a valid RegisterClass!";
289 OS << (!Empty ? ", " : "") << "NULL";
293 // Emit the super-register classes for each RegisterClass
294 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
295 const CodeGenRegisterClass &RC = RegisterClasses[rc];
297 // Give the register class a legal C name if it's anonymous.
298 std::string Name = RC.TheDef->getName();
301 << " Super-register Classess...\n"
302 << " static const TargetRegisterClass* const "
303 << Name << "SuperRegClasses [] = {\n ";
306 std::map<unsigned, std::set<unsigned> >::iterator I =
307 SuperRegClassMap.find(rc);
308 if (I != SuperRegClassMap.end()) {
309 for (std::set<unsigned>::iterator II = I->second.begin(),
310 EE = I->second.end(); II != EE; ++II) {
311 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
314 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
319 OS << (!Empty ? ", " : "") << "NULL";
323 // Emit the sub-classes array for each RegisterClass
324 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
325 const CodeGenRegisterClass &RC = RegisterClasses[rc];
327 // Give the register class a legal C name if it's anonymous.
328 std::string Name = RC.TheDef->getName();
330 std::set<Record*> RegSet;
331 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
332 Record *Reg = RC.Elements[i];
337 << " Register Class sub-classes...\n"
338 << " static const TargetRegisterClass* const "
339 << Name << "Subclasses [] = {\n ";
342 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
343 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
344 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
345 RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
348 if (!Empty) OS << ", ";
349 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
352 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
353 SuperClassMap.find(rc2);
354 if (SCMI == SuperClassMap.end()) {
355 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
356 SCMI = SuperClassMap.find(rc2);
358 SCMI->second.insert(rc);
361 OS << (!Empty ? ", " : "") << "NULL";
365 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
366 const CodeGenRegisterClass &RC = RegisterClasses[rc];
368 // Give the register class a legal C name if it's anonymous.
369 std::string Name = RC.TheDef->getName();
372 << " Register Class super-classes...\n"
373 << " static const TargetRegisterClass* const "
374 << Name << "Superclasses [] = {\n ";
377 std::map<unsigned, std::set<unsigned> >::iterator I =
378 SuperClassMap.find(rc);
379 if (I != SuperClassMap.end()) {
380 for (std::set<unsigned>::iterator II = I->second.begin(),
381 EE = I->second.end(); II != EE; ++II) {
382 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
383 if (!Empty) OS << ", ";
384 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
389 OS << (!Empty ? ", " : "") << "NULL";
394 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
395 const CodeGenRegisterClass &RC = RegisterClasses[i];
396 OS << RC.MethodBodies << "\n";
397 OS << RC.getName() << "Class::" << RC.getName()
398 << "Class() : TargetRegisterClass("
399 << RC.getName() + "RegClassID" << ", "
400 << RC.getName() + "VTs" << ", "
401 << RC.getName() + "Subclasses" << ", "
402 << RC.getName() + "Superclasses" << ", "
403 << RC.getName() + "SubRegClasses" << ", "
404 << RC.getName() + "SuperRegClasses" << ", "
405 << RC.SpillSize/8 << ", "
406 << RC.SpillAlignment/8 << ", "
407 << RC.CopyCost << ", "
408 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
415 OS << "\nnamespace {\n";
416 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
417 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
418 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
422 // Emit register sub-registers / super-registers, aliases...
423 std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
424 std::map<Record*, std::set<Record*> > RegisterSuperRegs;
425 std::map<Record*, std::set<Record*> > RegisterAliases;
426 std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
427 typedef std::map<Record*, std::vector<int>, LessRecord> DwarfRegNumsMapTy;
428 DwarfRegNumsMapTy DwarfRegNums;
430 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
432 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
433 Record *R = Regs[i].TheDef;
434 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
435 // Add information that R aliases all of the elements in the list... and
436 // that everything in the list aliases R.
437 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
439 if (RegisterAliases[R].count(Reg))
440 cerr << "Warning: register alias between " << getQualifiedName(R)
441 << " and " << getQualifiedName(Reg)
442 << " specified multiple times!\n";
443 RegisterAliases[R].insert(Reg);
445 if (RegisterAliases[Reg].count(R))
446 cerr << "Warning: register alias between " << getQualifiedName(R)
447 << " and " << getQualifiedName(Reg)
448 << " specified multiple times!\n";
449 RegisterAliases[Reg].insert(R);
453 // Process sub-register sets.
454 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
455 Record *R = Regs[i].TheDef;
456 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
457 // Process sub-register set and add aliases information.
458 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
459 Record *SubReg = LI[j];
460 if (RegisterSubRegs[R].count(SubReg))
461 cerr << "Warning: register " << getQualifiedName(SubReg)
462 << " specified as a sub-register of " << getQualifiedName(R)
463 << " multiple times!\n";
464 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
469 // Print the SubregHashTable, a simple quadratically probed
470 // hash table for determining if a register is a subregister
471 // of another register.
472 unsigned NumSubRegs = 0;
473 std::map<Record*, unsigned> RegNo;
474 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
475 RegNo[Regs[i].TheDef] = i;
476 NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
479 unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
480 unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
481 std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
483 unsigned hashMisses = 0;
485 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
486 Record* R = Regs[i].TheDef;
487 for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
488 E = RegisterSubRegs[R].end(); I != E; ++I) {
490 // We have to increase the indices of both registers by one when
491 // computing the hash because, in the generated code, there
492 // will be an extra empty slot at register 0.
493 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
494 unsigned ProbeAmt = 2;
495 while (SubregHashTable[index*2] != ~0U &&
496 SubregHashTable[index*2+1] != ~0U) {
497 index = (index + ProbeAmt) & (SubregHashTableSize-1);
503 SubregHashTable[index*2] = i;
504 SubregHashTable[index*2+1] = RegNo[RJ];
508 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
510 if (SubregHashTableSize) {
511 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
513 OS << " const unsigned SubregHashTable[] = { ";
514 for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
516 // Insert spaces for nice formatting.
519 if (SubregHashTable[2*i] != ~0U) {
520 OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
521 << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
523 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
527 unsigned Idx = SubregHashTableSize*2-2;
528 if (SubregHashTable[Idx] != ~0U) {
530 << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
531 << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
533 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
536 OS << " const unsigned SubregHashTableSize = "
537 << SubregHashTableSize << ";\n";
539 OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
540 << " const unsigned SubregHashTableSize = 1;\n";
543 delete [] SubregHashTable;
545 if (!RegisterAliases.empty())
546 OS << "\n\n // Register Alias Sets...\n";
548 // Emit the empty alias list
549 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
550 // Loop over all of the registers which have aliases, emitting the alias list
552 for (std::map<Record*, std::set<Record*> >::iterator
553 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
554 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
555 for (std::set<Record*>::iterator ASI = I->second.begin(),
556 E = I->second.end(); ASI != E; ++ASI)
557 OS << getQualifiedName(*ASI) << ", ";
561 if (!RegisterSubRegs.empty())
562 OS << "\n\n // Register Sub-registers Sets...\n";
564 // Emit the empty sub-registers list
565 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
566 // Loop over all of the registers which have sub-registers, emitting the
567 // sub-registers list to memory.
568 for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
569 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
570 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
571 std::vector<Record*> SubRegsVector;
572 for (std::set<Record*>::iterator ASI = I->second.begin(),
573 E = I->second.end(); ASI != E; ++ASI)
574 SubRegsVector.push_back(*ASI);
575 RegisterSorter RS(RegisterSubRegs);
576 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
577 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
578 OS << getQualifiedName(SubRegsVector[i]) << ", ";
582 if (!RegisterSuperRegs.empty())
583 OS << "\n\n // Register Super-registers Sets...\n";
585 // Emit the empty super-registers list
586 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
587 // Loop over all of the registers which have super-registers, emitting the
588 // super-registers list to memory.
589 for (std::map<Record*, std::set<Record*> >::iterator
590 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
591 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
593 std::vector<Record*> SuperRegsVector;
594 for (std::set<Record*>::iterator ASI = I->second.begin(),
595 E = I->second.end(); ASI != E; ++ASI)
596 SuperRegsVector.push_back(*ASI);
597 RegisterSorter RS(RegisterSubRegs);
598 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
599 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
600 OS << getQualifiedName(SuperRegsVector[i]) << ", ";
604 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
605 OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n";
607 // Now that register alias and sub-registers sets have been emitted, emit the
608 // register descriptors now.
609 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
610 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
611 const CodeGenRegister &Reg = Registers[i];
613 if (!Reg.TheDef->getValueAsString("AsmName").empty())
614 OS << Reg.TheDef->getValueAsString("AsmName");
618 OS << Reg.getName() << "\",\t";
619 if (RegisterAliases.count(Reg.TheDef))
620 OS << Reg.getName() << "_AliasSet,\t";
622 OS << "Empty_AliasSet,\t";
623 if (RegisterSubRegs.count(Reg.TheDef))
624 OS << Reg.getName() << "_SubRegsSet,\t";
626 OS << "Empty_SubRegsSet,\t";
627 if (RegisterSuperRegs.count(Reg.TheDef))
628 OS << Reg.getName() << "_SuperRegsSet },\n";
630 OS << "Empty_SuperRegsSet },\n";
632 OS << " };\n"; // End of register descriptors...
633 OS << "}\n\n"; // End of anonymous namespace...
635 std::string ClassName = Target.getName() + "GenRegisterInfo";
637 // Calculate the mapping of subregister+index pairs to physical registers.
638 std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
639 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
640 int subRegIndex = SubRegs[i]->getValueAsInt("index");
641 std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
642 std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
644 if (From.size() != To.size()) {
645 cerr << "Error: register list and sub-register list not of equal length"
646 << " in SubRegSet\n";
650 // For each entry in from/to vectors, insert the to register at index
651 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
652 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
655 // Emit the subregister + index mapping function based on the information
657 OS << "unsigned " << ClassName
658 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
659 << " switch (RegNo) {\n"
660 << " default: abort(); break;\n";
661 for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
662 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
663 OS << " case " << getQualifiedName(I->first) << ":\n";
664 OS << " switch (Index) {\n";
665 OS << " default: abort(); break;\n";
666 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
667 OS << " case " << (I->second)[i].first << ": return "
668 << getQualifiedName((I->second)[i].second) << ";\n";
669 OS << " }; break;\n";
672 OS << " return 0;\n";
675 // Emit the constructor of the class...
676 OS << ClassName << "::" << ClassName
677 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
678 << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
679 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
680 << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
681 << " SubregHashTable, SubregHashTableSize) {\n"
684 // Collect all information about dwarf register numbers
686 // First, just pull all provided information to the map
687 unsigned maxLength = 0;
688 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
689 Record *Reg = Registers[i].TheDef;
690 std::vector<int> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
691 maxLength = std::max((size_t)maxLength, RegNums.size());
692 if (DwarfRegNums.count(Reg))
693 cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
694 << "specified multiple times\n";
695 DwarfRegNums[Reg] = RegNums;
698 // Now we know maximal length of number list. Append -1's, where needed
699 for (DwarfRegNumsMapTy::iterator
700 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
701 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
702 I->second.push_back(-1);
704 // Emit information about the dwarf register numbers.
705 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
706 << "unsigned Flavour) const {\n"
707 << " switch (Flavour) {\n"
709 << " assert(0 && \"Unknown DWARF flavour\");\n"
712 for (unsigned i = 0, e = maxLength; i != e; ++i) {
713 OS << " case " << i << ":\n"
714 << " switch (RegNum) {\n"
716 << " assert(0 && \"Invalid RegNum\");\n"
719 // Sort by name to get a stable order.
722 for (DwarfRegNumsMapTy::iterator
723 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
724 int RegNo = I->second[i];
726 OS << " case " << getQualifiedName(I->first) << ":\n"
727 << " return " << RegNo << ";\n";
729 OS << " case " << getQualifiedName(I->first) << ":\n"
730 << " assert(0 && \"Invalid register for this mode\");\n"
738 OS << "} // End llvm namespace \n";