1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Streams.h"
26 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(std::ostream &OS) {
29 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
31 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
33 EmitSourceFileHeader("Target Register Enum Values", OS);
34 OS << "namespace llvm {\n\n";
36 if (!Namespace.empty())
37 OS << "namespace " << Namespace << " {\n";
38 OS << " enum {\n NoRegister,\n";
40 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
41 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
42 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
44 if (!Namespace.empty())
46 OS << "} // End llvm namespace \n";
49 void RegisterInfoEmitter::runHeader(std::ostream &OS) {
50 EmitSourceFileHeader("Register Information Header Fragment", OS);
52 const std::string &TargetName = Target.getName();
53 std::string ClassName = TargetName + "GenRegisterInfo";
55 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
56 OS << "#include <string>\n\n";
58 OS << "namespace llvm {\n\n";
60 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
61 << " explicit " << ClassName
62 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
63 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
64 << "unsigned Flavour) const;\n"
65 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
66 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
69 const std::vector<CodeGenRegisterClass> &RegisterClasses =
70 Target.getRegisterClasses();
72 if (!RegisterClasses.empty()) {
73 OS << "namespace " << RegisterClasses[0].Namespace
74 << " { // Register classes\n";
77 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
79 OS << " " << RegisterClasses[i].getName() << "RegClassID";
84 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
85 const std::string &Name = RegisterClasses[i].getName();
87 // Output the register class definition.
88 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
89 << " " << Name << "Class();\n"
90 << RegisterClasses[i].MethodProtos << " };\n";
92 // Output the extern for the instance.
93 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
94 // Output the extern for the pointer to the instance (should remove).
95 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
96 << Name << "RegClass;\n";
98 OS << "} // end of namespace " << TargetName << "\n\n";
100 OS << "} // End llvm namespace \n";
103 bool isSubRegisterClass(const CodeGenRegisterClass &RC,
104 std::set<Record*> &RegSet) {
105 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
106 Record *Reg = RC.Elements[i];
107 if (!RegSet.count(Reg))
113 static void addSuperReg(Record *R, Record *S,
114 std::map<Record*, std::set<Record*> > &SubRegs,
115 std::map<Record*, std::set<Record*> > &SuperRegs,
116 std::map<Record*, std::set<Record*> > &Aliases) {
118 cerr << "Error: recursive sub-register relationship between"
119 << " register " << getQualifiedName(R)
120 << " and its sub-registers?\n";
123 if (!SuperRegs[R].insert(S).second)
125 SubRegs[S].insert(R);
126 Aliases[R].insert(S);
127 Aliases[S].insert(R);
128 if (SuperRegs.count(S))
129 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
130 E = SuperRegs[S].end(); I != E; ++I)
131 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
134 static void addSubSuperReg(Record *R, Record *S,
135 std::map<Record*, std::set<Record*> > &SubRegs,
136 std::map<Record*, std::set<Record*> > &SuperRegs,
137 std::map<Record*, std::set<Record*> > &Aliases) {
139 cerr << "Error: recursive sub-register relationship between"
140 << " register " << getQualifiedName(R)
141 << " and its sub-registers?\n";
145 if (!SubRegs[R].insert(S).second)
147 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
148 Aliases[R].insert(S);
149 Aliases[S].insert(R);
150 if (SubRegs.count(S))
151 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
152 E = SubRegs[S].end(); I != E; ++I)
153 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
156 class RegisterSorter {
158 std::map<Record*, std::set<Record*> > &RegisterSubRegs;
161 RegisterSorter(std::map<Record*, std::set<Record*> > &RS)
162 : RegisterSubRegs(RS) {};
164 bool operator()(Record *RegA, Record *RegB) {
165 // B is sub-register of A.
166 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
170 // RegisterInfoEmitter::run - Main register file description emitter.
172 void RegisterInfoEmitter::run(std::ostream &OS) {
173 CodeGenTarget Target;
174 EmitSourceFileHeader("Register Information Source Fragment", OS);
176 OS << "namespace llvm {\n\n";
178 // Start out by emitting each of the register classes... to do this, we build
179 // a set of registers which belong to a register class, this is to ensure that
180 // each register is only in a single register class.
182 const std::vector<CodeGenRegisterClass> &RegisterClasses =
183 Target.getRegisterClasses();
185 // Loop over all of the register classes... emitting each one.
186 OS << "namespace { // Register classes...\n";
188 // RegClassesBelongedTo - Keep track of which register classes each reg
190 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
192 // Emit the register enum value arrays for each RegisterClass
193 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
194 const CodeGenRegisterClass &RC = RegisterClasses[rc];
196 // Give the register class a legal C name if it's anonymous.
197 std::string Name = RC.TheDef->getName();
199 // Emit the register list now.
200 OS << " // " << Name << " Register Class...\n"
201 << " static const unsigned " << Name
203 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
204 Record *Reg = RC.Elements[i];
205 OS << getQualifiedName(Reg) << ", ";
207 // Keep track of which regclasses this register is in.
208 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
213 // Emit the ValueType arrays for each RegisterClass
214 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
215 const CodeGenRegisterClass &RC = RegisterClasses[rc];
217 // Give the register class a legal C name if it's anonymous.
218 std::string Name = RC.TheDef->getName() + "VTs";
220 // Emit the register list now.
222 << " Register Class Value Types...\n"
223 << " static const MVT::ValueType " << Name
225 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
226 OS << getEnumName(RC.VTs[i]) << ", ";
227 OS << "MVT::Other\n };\n\n";
229 OS << "} // end anonymous namespace\n\n";
231 // Now that all of the structs have been emitted, emit the instances.
232 if (!RegisterClasses.empty()) {
233 OS << "namespace " << RegisterClasses[0].Namespace
234 << " { // Register class instances\n";
235 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
236 OS << " " << RegisterClasses[i].getName() << "Class\t"
237 << RegisterClasses[i].getName() << "RegClass;\n";
239 std::map<unsigned, std::set<unsigned> > SuperClassMap;
240 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
243 // Emit the sub-register classes for each RegisterClass
244 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
245 const CodeGenRegisterClass &RC = RegisterClasses[rc];
247 // Give the register class a legal C name if it's anonymous.
248 std::string Name = RC.TheDef->getName();
251 << " Sub-register Classess...\n"
252 << " static const TargetRegisterClass* const "
253 << Name << "SubRegClasses [] = {\n ";
257 for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size();
258 subrc != subrcMax; ++subrc) {
259 unsigned rc2 = 0, e2 = RegisterClasses.size();
260 for (; rc2 != e2; ++rc2) {
261 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
262 if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
265 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
268 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
269 SuperRegClassMap.find(rc2);
270 if (SCMI == SuperRegClassMap.end()) {
271 SuperRegClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
272 SCMI = SuperRegClassMap.find(rc2);
274 SCMI->second.insert(rc);
279 throw "Register Class member '" +
280 RC.SubRegClasses[subrc]->getName() +
281 "' is not a valid RegisterClass!";
284 OS << (!Empty ? ", " : "") << "NULL";
288 // Emit the super-register classes for each RegisterClass
289 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
290 const CodeGenRegisterClass &RC = RegisterClasses[rc];
292 // Give the register class a legal C name if it's anonymous.
293 std::string Name = RC.TheDef->getName();
296 << " Super-register Classess...\n"
297 << " static const TargetRegisterClass* const "
298 << Name << "SuperRegClasses [] = {\n ";
301 std::map<unsigned, std::set<unsigned> >::iterator I =
302 SuperRegClassMap.find(rc);
303 if (I != SuperRegClassMap.end()) {
304 for (std::set<unsigned>::iterator II = I->second.begin(),
305 EE = I->second.end(); II != EE; ++II) {
306 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
309 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
314 OS << (!Empty ? ", " : "") << "NULL";
318 // Emit the sub-classes array for each RegisterClass
319 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
320 const CodeGenRegisterClass &RC = RegisterClasses[rc];
322 // Give the register class a legal C name if it's anonymous.
323 std::string Name = RC.TheDef->getName();
325 std::set<Record*> RegSet;
326 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
327 Record *Reg = RC.Elements[i];
332 << " Register Class sub-classes...\n"
333 << " static const TargetRegisterClass* const "
334 << Name << "Subclasses [] = {\n ";
337 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
338 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
339 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
340 RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
343 if (!Empty) OS << ", ";
344 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
347 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
348 SuperClassMap.find(rc2);
349 if (SCMI == SuperClassMap.end()) {
350 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
351 SCMI = SuperClassMap.find(rc2);
353 SCMI->second.insert(rc);
356 OS << (!Empty ? ", " : "") << "NULL";
360 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
361 const CodeGenRegisterClass &RC = RegisterClasses[rc];
363 // Give the register class a legal C name if it's anonymous.
364 std::string Name = RC.TheDef->getName();
367 << " Register Class super-classes...\n"
368 << " static const TargetRegisterClass* const "
369 << Name << "Superclasses [] = {\n ";
372 std::map<unsigned, std::set<unsigned> >::iterator I =
373 SuperClassMap.find(rc);
374 if (I != SuperClassMap.end()) {
375 for (std::set<unsigned>::iterator II = I->second.begin(),
376 EE = I->second.end(); II != EE; ++II) {
377 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
378 if (!Empty) OS << ", ";
379 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
384 OS << (!Empty ? ", " : "") << "NULL";
389 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
390 const CodeGenRegisterClass &RC = RegisterClasses[i];
391 OS << RC.MethodBodies << "\n";
392 OS << RC.getName() << "Class::" << RC.getName()
393 << "Class() : TargetRegisterClass("
394 << RC.getName() + "RegClassID" << ", "
395 << RC.getName() + "VTs" << ", "
396 << RC.getName() + "Subclasses" << ", "
397 << RC.getName() + "Superclasses" << ", "
398 << RC.getName() + "SubRegClasses" << ", "
399 << RC.getName() + "SuperRegClasses" << ", "
400 << RC.SpillSize/8 << ", "
401 << RC.SpillAlignment/8 << ", "
402 << RC.CopyCost << ", "
403 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
410 OS << "\nnamespace {\n";
411 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
412 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
413 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
417 // Emit register sub-registers / super-registers, aliases...
418 std::map<Record*, std::set<Record*> > RegisterImmSubRegs;
419 std::map<Record*, std::set<Record*> > RegisterSubRegs;
420 std::map<Record*, std::set<Record*> > RegisterSuperRegs;
421 std::map<Record*, std::set<Record*> > RegisterAliases;
422 std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
423 std::map<Record*, std::vector<int> > DwarfRegNums;
425 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
427 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
428 Record *R = Regs[i].TheDef;
429 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
430 // Add information that R aliases all of the elements in the list... and
431 // that everything in the list aliases R.
432 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
434 if (RegisterAliases[R].count(Reg))
435 cerr << "Warning: register alias between " << getQualifiedName(R)
436 << " and " << getQualifiedName(Reg)
437 << " specified multiple times!\n";
438 RegisterAliases[R].insert(Reg);
440 if (RegisterAliases[Reg].count(R))
441 cerr << "Warning: register alias between " << getQualifiedName(R)
442 << " and " << getQualifiedName(Reg)
443 << " specified multiple times!\n";
444 RegisterAliases[Reg].insert(R);
448 // Process sub-register sets.
449 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
450 Record *R = Regs[i].TheDef;
451 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
452 // Process sub-register set and add aliases information.
453 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
454 Record *SubReg = LI[j];
455 if (RegisterSubRegs[R].count(SubReg))
456 cerr << "Warning: register " << getQualifiedName(SubReg)
457 << " specified as a sub-register of " << getQualifiedName(R)
458 << " multiple times!\n";
459 RegisterImmSubRegs[R].insert(SubReg);
460 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
465 if (!RegisterAliases.empty())
466 OS << "\n\n // Register Alias Sets...\n";
468 // Emit the empty alias list
469 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
470 // Loop over all of the registers which have aliases, emitting the alias list
472 for (std::map<Record*, std::set<Record*> >::iterator
473 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
474 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
475 for (std::set<Record*>::iterator ASI = I->second.begin(),
476 E = I->second.end(); ASI != E; ++ASI)
477 OS << getQualifiedName(*ASI) << ", ";
481 if (!RegisterSubRegs.empty())
482 OS << "\n\n // Register Sub-registers Sets...\n";
484 // Emit the empty sub-registers list
485 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
486 // Loop over all of the registers which have sub-registers, emitting the
487 // sub-registers list to memory.
488 for (std::map<Record*, std::set<Record*> >::iterator
489 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
490 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
491 std::vector<Record*> SubRegsVector;
492 for (std::set<Record*>::iterator ASI = I->second.begin(),
493 E = I->second.end(); ASI != E; ++ASI)
494 SubRegsVector.push_back(*ASI);
495 RegisterSorter RS(RegisterSubRegs);
496 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
497 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
498 OS << getQualifiedName(SubRegsVector[i]) << ", ";
502 if (!RegisterImmSubRegs.empty())
503 OS << "\n\n // Register Immediate Sub-registers Sets...\n";
505 // Loop over all of the registers which have sub-registers, emitting the
506 // sub-registers list to memory.
507 for (std::map<Record*, std::set<Record*> >::iterator
508 I = RegisterImmSubRegs.begin(), E = RegisterImmSubRegs.end();
510 OS << " const unsigned " << I->first->getName() << "_ImmSubRegsSet[] = { ";
511 for (std::set<Record*>::iterator ASI = I->second.begin(),
512 E = I->second.end(); ASI != E; ++ASI)
513 OS << getQualifiedName(*ASI) << ", ";
517 if (!RegisterSuperRegs.empty())
518 OS << "\n\n // Register Super-registers Sets...\n";
520 // Emit the empty super-registers list
521 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
522 // Loop over all of the registers which have super-registers, emitting the
523 // super-registers list to memory.
524 for (std::map<Record*, std::set<Record*> >::iterator
525 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
526 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
528 std::vector<Record*> SuperRegsVector;
529 for (std::set<Record*>::iterator ASI = I->second.begin(),
530 E = I->second.end(); ASI != E; ++ASI)
531 SuperRegsVector.push_back(*ASI);
532 RegisterSorter RS(RegisterSubRegs);
533 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
534 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
535 OS << getQualifiedName(SuperRegsVector[i]) << ", ";
539 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
540 OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0,\t0 },\n";
542 // Now that register alias and sub-registers sets have been emitted, emit the
543 // register descriptors now.
544 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
545 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
546 const CodeGenRegister &Reg = Registers[i];
548 if (!Reg.TheDef->getValueAsString("AsmName").empty())
549 OS << Reg.TheDef->getValueAsString("AsmName");
553 if (!Reg.TheDef->getValueAsString("Name").empty()) {
554 OS << Reg.TheDef->getValueAsString("Name");
556 // Default to "name".
557 if (!Reg.TheDef->getValueAsString("AsmName").empty())
558 OS << Reg.TheDef->getValueAsString("AsmName");
563 if (RegisterAliases.count(Reg.TheDef))
564 OS << Reg.getName() << "_AliasSet,\t";
566 OS << "Empty_AliasSet,\t";
567 if (RegisterSubRegs.count(Reg.TheDef))
568 OS << Reg.getName() << "_SubRegsSet,\t";
570 OS << "Empty_SubRegsSet,\t";
571 if (RegisterImmSubRegs.count(Reg.TheDef))
572 OS << Reg.getName() << "_ImmSubRegsSet,\t";
574 OS << "Empty_SubRegsSet,\t";
575 if (RegisterSuperRegs.count(Reg.TheDef))
576 OS << Reg.getName() << "_SuperRegsSet },\n";
578 OS << "Empty_SuperRegsSet },\n";
580 OS << " };\n"; // End of register descriptors...
581 OS << "}\n\n"; // End of anonymous namespace...
583 std::string ClassName = Target.getName() + "GenRegisterInfo";
585 // Calculate the mapping of subregister+index pairs to physical registers.
586 std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
587 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
588 int subRegIndex = SubRegs[i]->getValueAsInt("index");
589 std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
590 std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
592 if (From.size() != To.size()) {
593 cerr << "Error: register list and sub-register list not of equal length"
594 << " in SubRegSet\n";
598 // For each entry in from/to vectors, insert the to register at index
599 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
600 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
603 // Emit the subregister + index mapping function based on the information
605 OS << "unsigned " << ClassName
606 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
607 << " switch (RegNo) {\n"
608 << " default: abort(); break;\n";
609 for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
610 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
611 OS << " case " << getQualifiedName(I->first) << ":\n";
612 OS << " switch (Index) {\n";
613 OS << " default: abort(); break;\n";
614 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
615 OS << " case " << (I->second)[i].first << ": return "
616 << getQualifiedName((I->second)[i].second) << ";\n";
617 OS << " }; break;\n";
620 OS << " return 0;\n";
623 // Emit the constructor of the class...
624 OS << ClassName << "::" << ClassName
625 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
626 << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
627 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
628 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
630 // Collect all information about dwarf register numbers
632 // First, just pull all provided information to the map
633 unsigned maxLength = 0;
634 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
635 Record *Reg = Registers[i].TheDef;
636 std::vector<int> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
637 maxLength = std::max((size_t)maxLength, RegNums.size());
638 if (DwarfRegNums.count(Reg))
639 cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
640 << "specified multiple times\n";
641 DwarfRegNums[Reg] = RegNums;
644 // Now we know maximal length of number list. Append -1's, where needed
645 for (std::map<Record*, std::vector<int> >::iterator
646 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
647 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
648 I->second.push_back(-1);
650 // Emit information about the dwarf register numbers.
651 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
652 << "unsigned Flavour) const {\n"
653 << " switch (Flavour) {\n"
655 << " assert(0 && \"Unknown DWARF flavour\");\n"
658 for (unsigned i = 0, e = maxLength; i != e; ++i) {
659 OS << " case " << i << ":\n"
660 << " switch (RegNum) {\n"
662 << " assert(0 && \"Invalid RegNum\");\n"
665 for (std::map<Record*, std::vector<int> >::iterator
666 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
667 int RegNo = I->second[i];
669 OS << " case " << getQualifiedName(I->first) << ":\n"
670 << " return " << RegNo << ";\n";
672 OS << " case " << getQualifiedName(I->first) << ":\n"
673 << " assert(0 && \"Invalid register for this mode\");\n"
681 OS << "} // End llvm namespace \n";