1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
25 // runEnums - Print out enum values for all of the registers.
26 void RegisterInfoEmitter::runEnums(std::ostream &OS) {
28 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
30 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
32 EmitSourceFileHeader("Target Register Enum Values", OS);
33 OS << "namespace llvm {\n\n";
35 if (!Namespace.empty())
36 OS << "namespace " << Namespace << " {\n";
37 OS << " enum {\n NoRegister,\n";
39 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
40 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
43 if (!Namespace.empty())
45 OS << "} // End llvm namespace \n";
48 void RegisterInfoEmitter::runHeader(std::ostream &OS) {
49 EmitSourceFileHeader("Register Information Header Fragment", OS);
51 const std::string &TargetName = Target.getName();
52 std::string ClassName = TargetName + "GenRegisterInfo";
54 OS << "#include \"llvm/Target/MRegisterInfo.h\"\n\n";
56 OS << "namespace llvm {\n\n";
58 OS << "struct " << ClassName << " : public MRegisterInfo {\n"
60 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
61 << " const unsigned* getCalleeSaveRegs() const;\n"
64 std::vector<Record*> RegisterClasses =
65 Records.getAllDerivedDefinitions("RegisterClass");
67 OS << "namespace " << TargetName << " { // Register classes\n";
68 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
69 const std::string &Name = RegisterClasses[i]->getName();
70 if (Name.size() < 9 || Name[9] != '.') // Ignore anonymous classes
71 OS << " extern TargetRegisterClass *" << Name << "RegisterClass;\n";
73 OS << "} // end of namespace " << TargetName << "\n\n";
74 OS << "} // End llvm namespace \n";
77 // RegisterInfoEmitter::run - Main register file description emitter.
79 void RegisterInfoEmitter::run(std::ostream &OS) {
81 EmitSourceFileHeader("Register Information Source Fragment", OS);
83 OS << "namespace llvm {\n\n";
85 // Start out by emitting each of the register classes... to do this, we build
86 // a set of registers which belong to a register class, this is to ensure that
87 // each register is only in a single register class.
89 const std::vector<CodeGenRegisterClass> &RegisterClasses =
90 Target.getRegisterClasses();
92 std::set<Record*> RegistersFound;
93 std::vector<std::string> RegClassNames;
95 // Loop over all of the register classes... emitting each one.
96 OS << "namespace { // Register classes...\n";
98 // RegClassesBelongedTo - Keep track of which register classes each reg
100 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
102 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
103 const CodeGenRegisterClass &RC = RegisterClasses[rc];
105 std::string Name = RC.getName();
106 if (Name.size() > 9 && Name[9] == '.') {
107 static unsigned AnonCounter = 0;
108 Name = "AnonRegClass_"+utostr(AnonCounter++);
111 RegClassNames.push_back(Name);
113 // Emit the register list now...
114 OS << " // " << Name << " Register Class...\n const unsigned " << Name
116 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
117 Record *Reg = RC.Elements[i];
118 if (RegistersFound.count(Reg))
119 throw "Register '" + Reg->getName() +
120 "' included in multiple register classes!";
121 RegistersFound.insert(Reg);
122 OS << getQualifiedName(Reg) << ", ";
124 // Keep track of which regclasses this register is in.
125 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
129 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
130 << " " << Name << "Class() : TargetRegisterClass("
131 << RC.SpillSize/8 << ", " << RC.SpillAlignment/8 << ", " << Name << ", "
132 << Name << " + " << RC.Elements.size() << ") {}\n"
133 << RC.MethodDefinitions << " } " << Name << "Instance;\n\n";
136 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
137 for (unsigned i = 0, e = RegClassNames.size(); i != e; ++i)
138 OS << " &" << RegClassNames[i] << "Instance,\n";
141 // Emit register class aliases...
142 std::map<Record*, std::set<Record*> > RegisterAliases;
143 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
145 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
146 Record *R = Regs[i].TheDef;
147 ListInit *LI = Regs[i].TheDef->getValueAsListInit("Aliases");
148 // Add information that R aliases all of the elements in the list... and
149 // that everything in the list aliases R.
150 for (unsigned j = 0, e = LI->getSize(); j != e; ++j) {
151 DefInit *Reg = dynamic_cast<DefInit*>(LI->getElement(j));
152 if (!Reg) throw "ERROR: Alias list element is not a def!";
153 if (RegisterAliases[R].count(Reg->getDef()))
154 std::cerr << "Warning: register alias between " << getQualifiedName(R)
155 << " and " << getQualifiedName(Reg->getDef())
156 << " specified multiple times!\n";
157 RegisterAliases[R].insert(Reg->getDef());
159 if (RegisterAliases[Reg->getDef()].count(R))
160 std::cerr << "Warning: register alias between " << getQualifiedName(R)
161 << " and " << getQualifiedName(Reg->getDef())
162 << " specified multiple times!\n";
163 RegisterAliases[Reg->getDef()].insert(R);
167 if (!RegisterAliases.empty())
168 OS << "\n\n // Register Alias Sets...\n";
170 // Emit the empty alias list
171 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
172 // Loop over all of the registers which have aliases, emitting the alias list
174 for (std::map<Record*, std::set<Record*> >::iterator
175 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
176 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
177 for (std::set<Record*>::iterator ASI = I->second.begin(),
178 E = I->second.end(); ASI != E; ++ASI)
179 OS << getQualifiedName(*ASI) << ", ";
183 OS << "\n const MRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
184 OS << " { \"NOREG\",\t0,\t\t0,\t0 },\n";
187 // Now that register alias sets have been emitted, emit the register
189 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
190 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
191 const CodeGenRegister &Reg = Registers[i];
193 if (!Reg.TheDef->getValueAsString("Name").empty())
194 OS << Reg.TheDef->getValueAsString("Name");
198 if (RegisterAliases.count(Reg.TheDef))
199 OS << Reg.getName() << "_AliasSet,\t";
201 OS << "Empty_AliasSet,\t";
203 // Figure out what the size and alignment of the spill slots are for this
204 // reg. This may be explicitly declared in the register, or it may be
205 // inferred from the register classes it is part of.
206 std::multimap<Record*, const CodeGenRegisterClass*>::iterator I, E;
207 tie(I, E) = RegClassesBelongedTo.equal_range(Reg.TheDef);
208 unsigned SpillSize = Reg.DeclaredSpillSize;
209 unsigned SpillAlign = Reg.DeclaredSpillAlignment;
210 for (; I != E; ++I) { // For each reg class this belongs to.
211 const CodeGenRegisterClass *RC = I->second;
213 SpillSize = RC->SpillSize;
214 else if (SpillSize != RC->SpillSize)
215 throw "Spill size for regclass '" + RC->getName() +
216 "' doesn't match spill sized already inferred for register '" +
217 Reg.getName() + "'!";
219 SpillAlign = RC->SpillAlignment;
220 else if (SpillAlign != RC->SpillAlignment)
221 throw "Spill alignment for regclass '" + RC->getName() +
222 "' doesn't match spill sized already inferred for register '" +
223 Reg.getName() + "'!";
226 OS << SpillSize << ", " << SpillAlign << " },\n";
228 OS << " };\n"; // End of register descriptors...
229 OS << "}\n\n"; // End of anonymous namespace...
231 OS << "namespace " << Target.getName() << " { // Register classes\n";
232 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
233 const std::string &Name = RegisterClasses[i].getName();
234 if (Name.size() < 9 || Name[9] != '.') // Ignore anonymous classes
235 OS << " TargetRegisterClass *" << Name << "RegisterClass = &"
236 << Name << "Instance;\n";
238 OS << "} // end of namespace " << Target.getName() << "\n\n";
242 std::string ClassName = Target.getName() + "GenRegisterInfo";
244 // Emit the constructor of the class...
245 OS << ClassName << "::" << ClassName
246 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
247 << " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1
248 << ", RegisterClasses, RegisterClasses+" << RegClassNames.size() << ",\n "
249 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
251 // Emit the getCalleeSaveRegs method...
252 OS << "const unsigned* " << ClassName << "::getCalleeSaveRegs() const {\n"
253 << " static const unsigned CalleeSaveRegs[] = {\n ";
255 const std::vector<Record*> &CSR = Target.getCalleeSavedRegisters();
256 for (unsigned i = 0, e = CSR.size(); i != e; ++i)
257 OS << getQualifiedName(CSR[i]) << ", ";
258 OS << " 0\n };\n return CalleeSaveRegs;\n}\n\n";
259 OS << "} // End llvm namespace \n";