1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Format.h"
27 // runEnums - Print out enum values for all of the registers.
28 void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
29 CodeGenTarget Target(Records);
30 CodeGenRegBank &Bank = Target.getRegBank();
31 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
33 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
35 EmitSourceFileHeader("Target Register Enum Values", OS);
36 OS << "namespace llvm {\n\n";
38 if (!Namespace.empty())
39 OS << "namespace " << Namespace << " {\n";
40 OS << "enum {\n NoRegister,\n";
42 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
43 OS << " " << Registers[i].getName() << " = " <<
44 Registers[i].EnumValue << ",\n";
45 assert(Registers.size() == Registers[Registers.size()-1].EnumValue &&
46 "Register enum value mismatch!");
47 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
49 if (!Namespace.empty())
52 const std::vector<Record*> &SubRegIndices = Bank.getSubRegIndices();
53 if (!SubRegIndices.empty()) {
54 OS << "\n// Subregister indices\n";
55 Namespace = SubRegIndices[0]->getValueAsString("Namespace");
56 if (!Namespace.empty())
57 OS << "namespace " << Namespace << " {\n";
58 OS << "enum {\n NoSubRegister,\n";
59 for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
60 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
61 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
63 if (!Namespace.empty())
66 OS << "} // End llvm namespace \n";
69 void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
70 EmitSourceFileHeader("Register Information Header Fragment", OS);
71 CodeGenTarget Target(Records);
72 const std::string &TargetName = Target.getName();
73 std::string ClassName = TargetName + "GenRegisterInfo";
75 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
76 OS << "#include <string>\n\n";
78 OS << "namespace llvm {\n\n";
80 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
81 << " explicit " << ClassName
82 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
83 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
84 << "unsigned Flavour) const;\n"
85 << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
86 << "unsigned Flavour) const;\n"
87 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
88 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
89 << " { return false; }\n"
90 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
91 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
92 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
95 const std::vector<CodeGenRegisterClass> &RegisterClasses =
96 Target.getRegisterClasses();
98 if (!RegisterClasses.empty()) {
99 OS << "namespace " << RegisterClasses[0].Namespace
100 << " { // Register classes\n";
103 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
105 OS << " " << RegisterClasses[i].getName() << "RegClassID";
110 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
111 const std::string &Name = RegisterClasses[i].getName();
113 // Output the register class definition.
114 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
115 << " " << Name << "Class();\n"
116 << RegisterClasses[i].MethodProtos << " };\n";
118 // Output the extern for the instance.
119 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
120 // Output the extern for the pointer to the instance (should remove).
121 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
122 << Name << "RegClass;\n";
124 OS << "} // end of namespace " << TargetName << "\n\n";
126 OS << "} // End llvm namespace \n";
129 typedef std::pair<unsigned, unsigned> UUPair;
130 typedef std::vector<UUPair> UUVector;
133 // RegisterInfoEmitter::run - Main register file description emitter.
135 void RegisterInfoEmitter::run(raw_ostream &OS) {
136 CodeGenTarget Target(Records);
137 CodeGenRegBank &RegBank = Target.getRegBank();
138 RegBank.computeDerivedInfo();
139 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
140 RegBank.computeOverlaps(Overlaps);
142 EmitSourceFileHeader("Register Information Source Fragment", OS);
144 OS << "namespace llvm {\n\n";
146 // Start out by emitting each of the register classes.
147 const std::vector<CodeGenRegisterClass> &RegisterClasses =
148 Target.getRegisterClasses();
150 // Collect all registers belonging to any allocatable class.
151 std::set<Record*> AllocatableRegs;
153 // Loop over all of the register classes... emitting each one.
154 OS << "namespace { // Register classes...\n";
156 // Emit the register enum value arrays for each RegisterClass
157 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
158 const CodeGenRegisterClass &RC = RegisterClasses[rc];
159 ArrayRef<Record*> Order = RC.getOrder();
161 // Collect allocatable registers.
163 AllocatableRegs.insert(Order.begin(), Order.end());
165 // Give the register class a legal C name if it's anonymous.
166 std::string Name = RC.getName();
168 // Emit the register list now.
169 OS << " // " << Name << " Register Class...\n"
170 << " static const unsigned " << Name
172 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
173 Record *Reg = Order[i];
174 OS << getQualifiedName(Reg) << ", ";
179 // Emit the ValueType arrays for each RegisterClass
180 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
181 const CodeGenRegisterClass &RC = RegisterClasses[rc];
183 // Give the register class a legal C name if it's anonymous.
184 std::string Name = RC.getName() + "VTs";
186 // Emit the register list now.
188 << " Register Class Value Types...\n"
189 << " static const EVT " << Name
191 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
192 OS << getEnumName(RC.VTs[i]) << ", ";
193 OS << "MVT::Other\n };\n\n";
195 OS << "} // end anonymous namespace\n\n";
197 // Now that all of the structs have been emitted, emit the instances.
198 if (!RegisterClasses.empty()) {
199 OS << "namespace " << RegisterClasses[0].Namespace
200 << " { // Register class instances\n";
201 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
202 OS << " " << RegisterClasses[i].getName() << "Class\t"
203 << RegisterClasses[i].getName() << "RegClass;\n";
205 std::map<unsigned, std::set<unsigned> > SuperClassMap;
206 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
209 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
211 if (NumSubRegIndices) {
212 // Emit the sub-register classes for each RegisterClass
213 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
214 const CodeGenRegisterClass &RC = RegisterClasses[rc];
215 std::vector<Record*> SRC(NumSubRegIndices);
216 for (DenseMap<Record*,Record*>::const_iterator
217 i = RC.SubRegClasses.begin(),
218 e = RC.SubRegClasses.end(); i != e; ++i) {
220 unsigned idx = RegBank.getSubRegIndexNo(i->first);
221 SRC.at(idx-1) = i->second;
223 // Find the register class number of i->second for SuperRegClassMap.
224 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
225 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
226 if (RC2.TheDef == i->second) {
227 SuperRegClassMap[rc2].insert(rc);
233 // Give the register class a legal C name if it's anonymous.
234 std::string Name = RC.TheDef->getName();
237 << " Sub-register Classes...\n"
238 << " static const TargetRegisterClass* const "
239 << Name << "SubRegClasses[] = {\n ";
241 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
245 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
252 // Emit the super-register classes for each RegisterClass
253 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
254 const CodeGenRegisterClass &RC = RegisterClasses[rc];
256 // Give the register class a legal C name if it's anonymous.
257 std::string Name = RC.TheDef->getName();
260 << " Super-register Classes...\n"
261 << " static const TargetRegisterClass* const "
262 << Name << "SuperRegClasses[] = {\n ";
265 std::map<unsigned, std::set<unsigned> >::iterator I =
266 SuperRegClassMap.find(rc);
267 if (I != SuperRegClassMap.end()) {
268 for (std::set<unsigned>::iterator II = I->second.begin(),
269 EE = I->second.end(); II != EE; ++II) {
270 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
273 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
278 OS << (!Empty ? ", " : "") << "NULL";
282 // No subregindices in this target
283 OS << " static const TargetRegisterClass* const "
284 << "NullRegClasses[] = { NULL };\n\n";
287 // Emit the sub-classes array for each RegisterClass
288 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
289 const CodeGenRegisterClass &RC = RegisterClasses[rc];
291 // Give the register class a legal C name if it's anonymous.
292 std::string Name = RC.TheDef->getName();
295 << " Register Class sub-classes...\n"
296 << " static const TargetRegisterClass* const "
297 << Name << "Subclasses[] = {\n ";
300 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
301 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
303 // Sub-classes are used to determine if a virtual register can be used
304 // as an instruction operand, or if it must be copied first.
305 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
307 if (!Empty) OS << ", ";
308 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
311 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
312 SuperClassMap.find(rc2);
313 if (SCMI == SuperClassMap.end()) {
314 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
315 SCMI = SuperClassMap.find(rc2);
317 SCMI->second.insert(rc);
320 OS << (!Empty ? ", " : "") << "NULL";
324 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
325 const CodeGenRegisterClass &RC = RegisterClasses[rc];
327 // Give the register class a legal C name if it's anonymous.
328 std::string Name = RC.TheDef->getName();
331 << " Register Class super-classes...\n"
332 << " static const TargetRegisterClass* const "
333 << Name << "Superclasses[] = {\n ";
336 std::map<unsigned, std::set<unsigned> >::iterator I =
337 SuperClassMap.find(rc);
338 if (I != SuperClassMap.end()) {
339 for (std::set<unsigned>::iterator II = I->second.begin(),
340 EE = I->second.end(); II != EE; ++II) {
341 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
342 if (!Empty) OS << ", ";
343 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
348 OS << (!Empty ? ", " : "") << "NULL";
353 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
354 const CodeGenRegisterClass &RC = RegisterClasses[i];
355 OS << RC.MethodBodies << "\n";
356 OS << RC.getName() << "Class::" << RC.getName()
357 << "Class() : TargetRegisterClass("
358 << RC.getName() + "RegClassID" << ", "
359 << '\"' << RC.getName() << "\", "
360 << RC.getName() + "VTs" << ", "
361 << RC.getName() + "Subclasses" << ", "
362 << RC.getName() + "Superclasses" << ", "
363 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
365 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
367 << RC.SpillSize/8 << ", "
368 << RC.SpillAlignment/8 << ", "
369 << RC.CopyCost << ", "
370 << RC.Allocatable << ", "
371 << RC.getName() << ", " << RC.getName() << " + "
372 << RC.getOrder().size()
379 OS << "\nnamespace {\n";
380 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
381 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
382 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
386 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
387 DwarfRegNumsMapTy DwarfRegNums;
388 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
390 // Emit an overlap list for all registers.
391 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
392 const CodeGenRegister *Reg = &Regs[i];
393 const CodeGenRegister::Set &O = Overlaps[Reg];
394 // Move Reg to the front so TRI::getAliasSet can share the list.
395 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
396 << getQualifiedName(Reg->TheDef) << ", ";
397 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
400 OS << getQualifiedName((*I)->TheDef) << ", ";
404 // Emit the empty sub-registers list
405 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
406 // Loop over all of the registers which have sub-registers, emitting the
407 // sub-registers list to memory.
408 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
409 const CodeGenRegister &Reg = Regs[i];
410 if (Reg.getSubRegs().empty())
412 // getSubRegs() orders by SubRegIndex. We want a topological order.
413 SetVector<CodeGenRegister*> SR;
414 Reg.addSubRegsPreOrder(SR);
415 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
416 for (unsigned j = 0, je = SR.size(); j != je; ++j)
417 OS << getQualifiedName(SR[j]->TheDef) << ", ";
421 // Emit the empty super-registers list
422 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
423 // Loop over all of the registers which have super-registers, emitting the
424 // super-registers list to memory.
425 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
426 const CodeGenRegister &Reg = Regs[i];
427 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
430 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
431 for (unsigned j = 0, je = SR.size(); j != je; ++j)
432 OS << getQualifiedName(SR[j]->TheDef) << ", ";
436 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
437 OS << " { \"NOREG\",\t0,\t0,\t0,\t0,\t0 },\n";
439 // Now that register alias and sub-registers sets have been emitted, emit the
440 // register descriptors now.
441 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
442 const CodeGenRegister &Reg = Regs[i];
444 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
445 if (!Reg.getSubRegs().empty())
446 OS << Reg.getName() << "_SubRegsSet,\t";
448 OS << "Empty_SubRegsSet,\t";
449 if (!Reg.getSuperRegs().empty())
450 OS << Reg.getName() << "_SuperRegsSet,\t";
452 OS << "Empty_SuperRegsSet,\t";
453 OS << Reg.CostPerUse << ",\t"
454 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
456 OS << " };\n"; // End of register descriptors...
458 // Calculate the mapping of subregister+index pairs to physical registers.
459 // This will also create further anonymous indexes.
460 unsigned NamedIndices = RegBank.getNumNamedIndices();
462 // Emit SubRegIndex names, skipping 0
463 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
464 OS << "\n const char *const SubRegIndexTable[] = { \"";
465 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
466 OS << SubRegIndices[i]->getName();
472 // Emit names of the anonymus subreg indexes.
473 if (SubRegIndices.size() > NamedIndices) {
475 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
476 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
482 OS << "}\n\n"; // End of anonymous namespace...
484 std::string ClassName = Target.getName() + "GenRegisterInfo";
486 // Emit the subregister + index mapping function based on the information
488 OS << "unsigned " << ClassName
489 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
490 << " switch (RegNo) {\n"
491 << " default:\n return 0;\n";
492 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
493 const CodeGenRegister::SubRegMap &SRM = Regs[i].getSubRegs();
496 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
497 OS << " switch (Index) {\n";
498 OS << " default: return 0;\n";
499 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
500 ie = SRM.end(); ii != ie; ++ii)
501 OS << " case " << getQualifiedName(ii->first)
502 << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
503 OS << " };\n" << " break;\n";
506 OS << " return 0;\n";
509 OS << "unsigned " << ClassName
510 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
511 << " switch (RegNo) {\n"
512 << " default:\n return 0;\n";
513 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
514 const CodeGenRegister::SubRegMap &SRM = Regs[i].getSubRegs();
517 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
518 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
519 ie = SRM.end(); ii != ie; ++ii)
520 OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
521 << ") return " << getQualifiedName(ii->first) << ";\n";
522 OS << " return 0;\n";
525 OS << " return 0;\n";
528 // Emit composeSubRegIndices
529 OS << "unsigned " << ClassName
530 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
531 << " switch (IdxA) {\n"
532 << " default:\n return IdxB;\n";
533 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
535 for (unsigned j = 0; j != e; ++j) {
536 if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
539 OS << " case " << getQualifiedName(SubRegIndices[i])
540 << ": switch(IdxB) {\n default: return IdxB;\n";
543 OS << " case " << getQualifiedName(SubRegIndices[j])
544 << ": return " << getQualifiedName(Comp) << ";\n";
552 // Emit the constructor of the class...
553 OS << ClassName << "::" << ClassName
554 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
555 << " : TargetRegisterInfo(RegisterDescriptors, " << Regs.size()+1
556 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
557 << " SubRegIndexTable,\n"
558 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {\n"
561 // Collect all information about dwarf register numbers
563 // First, just pull all provided information to the map
564 unsigned maxLength = 0;
565 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
566 Record *Reg = Regs[i].TheDef;
567 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
568 maxLength = std::max((size_t)maxLength, RegNums.size());
569 if (DwarfRegNums.count(Reg))
570 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
571 << "specified multiple times\n";
572 DwarfRegNums[Reg] = RegNums;
575 // Now we know maximal length of number list. Append -1's, where needed
576 for (DwarfRegNumsMapTy::iterator
577 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
578 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
579 I->second.push_back(-1);
581 // Emit reverse information about the dwarf register numbers.
582 OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, "
583 << "unsigned Flavour) const {\n"
584 << " switch (Flavour) {\n"
586 << " assert(0 && \"Unknown DWARF flavour\");\n"
589 for (unsigned i = 0, e = maxLength; i != e; ++i) {
590 OS << " case " << i << ":\n"
591 << " switch (DwarfRegNum) {\n"
593 << " assert(0 && \"Invalid DwarfRegNum\");\n"
596 for (DwarfRegNumsMapTy::iterator
597 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
598 int DwarfRegNo = I->second[i];
600 OS << " case " << DwarfRegNo << ":\n"
601 << " return " << getQualifiedName(I->first) << ";\n";
608 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
609 Record *Reg = Regs[i].TheDef;
610 const RecordVal *V = Reg->getValue("DwarfAlias");
611 if (!V || !V->getValue())
614 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
615 Record *Alias = DI->getDef();
616 DwarfRegNums[Reg] = DwarfRegNums[Alias];
619 // Emit information about the dwarf register numbers.
620 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
621 << "unsigned Flavour) const {\n"
622 << " switch (Flavour) {\n"
624 << " assert(0 && \"Unknown DWARF flavour\");\n"
627 for (unsigned i = 0, e = maxLength; i != e; ++i) {
628 OS << " case " << i << ":\n"
629 << " switch (RegNum) {\n"
631 << " assert(0 && \"Invalid RegNum\");\n"
634 // Sort by name to get a stable order.
637 for (DwarfRegNumsMapTy::iterator
638 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
639 int RegNo = I->second[i];
640 OS << " case " << getQualifiedName(I->first) << ":\n"
641 << " return " << RegNo << ";\n";
648 OS << "} // End llvm namespace \n";