1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Format.h"
27 // runEnums - Print out enum values for all of the registers.
29 RegisterInfoEmitter::runEnums(raw_ostream &OS,
30 CodeGenTarget &Target, CodeGenRegBank &Bank) {
31 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
33 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
35 EmitSourceFileHeader("Target Register Enum Values", OS);
37 OS << "\n#ifdef GET_REGINFO_ENUM\n";
38 OS << "#undef GET_REGINFO_ENUM\n";
40 OS << "namespace llvm {\n\n";
42 if (!Namespace.empty())
43 OS << "namespace " << Namespace << " {\n";
44 OS << "enum {\n NoRegister,\n";
46 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
47 OS << " " << Registers[i]->getName() << " = " <<
48 Registers[i]->EnumValue << ",\n";
49 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
50 "Register enum value mismatch!");
51 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
53 if (!Namespace.empty())
56 const std::vector<CodeGenRegisterClass> &RegisterClasses =
57 Target.getRegisterClasses();
58 if (!RegisterClasses.empty()) {
59 OS << "\n// Register classes\n";
60 if (!Namespace.empty())
61 OS << "namespace " << Namespace << " {\n";
63 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
65 OS << " " << RegisterClasses[i].getName() << "RegClassID";
69 if (!Namespace.empty())
73 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
74 // If the only definition is the default NoRegAltName, we don't need to
76 if (RegAltNameIndices.size() > 1) {
77 OS << "\n// Register alternate name indices\n";
78 if (!Namespace.empty())
79 OS << "namespace " << Namespace << " {\n";
81 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
82 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
83 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
85 if (!Namespace.empty())
90 OS << "} // End llvm namespace \n";
91 OS << "#endif // GET_REGINFO_ENUM\n\n";
95 // runMCDesc - Print out MC register descriptions.
98 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
99 CodeGenRegBank &RegBank) {
100 EmitSourceFileHeader("MC Register Information", OS);
102 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
103 OS << "#undef GET_REGINFO_MC_DESC\n";
105 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
106 RegBank.computeOverlaps(Overlaps);
108 OS << "namespace llvm {\n\n";
110 const std::string &TargetName = Target.getName();
111 std::string ClassName = TargetName + "GenMCRegisterInfo";
112 OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
113 << " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
116 OS << "\nnamespace {\n";
118 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
120 // Emit an overlap list for all registers.
121 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
122 const CodeGenRegister *Reg = Regs[i];
123 const CodeGenRegister::Set &O = Overlaps[Reg];
124 // Move Reg to the front so TRI::getAliasSet can share the list.
125 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
126 << getQualifiedName(Reg->TheDef) << ", ";
127 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
130 OS << getQualifiedName((*I)->TheDef) << ", ";
134 // Emit the empty sub-registers list
135 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
136 // Loop over all of the registers which have sub-registers, emitting the
137 // sub-registers list to memory.
138 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
139 const CodeGenRegister &Reg = *Regs[i];
140 if (Reg.getSubRegs().empty())
142 // getSubRegs() orders by SubRegIndex. We want a topological order.
143 SetVector<CodeGenRegister*> SR;
144 Reg.addSubRegsPreOrder(SR);
145 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
146 for (unsigned j = 0, je = SR.size(); j != je; ++j)
147 OS << getQualifiedName(SR[j]->TheDef) << ", ";
151 // Emit the empty super-registers list
152 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
153 // Loop over all of the registers which have super-registers, emitting the
154 // super-registers list to memory.
155 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
156 const CodeGenRegister &Reg = *Regs[i];
157 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
160 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
161 for (unsigned j = 0, je = SR.size(); j != je; ++j)
162 OS << getQualifiedName(SR[j]->TheDef) << ", ";
165 OS << "}\n"; // End of anonymous namespace...
167 OS << "\nMCRegisterDesc " << TargetName
168 << "RegDesc[] = { // Descriptors\n";
169 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
171 // Now that register alias and sub-registers sets have been emitted, emit the
172 // register descriptors now.
173 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
174 const CodeGenRegister &Reg = *Regs[i];
176 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
177 if (!Reg.getSubRegs().empty())
178 OS << Reg.getName() << "_SubRegsSet,\t";
180 OS << "Empty_SubRegsSet,\t";
181 if (!Reg.getSuperRegs().empty())
182 OS << Reg.getName() << "_SuperRegsSet";
184 OS << "Empty_SuperRegsSet";
187 OS << "};\n\n"; // End of register descriptors...
189 // MCRegisterInfo initialization routine.
190 OS << "static inline void Init" << TargetName
191 << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
192 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
193 << Regs.size()+1 << ");\n}\n\n";
195 OS << "} // End llvm namespace \n";
196 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
200 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
201 CodeGenRegBank &RegBank) {
202 EmitSourceFileHeader("Register Information Header Fragment", OS);
204 OS << "\n#ifdef GET_REGINFO_HEADER\n";
205 OS << "#undef GET_REGINFO_HEADER\n";
207 const std::string &TargetName = Target.getName();
208 std::string ClassName = TargetName + "GenRegisterInfo";
210 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
211 OS << "#include <string>\n\n";
213 OS << "namespace llvm {\n\n";
215 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
216 << " explicit " << ClassName << "();\n"
217 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
218 << "unsigned Flavour) const;\n"
219 << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
220 << "unsigned Flavour) const;\n"
221 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
222 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
223 << " { return false; }\n"
224 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
225 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
226 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
229 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
230 if (!SubRegIndices.empty()) {
231 OS << "\n// Subregister indices\n";
232 std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace");
233 if (!Namespace.empty())
234 OS << "namespace " << Namespace << " {\n";
235 OS << "enum {\n NoSubRegister,\n";
236 for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i)
237 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
238 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
240 if (!Namespace.empty())
244 const std::vector<CodeGenRegisterClass> &RegisterClasses =
245 Target.getRegisterClasses();
247 if (!RegisterClasses.empty()) {
248 OS << "namespace " << RegisterClasses[0].Namespace
249 << " { // Register classes\n";
251 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
252 const CodeGenRegisterClass &RC = RegisterClasses[i];
253 const std::string &Name = RC.getName();
255 // Output the register class definition.
256 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
257 << " " << Name << "Class();\n";
258 if (!RC.AltOrderSelect.empty())
259 OS << " ArrayRef<unsigned> "
260 "getRawAllocationOrder(const MachineFunction&) const;\n";
263 // Output the extern for the instance.
264 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
265 // Output the extern for the pointer to the instance (should remove).
266 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
267 << Name << "RegClass;\n";
269 OS << "} // end of namespace " << TargetName << "\n\n";
271 OS << "} // End llvm namespace \n";
272 OS << "#endif // GET_REGINFO_HEADER\n\n";
276 // runTargetDesc - Output the target register and register file descriptions.
279 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
280 CodeGenRegBank &RegBank){
281 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
283 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
284 OS << "#undef GET_REGINFO_TARGET_DESC\n";
286 OS << "namespace llvm {\n\n";
288 // Start out by emitting each of the register classes.
289 const std::vector<CodeGenRegisterClass> &RegisterClasses =
290 Target.getRegisterClasses();
292 // Collect all registers belonging to any allocatable class.
293 std::set<Record*> AllocatableRegs;
295 // Loop over all of the register classes... emitting each one.
296 OS << "namespace { // Register classes...\n";
298 // Emit the register enum value arrays for each RegisterClass
299 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
300 const CodeGenRegisterClass &RC = RegisterClasses[rc];
301 ArrayRef<Record*> Order = RC.getOrder();
303 // Collect allocatable registers.
305 AllocatableRegs.insert(Order.begin(), Order.end());
307 // Give the register class a legal C name if it's anonymous.
308 std::string Name = RC.getName();
310 // Emit the register list now.
311 OS << " // " << Name << " Register Class...\n"
312 << " static const unsigned " << Name
314 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
315 Record *Reg = Order[i];
316 OS << getQualifiedName(Reg) << ", ";
321 // Emit the ValueType arrays for each RegisterClass
322 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
323 const CodeGenRegisterClass &RC = RegisterClasses[rc];
325 // Give the register class a legal C name if it's anonymous.
326 std::string Name = RC.getName() + "VTs";
328 // Emit the register list now.
330 << " Register Class Value Types...\n"
331 << " static const EVT " << Name
333 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
334 OS << getEnumName(RC.VTs[i]) << ", ";
335 OS << "MVT::Other\n };\n\n";
337 OS << "} // end anonymous namespace\n\n";
339 // Now that all of the structs have been emitted, emit the instances.
340 if (!RegisterClasses.empty()) {
341 OS << "namespace " << RegisterClasses[0].Namespace
342 << " { // Register class instances\n";
343 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
344 OS << " " << RegisterClasses[i].getName() << "Class\t"
345 << RegisterClasses[i].getName() << "RegClass;\n";
347 std::map<unsigned, std::set<unsigned> > SuperClassMap;
348 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
351 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
353 if (NumSubRegIndices) {
354 // Emit the sub-register classes for each RegisterClass
355 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
356 const CodeGenRegisterClass &RC = RegisterClasses[rc];
357 std::vector<Record*> SRC(NumSubRegIndices);
358 for (DenseMap<Record*,Record*>::const_iterator
359 i = RC.SubRegClasses.begin(),
360 e = RC.SubRegClasses.end(); i != e; ++i) {
362 unsigned idx = RegBank.getSubRegIndexNo(i->first);
363 SRC.at(idx-1) = i->second;
365 // Find the register class number of i->second for SuperRegClassMap.
366 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
367 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
368 if (RC2.TheDef == i->second) {
369 SuperRegClassMap[rc2].insert(rc);
375 // Give the register class a legal C name if it's anonymous.
376 std::string Name = RC.TheDef->getName();
379 << " Sub-register Classes...\n"
380 << " static const TargetRegisterClass* const "
381 << Name << "SubRegClasses[] = {\n ";
383 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
387 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
394 // Emit the super-register classes for each RegisterClass
395 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
396 const CodeGenRegisterClass &RC = RegisterClasses[rc];
398 // Give the register class a legal C name if it's anonymous.
399 std::string Name = RC.TheDef->getName();
402 << " Super-register Classes...\n"
403 << " static const TargetRegisterClass* const "
404 << Name << "SuperRegClasses[] = {\n ";
407 std::map<unsigned, std::set<unsigned> >::iterator I =
408 SuperRegClassMap.find(rc);
409 if (I != SuperRegClassMap.end()) {
410 for (std::set<unsigned>::iterator II = I->second.begin(),
411 EE = I->second.end(); II != EE; ++II) {
412 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
415 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
420 OS << (!Empty ? ", " : "") << "NULL";
424 // No subregindices in this target
425 OS << " static const TargetRegisterClass* const "
426 << "NullRegClasses[] = { NULL };\n\n";
429 // Emit the sub-classes array for each RegisterClass
430 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
431 const CodeGenRegisterClass &RC = RegisterClasses[rc];
433 // Give the register class a legal C name if it's anonymous.
434 std::string Name = RC.TheDef->getName();
437 << " Register Class sub-classes...\n"
438 << " static const TargetRegisterClass* const "
439 << Name << "Subclasses[] = {\n ";
442 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
443 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
445 // Sub-classes are used to determine if a virtual register can be used
446 // as an instruction operand, or if it must be copied first.
447 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
449 if (!Empty) OS << ", ";
450 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
453 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
454 SuperClassMap.find(rc2);
455 if (SCMI == SuperClassMap.end()) {
456 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
457 SCMI = SuperClassMap.find(rc2);
459 SCMI->second.insert(rc);
462 OS << (!Empty ? ", " : "") << "NULL";
466 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
467 const CodeGenRegisterClass &RC = RegisterClasses[rc];
469 // Give the register class a legal C name if it's anonymous.
470 std::string Name = RC.TheDef->getName();
473 << " Register Class super-classes...\n"
474 << " static const TargetRegisterClass* const "
475 << Name << "Superclasses[] = {\n ";
478 std::map<unsigned, std::set<unsigned> >::iterator I =
479 SuperClassMap.find(rc);
480 if (I != SuperClassMap.end()) {
481 for (std::set<unsigned>::iterator II = I->second.begin(),
482 EE = I->second.end(); II != EE; ++II) {
483 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
484 if (!Empty) OS << ", ";
485 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
490 OS << (!Empty ? ", " : "") << "NULL";
495 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
496 const CodeGenRegisterClass &RC = RegisterClasses[i];
497 OS << RC.getName() << "Class::" << RC.getName()
498 << "Class() : TargetRegisterClass("
499 << RC.getName() + "RegClassID" << ", "
500 << '\"' << RC.getName() << "\", "
501 << RC.getName() + "VTs" << ", "
502 << RC.getName() + "Subclasses" << ", "
503 << RC.getName() + "Superclasses" << ", "
504 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
506 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
508 << RC.SpillSize/8 << ", "
509 << RC.SpillAlignment/8 << ", "
510 << RC.CopyCost << ", "
511 << RC.Allocatable << ", "
512 << RC.getName() << ", " << RC.getName() << " + "
513 << RC.getOrder().size()
515 if (!RC.AltOrderSelect.empty()) {
516 OS << "\nstatic inline unsigned " << RC.getName()
517 << "AltOrderSelect(const MachineFunction &MF) {"
518 << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
519 << RC.getName() << "Class::"
520 << "getRawAllocationOrder(const MachineFunction &MF) const {\n";
521 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
522 ArrayRef<Record*> Elems = RC.getOrder(oi);
523 OS << " static const unsigned AltOrder" << oi << "[] = {";
524 for (unsigned elem = 0; elem != Elems.size(); ++elem)
525 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
528 OS << " static const ArrayRef<unsigned> Order[] = {\n"
529 << " makeArrayRef(" << RC.getName();
530 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
531 OS << "),\n makeArrayRef(AltOrder" << oi;
532 OS << ")\n };\n const unsigned Select = " << RC.getName()
533 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
534 << ");\n return Order[Select];\n}\n";
541 OS << "\nnamespace {\n";
542 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
543 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
544 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
547 OS << "}\n"; // End of anonymous namespace...
549 // Emit extra information about registers.
550 const std::string &TargetName = Target.getName();
551 OS << "\n static const TargetRegisterInfoDesc "
552 << TargetName << "RegInfoDesc[] = "
553 << "{ // Extra Descriptors\n";
554 OS << " { 0, 0 },\n";
556 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
557 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
558 const CodeGenRegister &Reg = *Regs[i];
560 OS << Reg.CostPerUse << ", "
561 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
563 OS << " };\n"; // End of register descriptors...
566 // Calculate the mapping of subregister+index pairs to physical registers.
567 // This will also create further anonymous indexes.
568 unsigned NamedIndices = RegBank.getNumNamedIndices();
570 // Emit SubRegIndex names, skipping 0
571 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
572 OS << "\n static const char *const " << TargetName
573 << "SubRegIndexTable[] = { \"";
574 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
575 OS << SubRegIndices[i]->getName();
581 // Emit names of the anonymus subreg indexes.
582 if (SubRegIndices.size() > NamedIndices) {
584 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
585 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
593 std::string ClassName = Target.getName() + "GenRegisterInfo";
595 // Emit the subregister + index mapping function based on the information
597 OS << "unsigned " << ClassName
598 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
599 << " switch (RegNo) {\n"
600 << " default:\n return 0;\n";
601 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
602 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
605 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
606 OS << " switch (Index) {\n";
607 OS << " default: return 0;\n";
608 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
609 ie = SRM.end(); ii != ie; ++ii)
610 OS << " case " << getQualifiedName(ii->first)
611 << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
612 OS << " };\n" << " break;\n";
615 OS << " return 0;\n";
618 OS << "unsigned " << ClassName
619 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
620 << " switch (RegNo) {\n"
621 << " default:\n return 0;\n";
622 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
623 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
626 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
627 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
628 ie = SRM.end(); ii != ie; ++ii)
629 OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
630 << ") return " << getQualifiedName(ii->first) << ";\n";
631 OS << " return 0;\n";
634 OS << " return 0;\n";
637 // Emit composeSubRegIndices
638 OS << "unsigned " << ClassName
639 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
640 << " switch (IdxA) {\n"
641 << " default:\n return IdxB;\n";
642 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
644 for (unsigned j = 0; j != e; ++j) {
645 if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
648 OS << " case " << getQualifiedName(SubRegIndices[i])
649 << ": switch(IdxB) {\n default: return IdxB;\n";
652 OS << " case " << getQualifiedName(SubRegIndices[j])
653 << ": return " << getQualifiedName(Comp) << ";\n";
661 // Emit the constructor of the class...
662 OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n";
664 OS << ClassName << "::" << ClassName
666 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
667 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
668 << " " << TargetName << "SubRegIndexTable) {\n"
669 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
670 << Regs.size()+1 << ");\n"
673 // Collect all information about dwarf register numbers
674 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
675 DwarfRegNumsMapTy DwarfRegNums;
677 // First, just pull all provided information to the map
678 unsigned maxLength = 0;
679 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
680 Record *Reg = Regs[i]->TheDef;
681 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
682 maxLength = std::max((size_t)maxLength, RegNums.size());
683 if (DwarfRegNums.count(Reg))
684 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
685 << "specified multiple times\n";
686 DwarfRegNums[Reg] = RegNums;
689 // Now we know maximal length of number list. Append -1's, where needed
690 for (DwarfRegNumsMapTy::iterator
691 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
692 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
693 I->second.push_back(-1);
695 // Emit reverse information about the dwarf register numbers.
696 OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, "
697 << "unsigned Flavour) const {\n"
698 << " switch (Flavour) {\n"
700 << " assert(0 && \"Unknown DWARF flavour\");\n"
703 for (unsigned i = 0, e = maxLength; i != e; ++i) {
704 OS << " case " << i << ":\n"
705 << " switch (DwarfRegNum) {\n"
707 << " assert(0 && \"Invalid DwarfRegNum\");\n"
710 for (DwarfRegNumsMapTy::iterator
711 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
712 int DwarfRegNo = I->second[i];
714 OS << " case " << DwarfRegNo << ":\n"
715 << " return " << getQualifiedName(I->first) << ";\n";
722 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
723 Record *Reg = Regs[i]->TheDef;
724 const RecordVal *V = Reg->getValue("DwarfAlias");
725 if (!V || !V->getValue())
728 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
729 Record *Alias = DI->getDef();
730 DwarfRegNums[Reg] = DwarfRegNums[Alias];
733 // Emit information about the dwarf register numbers.
734 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
735 << "unsigned Flavour) const {\n"
736 << " switch (Flavour) {\n"
738 << " assert(0 && \"Unknown DWARF flavour\");\n"
741 for (unsigned i = 0, e = maxLength; i != e; ++i) {
742 OS << " case " << i << ":\n"
743 << " switch (RegNum) {\n"
745 << " assert(0 && \"Invalid RegNum\");\n"
748 // Sort by name to get a stable order.
751 for (DwarfRegNumsMapTy::iterator
752 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
753 int RegNo = I->second[i];
754 OS << " case " << getQualifiedName(I->first) << ":\n"
755 << " return " << RegNo << ";\n";
762 OS << "} // End llvm namespace \n";
763 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
766 void RegisterInfoEmitter::run(raw_ostream &OS) {
767 CodeGenTarget Target(Records);
768 CodeGenRegBank &RegBank = Target.getRegBank();
769 RegBank.computeDerivedInfo();
771 runEnums(OS, Target, RegBank);
772 runMCDesc(OS, Target, RegBank);
773 runTargetHeader(OS, Target, RegBank);
774 runTargetDesc(OS, Target, RegBank);