1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Streams.h"
27 // runEnums - Print out enum values for all of the registers.
28 void RegisterInfoEmitter::runEnums(std::ostream &OS) {
30 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
32 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
34 EmitSourceFileHeader("Target Register Enum Values", OS);
35 OS << "namespace llvm {\n\n";
37 if (!Namespace.empty())
38 OS << "namespace " << Namespace << " {\n";
39 OS << " enum {\n NoRegister,\n";
41 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
42 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
43 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
45 if (!Namespace.empty())
47 OS << "} // End llvm namespace \n";
50 void RegisterInfoEmitter::runHeader(std::ostream &OS) {
51 EmitSourceFileHeader("Register Information Header Fragment", OS);
53 const std::string &TargetName = Target.getName();
54 std::string ClassName = TargetName + "GenRegisterInfo";
56 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
57 OS << "#include <string>\n\n";
59 OS << "namespace llvm {\n\n";
61 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
62 << " explicit " << ClassName
63 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
64 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
65 << "unsigned Flavour) const;\n"
66 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
67 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
68 << " { return false; }\n"
69 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
72 const std::vector<CodeGenRegisterClass> &RegisterClasses =
73 Target.getRegisterClasses();
75 if (!RegisterClasses.empty()) {
76 OS << "namespace " << RegisterClasses[0].Namespace
77 << " { // Register classes\n";
80 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
82 OS << " " << RegisterClasses[i].getName() << "RegClassID";
87 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
88 const std::string &Name = RegisterClasses[i].getName();
90 // Output the register class definition.
91 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
92 << " " << Name << "Class();\n"
93 << RegisterClasses[i].MethodProtos << " };\n";
95 // Output the extern for the instance.
96 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
97 // Output the extern for the pointer to the instance (should remove).
98 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
99 << Name << "RegClass;\n";
101 OS << "} // end of namespace " << TargetName << "\n\n";
103 OS << "} // End llvm namespace \n";
106 bool isSubRegisterClass(const CodeGenRegisterClass &RC,
107 std::set<Record*> &RegSet) {
108 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
109 Record *Reg = RC.Elements[i];
110 if (!RegSet.count(Reg))
116 static void addSuperReg(Record *R, Record *S,
117 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
118 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
119 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
121 cerr << "Error: recursive sub-register relationship between"
122 << " register " << getQualifiedName(R)
123 << " and its sub-registers?\n";
126 if (!SuperRegs[R].insert(S).second)
128 SubRegs[S].insert(R);
129 Aliases[R].insert(S);
130 Aliases[S].insert(R);
131 if (SuperRegs.count(S))
132 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
133 E = SuperRegs[S].end(); I != E; ++I)
134 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
137 static void addSubSuperReg(Record *R, Record *S,
138 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
139 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
140 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
142 cerr << "Error: recursive sub-register relationship between"
143 << " register " << getQualifiedName(R)
144 << " and its sub-registers?\n";
148 if (!SubRegs[R].insert(S).second)
150 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
151 Aliases[R].insert(S);
152 Aliases[S].insert(R);
153 if (SubRegs.count(S))
154 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
155 E = SubRegs[S].end(); I != E; ++I)
156 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
159 class RegisterSorter {
161 std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
164 RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
165 : RegisterSubRegs(RS) {};
167 bool operator()(Record *RegA, Record *RegB) {
168 // B is sub-register of A.
169 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
173 // RegisterInfoEmitter::run - Main register file description emitter.
175 void RegisterInfoEmitter::run(std::ostream &OS) {
176 CodeGenTarget Target;
177 EmitSourceFileHeader("Register Information Source Fragment", OS);
179 OS << "namespace llvm {\n\n";
181 // Start out by emitting each of the register classes... to do this, we build
182 // a set of registers which belong to a register class, this is to ensure that
183 // each register is only in a single register class.
185 const std::vector<CodeGenRegisterClass> &RegisterClasses =
186 Target.getRegisterClasses();
188 // Loop over all of the register classes... emitting each one.
189 OS << "namespace { // Register classes...\n";
191 // RegClassesBelongedTo - Keep track of which register classes each reg
193 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
195 // Emit the register enum value arrays for each RegisterClass
196 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
197 const CodeGenRegisterClass &RC = RegisterClasses[rc];
199 // Give the register class a legal C name if it's anonymous.
200 std::string Name = RC.TheDef->getName();
202 // Emit the register list now.
203 OS << " // " << Name << " Register Class...\n"
204 << " static const unsigned " << Name
206 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
207 Record *Reg = RC.Elements[i];
208 OS << getQualifiedName(Reg) << ", ";
210 // Keep track of which regclasses this register is in.
211 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
216 // Emit the ValueType arrays for each RegisterClass
217 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
218 const CodeGenRegisterClass &RC = RegisterClasses[rc];
220 // Give the register class a legal C name if it's anonymous.
221 std::string Name = RC.TheDef->getName() + "VTs";
223 // Emit the register list now.
225 << " Register Class Value Types...\n"
226 << " static const MVT " << Name
228 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
229 OS << getEnumName(RC.VTs[i]) << ", ";
230 OS << "MVT::Other\n };\n\n";
232 OS << "} // end anonymous namespace\n\n";
234 // Now that all of the structs have been emitted, emit the instances.
235 if (!RegisterClasses.empty()) {
236 OS << "namespace " << RegisterClasses[0].Namespace
237 << " { // Register class instances\n";
238 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
239 OS << " " << RegisterClasses[i].getName() << "Class\t"
240 << RegisterClasses[i].getName() << "RegClass;\n";
242 std::map<unsigned, std::set<unsigned> > SuperClassMap;
245 // Emit the sub-classes array for each RegisterClass
246 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
247 const CodeGenRegisterClass &RC = RegisterClasses[rc];
249 // Give the register class a legal C name if it's anonymous.
250 std::string Name = RC.TheDef->getName();
252 std::set<Record*> RegSet;
253 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
254 Record *Reg = RC.Elements[i];
259 << " Register Class sub-classes...\n"
260 << " static const TargetRegisterClass* const "
261 << Name << "Subclasses [] = {\n ";
264 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
265 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
266 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
267 RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
270 if (!Empty) OS << ", ";
271 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
274 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
275 SuperClassMap.find(rc2);
276 if (SCMI == SuperClassMap.end()) {
277 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
278 SCMI = SuperClassMap.find(rc2);
280 SCMI->second.insert(rc);
283 OS << (!Empty ? ", " : "") << "NULL";
287 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
288 const CodeGenRegisterClass &RC = RegisterClasses[rc];
290 // Give the register class a legal C name if it's anonymous.
291 std::string Name = RC.TheDef->getName();
294 << " Register Class super-classes...\n"
295 << " static const TargetRegisterClass* const "
296 << Name << "Superclasses [] = {\n ";
299 std::map<unsigned, std::set<unsigned> >::iterator I =
300 SuperClassMap.find(rc);
301 if (I != SuperClassMap.end()) {
302 for (std::set<unsigned>::iterator II = I->second.begin(),
303 EE = I->second.end(); II != EE; ++II) {
304 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
305 if (!Empty) OS << ", ";
306 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
311 OS << (!Empty ? ", " : "") << "NULL";
316 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
317 const CodeGenRegisterClass &RC = RegisterClasses[i];
318 OS << RC.MethodBodies << "\n";
319 OS << RC.getName() << "Class::" << RC.getName()
320 << "Class() : TargetRegisterClass("
321 << RC.getName() + "RegClassID" << ", "
322 << '\"' << RC.getName() << "\", "
323 << RC.getName() + "VTs" << ", "
324 << RC.getName() + "Subclasses" << ", "
325 << RC.getName() + "Superclasses" << ", "
326 << RC.SpillSize/8 << ", "
327 << RC.SpillAlignment/8 << ", "
328 << RC.CopyCost << ", "
329 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
336 OS << "\nnamespace {\n";
337 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
338 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
339 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
343 // Emit register sub-registers / super-registers, aliases...
344 std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
345 std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
346 std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
347 std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
348 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
349 DwarfRegNumsMapTy DwarfRegNums;
351 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
353 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
354 Record *R = Regs[i].TheDef;
355 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
356 // Add information that R aliases all of the elements in the list... and
357 // that everything in the list aliases R.
358 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
360 if (RegisterAliases[R].count(Reg))
361 cerr << "Warning: register alias between " << getQualifiedName(R)
362 << " and " << getQualifiedName(Reg)
363 << " specified multiple times!\n";
364 RegisterAliases[R].insert(Reg);
366 if (RegisterAliases[Reg].count(R))
367 cerr << "Warning: register alias between " << getQualifiedName(R)
368 << " and " << getQualifiedName(Reg)
369 << " specified multiple times!\n";
370 RegisterAliases[Reg].insert(R);
374 // Process sub-register sets.
375 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
376 Record *R = Regs[i].TheDef;
377 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
378 // Process sub-register set and add aliases information.
379 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
380 Record *SubReg = LI[j];
381 if (RegisterSubRegs[R].count(SubReg))
382 cerr << "Warning: register " << getQualifiedName(SubReg)
383 << " specified as a sub-register of " << getQualifiedName(R)
384 << " multiple times!\n";
385 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
390 // Print the SubregHashTable, a simple quadratically probed
391 // hash table for determining if a register is a subregister
392 // of another register.
393 unsigned NumSubRegs = 0;
394 std::map<Record*, unsigned> RegNo;
395 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
396 RegNo[Regs[i].TheDef] = i;
397 NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
400 unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
401 unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
402 std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
404 unsigned hashMisses = 0;
406 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
407 Record* R = Regs[i].TheDef;
408 for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
409 E = RegisterSubRegs[R].end(); I != E; ++I) {
411 // We have to increase the indices of both registers by one when
412 // computing the hash because, in the generated code, there
413 // will be an extra empty slot at register 0.
414 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
415 unsigned ProbeAmt = 2;
416 while (SubregHashTable[index*2] != ~0U &&
417 SubregHashTable[index*2+1] != ~0U) {
418 index = (index + ProbeAmt) & (SubregHashTableSize-1);
424 SubregHashTable[index*2] = i;
425 SubregHashTable[index*2+1] = RegNo[RJ];
429 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
431 if (SubregHashTableSize) {
432 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
434 OS << " const unsigned SubregHashTable[] = { ";
435 for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
437 // Insert spaces for nice formatting.
440 if (SubregHashTable[2*i] != ~0U) {
441 OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
442 << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
444 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
448 unsigned Idx = SubregHashTableSize*2-2;
449 if (SubregHashTable[Idx] != ~0U) {
451 << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
452 << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
454 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
457 OS << " const unsigned SubregHashTableSize = "
458 << SubregHashTableSize << ";\n";
460 OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
461 << " const unsigned SubregHashTableSize = 1;\n";
464 delete [] SubregHashTable;
467 // Print the SuperregHashTable, a simple quadratically probed
468 // hash table for determining if a register is a super-register
469 // of another register.
470 unsigned NumSupRegs = 0;
472 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
473 RegNo[Regs[i].TheDef] = i;
474 NumSupRegs += RegisterSuperRegs[Regs[i].TheDef].size();
477 unsigned SuperregHashTableSize = 2 * NextPowerOf2(2 * NumSupRegs);
478 unsigned* SuperregHashTable = new unsigned[2 * SuperregHashTableSize];
479 std::fill(SuperregHashTable, SuperregHashTable + 2 * SuperregHashTableSize, ~0U);
483 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
484 Record* R = Regs[i].TheDef;
485 for (std::set<Record*>::iterator I = RegisterSuperRegs[R].begin(),
486 E = RegisterSuperRegs[R].end(); I != E; ++I) {
488 // We have to increase the indices of both registers by one when
489 // computing the hash because, in the generated code, there
490 // will be an extra empty slot at register 0.
491 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SuperregHashTableSize-1);
492 unsigned ProbeAmt = 2;
493 while (SuperregHashTable[index*2] != ~0U &&
494 SuperregHashTable[index*2+1] != ~0U) {
495 index = (index + ProbeAmt) & (SuperregHashTableSize-1);
501 SuperregHashTable[index*2] = i;
502 SuperregHashTable[index*2+1] = RegNo[RJ];
506 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
508 if (SuperregHashTableSize) {
509 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
511 OS << " const unsigned SuperregHashTable[] = { ";
512 for (unsigned i = 0; i < SuperregHashTableSize - 1; ++i) {
514 // Insert spaces for nice formatting.
517 if (SuperregHashTable[2*i] != ~0U) {
518 OS << getQualifiedName(Regs[SuperregHashTable[2*i]].TheDef) << ", "
519 << getQualifiedName(Regs[SuperregHashTable[2*i+1]].TheDef) << ", \n";
521 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
525 unsigned Idx = SuperregHashTableSize*2-2;
526 if (SuperregHashTable[Idx] != ~0U) {
528 << getQualifiedName(Regs[SuperregHashTable[Idx]].TheDef) << ", "
529 << getQualifiedName(Regs[SuperregHashTable[Idx+1]].TheDef) << " };\n";
531 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
534 OS << " const unsigned SuperregHashTableSize = "
535 << SuperregHashTableSize << ";\n";
537 OS << " const unsigned SuperregHashTable[] = { ~0U, ~0U };\n"
538 << " const unsigned SuperregHashTableSize = 1;\n";
541 delete [] SuperregHashTable;
544 // Print the AliasHashTable, a simple quadratically probed
545 // hash table for determining if a register aliases another register.
546 unsigned NumAliases = 0;
548 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
549 RegNo[Regs[i].TheDef] = i;
550 NumAliases += RegisterAliases[Regs[i].TheDef].size();
553 unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
554 unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
555 std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
559 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
560 Record* R = Regs[i].TheDef;
561 for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
562 E = RegisterAliases[R].end(); I != E; ++I) {
564 // We have to increase the indices of both registers by one when
565 // computing the hash because, in the generated code, there
566 // will be an extra empty slot at register 0.
567 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
568 unsigned ProbeAmt = 2;
569 while (AliasesHashTable[index*2] != ~0U &&
570 AliasesHashTable[index*2+1] != ~0U) {
571 index = (index + ProbeAmt) & (AliasesHashTableSize-1);
577 AliasesHashTable[index*2] = i;
578 AliasesHashTable[index*2+1] = RegNo[RJ];
582 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
584 if (AliasesHashTableSize) {
585 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
587 OS << " const unsigned AliasesHashTable[] = { ";
588 for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
590 // Insert spaces for nice formatting.
593 if (AliasesHashTable[2*i] != ~0U) {
594 OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
595 << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
597 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
601 unsigned Idx = AliasesHashTableSize*2-2;
602 if (AliasesHashTable[Idx] != ~0U) {
604 << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
605 << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
607 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
610 OS << " const unsigned AliasesHashTableSize = "
611 << AliasesHashTableSize << ";\n";
613 OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
614 << " const unsigned AliasesHashTableSize = 1;\n";
617 delete [] AliasesHashTable;
619 if (!RegisterAliases.empty())
620 OS << "\n\n // Register Alias Sets...\n";
622 // Emit the empty alias list
623 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
624 // Loop over all of the registers which have aliases, emitting the alias list
626 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
627 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
628 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
629 for (std::set<Record*>::iterator ASI = I->second.begin(),
630 E = I->second.end(); ASI != E; ++ASI)
631 OS << getQualifiedName(*ASI) << ", ";
635 if (!RegisterSubRegs.empty())
636 OS << "\n\n // Register Sub-registers Sets...\n";
638 // Emit the empty sub-registers list
639 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
640 // Loop over all of the registers which have sub-registers, emitting the
641 // sub-registers list to memory.
642 for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
643 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
644 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
645 std::vector<Record*> SubRegsVector;
646 for (std::set<Record*>::iterator ASI = I->second.begin(),
647 E = I->second.end(); ASI != E; ++ASI)
648 SubRegsVector.push_back(*ASI);
649 RegisterSorter RS(RegisterSubRegs);
650 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
651 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
652 OS << getQualifiedName(SubRegsVector[i]) << ", ";
656 if (!RegisterSuperRegs.empty())
657 OS << "\n\n // Register Super-registers Sets...\n";
659 // Emit the empty super-registers list
660 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
661 // Loop over all of the registers which have super-registers, emitting the
662 // super-registers list to memory.
663 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
664 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
665 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
667 std::vector<Record*> SuperRegsVector;
668 for (std::set<Record*>::iterator ASI = I->second.begin(),
669 E = I->second.end(); ASI != E; ++ASI)
670 SuperRegsVector.push_back(*ASI);
671 RegisterSorter RS(RegisterSubRegs);
672 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
673 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
674 OS << getQualifiedName(SuperRegsVector[i]) << ", ";
678 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
679 OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n";
681 // Now that register alias and sub-registers sets have been emitted, emit the
682 // register descriptors now.
683 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
684 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
685 const CodeGenRegister &Reg = Registers[i];
687 if (!Reg.TheDef->getValueAsString("AsmName").empty())
688 OS << Reg.TheDef->getValueAsString("AsmName");
692 OS << Reg.getName() << "\",\t";
693 if (RegisterAliases.count(Reg.TheDef))
694 OS << Reg.getName() << "_AliasSet,\t";
696 OS << "Empty_AliasSet,\t";
697 if (RegisterSubRegs.count(Reg.TheDef))
698 OS << Reg.getName() << "_SubRegsSet,\t";
700 OS << "Empty_SubRegsSet,\t";
701 if (RegisterSuperRegs.count(Reg.TheDef))
702 OS << Reg.getName() << "_SuperRegsSet },\n";
704 OS << "Empty_SuperRegsSet },\n";
706 OS << " };\n"; // End of register descriptors...
707 OS << "}\n\n"; // End of anonymous namespace...
709 std::string ClassName = Target.getName() + "GenRegisterInfo";
711 // Calculate the mapping of subregister+index pairs to physical registers.
712 std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
713 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
714 int subRegIndex = SubRegs[i]->getValueAsInt("index");
715 std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
716 std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
718 if (From.size() != To.size()) {
719 cerr << "Error: register list and sub-register list not of equal length"
720 << " in SubRegSet\n";
724 // For each entry in from/to vectors, insert the to register at index
725 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
726 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
729 // Emit the subregister + index mapping function based on the information
731 OS << "unsigned " << ClassName
732 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
733 << " switch (RegNo) {\n"
734 << " default:\n return 0;\n";
735 for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
736 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
737 OS << " case " << getQualifiedName(I->first) << ":\n";
738 OS << " switch (Index) {\n";
739 OS << " default: return 0;\n";
740 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
741 OS << " case " << (I->second)[i].first << ": return "
742 << getQualifiedName((I->second)[i].second) << ";\n";
743 OS << " };\n" << " break;\n";
746 OS << " return 0;\n";
749 // Emit the constructor of the class...
750 OS << ClassName << "::" << ClassName
751 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
752 << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
753 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
754 << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
755 << " SubregHashTable, SubregHashTableSize,\n"
756 << " SuperregHashTable, SuperregHashTableSize,\n"
757 << " AliasesHashTable, AliasesHashTableSize) {\n"
760 // Collect all information about dwarf register numbers
762 // First, just pull all provided information to the map
763 unsigned maxLength = 0;
764 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
765 Record *Reg = Registers[i].TheDef;
766 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
767 maxLength = std::max((size_t)maxLength, RegNums.size());
768 if (DwarfRegNums.count(Reg))
769 cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
770 << "specified multiple times\n";
771 DwarfRegNums[Reg] = RegNums;
774 // Now we know maximal length of number list. Append -1's, where needed
775 for (DwarfRegNumsMapTy::iterator
776 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
777 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
778 I->second.push_back(-1);
780 // Emit information about the dwarf register numbers.
781 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
782 << "unsigned Flavour) const {\n"
783 << " switch (Flavour) {\n"
785 << " assert(0 && \"Unknown DWARF flavour\");\n"
788 for (unsigned i = 0, e = maxLength; i != e; ++i) {
789 OS << " case " << i << ":\n"
790 << " switch (RegNum) {\n"
792 << " assert(0 && \"Invalid RegNum\");\n"
795 // Sort by name to get a stable order.
798 for (DwarfRegNumsMapTy::iterator
799 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
800 int RegNo = I->second[i];
802 OS << " case " << getQualifiedName(I->first) << ":\n"
803 << " return " << RegNo << ";\n";
805 OS << " case " << getQualifiedName(I->first) << ":\n"
806 << " assert(0 && \"Invalid register for this mode\");\n"
814 OS << "} // End llvm namespace \n";