1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Format.h"
27 // runEnums - Print out enum values for all of the registers.
28 void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
29 CodeGenTarget Target(Records);
30 CodeGenRegBank &Bank = Target.getRegBank();
31 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
33 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
35 EmitSourceFileHeader("Target Register Enum Values", OS);
36 OS << "namespace llvm {\n\n";
38 if (!Namespace.empty())
39 OS << "namespace " << Namespace << " {\n";
40 OS << "enum {\n NoRegister,\n";
42 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
43 OS << " " << Registers[i]->getName() << " = " <<
44 Registers[i]->EnumValue << ",\n";
45 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
46 "Register enum value mismatch!");
47 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
49 if (!Namespace.empty())
52 const std::vector<Record*> &SubRegIndices = Bank.getSubRegIndices();
53 if (!SubRegIndices.empty()) {
54 OS << "\n// Subregister indices\n";
55 Namespace = SubRegIndices[0]->getValueAsString("Namespace");
56 if (!Namespace.empty())
57 OS << "namespace " << Namespace << " {\n";
58 OS << "enum {\n NoSubRegister,\n";
59 for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
60 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
61 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
63 if (!Namespace.empty())
66 OS << "} // End llvm namespace \n";
69 void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
70 EmitSourceFileHeader("Register Information Header Fragment", OS);
71 CodeGenTarget Target(Records);
72 const std::string &TargetName = Target.getName();
73 std::string ClassName = TargetName + "GenRegisterInfo";
75 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
76 OS << "#include <string>\n\n";
78 OS << "namespace llvm {\n\n";
80 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
81 << " explicit " << ClassName
82 << "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
83 << "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
84 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
85 << "unsigned Flavour) const;\n"
86 << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
87 << "unsigned Flavour) const;\n"
88 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
89 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
90 << " { return false; }\n"
91 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
92 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
93 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
96 const std::vector<CodeGenRegisterClass> &RegisterClasses =
97 Target.getRegisterClasses();
99 if (!RegisterClasses.empty()) {
100 OS << "namespace " << RegisterClasses[0].Namespace
101 << " { // Register classes\n";
104 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
106 OS << " " << RegisterClasses[i].getName() << "RegClassID";
111 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
112 const CodeGenRegisterClass &RC = RegisterClasses[i];
113 const std::string &Name = RC.getName();
115 // Output the register class definition.
116 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
117 << " " << Name << "Class();\n";
118 if (!RC.AltOrderSelect.empty())
119 OS << " ArrayRef<unsigned> "
120 "getRawAllocationOrder(const MachineFunction&) const;\n";
123 // Output the extern for the instance.
124 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
125 // Output the extern for the pointer to the instance (should remove).
126 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
127 << Name << "RegClass;\n";
129 OS << "} // end of namespace " << TargetName << "\n\n";
131 OS << "} // End llvm namespace \n";
134 typedef std::pair<unsigned, unsigned> UUPair;
135 typedef std::vector<UUPair> UUVector;
138 // RegisterInfoEmitter::run - Main register file description emitter.
140 void RegisterInfoEmitter::run(raw_ostream &OS) {
141 CodeGenTarget Target(Records);
142 CodeGenRegBank &RegBank = Target.getRegBank();
143 RegBank.computeDerivedInfo();
145 EmitSourceFileHeader("Register Information Source Fragment", OS);
147 OS << "namespace llvm {\n\n";
149 // Start out by emitting each of the register classes.
150 const std::vector<CodeGenRegisterClass> &RegisterClasses =
151 Target.getRegisterClasses();
153 // Collect all registers belonging to any allocatable class.
154 std::set<Record*> AllocatableRegs;
156 // Loop over all of the register classes... emitting each one.
157 OS << "namespace { // Register classes...\n";
159 // Emit the register enum value arrays for each RegisterClass
160 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
161 const CodeGenRegisterClass &RC = RegisterClasses[rc];
162 ArrayRef<Record*> Order = RC.getOrder();
164 // Collect allocatable registers.
166 AllocatableRegs.insert(Order.begin(), Order.end());
168 // Give the register class a legal C name if it's anonymous.
169 std::string Name = RC.getName();
171 // Emit the register list now.
172 OS << " // " << Name << " Register Class...\n"
173 << " static const unsigned " << Name
175 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
176 Record *Reg = Order[i];
177 OS << getQualifiedName(Reg) << ", ";
182 // Emit the ValueType arrays for each RegisterClass
183 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
184 const CodeGenRegisterClass &RC = RegisterClasses[rc];
186 // Give the register class a legal C name if it's anonymous.
187 std::string Name = RC.getName() + "VTs";
189 // Emit the register list now.
191 << " Register Class Value Types...\n"
192 << " static const EVT " << Name
194 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
195 OS << getEnumName(RC.VTs[i]) << ", ";
196 OS << "MVT::Other\n };\n\n";
198 OS << "} // end anonymous namespace\n\n";
200 // Now that all of the structs have been emitted, emit the instances.
201 if (!RegisterClasses.empty()) {
202 OS << "namespace " << RegisterClasses[0].Namespace
203 << " { // Register class instances\n";
204 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
205 OS << " " << RegisterClasses[i].getName() << "Class\t"
206 << RegisterClasses[i].getName() << "RegClass;\n";
208 std::map<unsigned, std::set<unsigned> > SuperClassMap;
209 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
212 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
214 if (NumSubRegIndices) {
215 // Emit the sub-register classes for each RegisterClass
216 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
217 const CodeGenRegisterClass &RC = RegisterClasses[rc];
218 std::vector<Record*> SRC(NumSubRegIndices);
219 for (DenseMap<Record*,Record*>::const_iterator
220 i = RC.SubRegClasses.begin(),
221 e = RC.SubRegClasses.end(); i != e; ++i) {
223 unsigned idx = RegBank.getSubRegIndexNo(i->first);
224 SRC.at(idx-1) = i->second;
226 // Find the register class number of i->second for SuperRegClassMap.
227 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
228 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
229 if (RC2.TheDef == i->second) {
230 SuperRegClassMap[rc2].insert(rc);
236 // Give the register class a legal C name if it's anonymous.
237 std::string Name = RC.TheDef->getName();
240 << " Sub-register Classes...\n"
241 << " static const TargetRegisterClass* const "
242 << Name << "SubRegClasses[] = {\n ";
244 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
248 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
255 // Emit the super-register classes for each RegisterClass
256 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
257 const CodeGenRegisterClass &RC = RegisterClasses[rc];
259 // Give the register class a legal C name if it's anonymous.
260 std::string Name = RC.TheDef->getName();
263 << " Super-register Classes...\n"
264 << " static const TargetRegisterClass* const "
265 << Name << "SuperRegClasses[] = {\n ";
268 std::map<unsigned, std::set<unsigned> >::iterator I =
269 SuperRegClassMap.find(rc);
270 if (I != SuperRegClassMap.end()) {
271 for (std::set<unsigned>::iterator II = I->second.begin(),
272 EE = I->second.end(); II != EE; ++II) {
273 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
276 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
281 OS << (!Empty ? ", " : "") << "NULL";
285 // No subregindices in this target
286 OS << " static const TargetRegisterClass* const "
287 << "NullRegClasses[] = { NULL };\n\n";
290 // Emit the sub-classes array for each RegisterClass
291 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
292 const CodeGenRegisterClass &RC = RegisterClasses[rc];
294 // Give the register class a legal C name if it's anonymous.
295 std::string Name = RC.TheDef->getName();
298 << " Register Class sub-classes...\n"
299 << " static const TargetRegisterClass* const "
300 << Name << "Subclasses[] = {\n ";
303 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
304 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
306 // Sub-classes are used to determine if a virtual register can be used
307 // as an instruction operand, or if it must be copied first.
308 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
310 if (!Empty) OS << ", ";
311 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
314 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
315 SuperClassMap.find(rc2);
316 if (SCMI == SuperClassMap.end()) {
317 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
318 SCMI = SuperClassMap.find(rc2);
320 SCMI->second.insert(rc);
323 OS << (!Empty ? ", " : "") << "NULL";
327 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
328 const CodeGenRegisterClass &RC = RegisterClasses[rc];
330 // Give the register class a legal C name if it's anonymous.
331 std::string Name = RC.TheDef->getName();
334 << " Register Class super-classes...\n"
335 << " static const TargetRegisterClass* const "
336 << Name << "Superclasses[] = {\n ";
339 std::map<unsigned, std::set<unsigned> >::iterator I =
340 SuperClassMap.find(rc);
341 if (I != SuperClassMap.end()) {
342 for (std::set<unsigned>::iterator II = I->second.begin(),
343 EE = I->second.end(); II != EE; ++II) {
344 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
345 if (!Empty) OS << ", ";
346 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
351 OS << (!Empty ? ", " : "") << "NULL";
356 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
357 const CodeGenRegisterClass &RC = RegisterClasses[i];
358 OS << RC.getName() << "Class::" << RC.getName()
359 << "Class() : TargetRegisterClass("
360 << RC.getName() + "RegClassID" << ", "
361 << '\"' << RC.getName() << "\", "
362 << RC.getName() + "VTs" << ", "
363 << RC.getName() + "Subclasses" << ", "
364 << RC.getName() + "Superclasses" << ", "
365 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
367 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
369 << RC.SpillSize/8 << ", "
370 << RC.SpillAlignment/8 << ", "
371 << RC.CopyCost << ", "
372 << RC.Allocatable << ", "
373 << RC.getName() << ", " << RC.getName() << " + "
374 << RC.getOrder().size()
376 if (!RC.AltOrderSelect.empty()) {
377 OS << "\nstatic inline unsigned " << RC.getName()
378 << "AltOrderSelect(const MachineFunction &MF) {"
379 << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
380 << RC.getName() << "Class::"
381 << "getRawAllocationOrder(const MachineFunction &MF) const {\n";
382 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
383 ArrayRef<Record*> Elems = RC.getOrder(oi);
384 OS << " static const unsigned AltOrder" << oi << "[] = {";
385 for (unsigned elem = 0; elem != Elems.size(); ++elem)
386 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
389 OS << " static const ArrayRef<unsigned> Order[] = {\n"
390 << " ArrayRef<unsigned>(" << RC.getName();
391 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
392 OS << "),\n ArrayRef<unsigned>(AltOrder" << oi;
393 OS << ")\n };\n const unsigned Select = " << RC.getName()
394 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
395 << ");\n return Order[Select];\n}\n";
402 OS << "\nnamespace {\n";
403 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
404 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
405 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
409 // Emit extra information about registers.
410 OS << "\n static const TargetRegisterInfoDesc "
411 << Target.getName() << "RegInfoDesc[] = "
412 << "{ // Extra Descriptors\n";
413 OS << " { 0, 0 },\n";
415 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
416 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
417 const CodeGenRegister &Reg = *Regs[i];
419 OS << Reg.CostPerUse << ", "
420 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
422 OS << " };\n"; // End of register descriptors...
425 // Calculate the mapping of subregister+index pairs to physical registers.
426 // This will also create further anonymous indexes.
427 unsigned NamedIndices = RegBank.getNumNamedIndices();
429 // Emit SubRegIndex names, skipping 0
430 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
431 OS << "\n const char *const SubRegIndexTable[] = { \"";
432 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
433 OS << SubRegIndices[i]->getName();
439 // Emit names of the anonymus subreg indexes.
440 if (SubRegIndices.size() > NamedIndices) {
442 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
443 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
449 OS << "}\n\n"; // End of anonymous namespace...
451 std::string ClassName = Target.getName() + "GenRegisterInfo";
453 // Emit the subregister + index mapping function based on the information
455 OS << "unsigned " << ClassName
456 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
457 << " switch (RegNo) {\n"
458 << " default:\n return 0;\n";
459 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
460 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
463 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
464 OS << " switch (Index) {\n";
465 OS << " default: return 0;\n";
466 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
467 ie = SRM.end(); ii != ie; ++ii)
468 OS << " case " << getQualifiedName(ii->first)
469 << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
470 OS << " };\n" << " break;\n";
473 OS << " return 0;\n";
476 OS << "unsigned " << ClassName
477 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
478 << " switch (RegNo) {\n"
479 << " default:\n return 0;\n";
480 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
481 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
484 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
485 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
486 ie = SRM.end(); ii != ie; ++ii)
487 OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
488 << ") return " << getQualifiedName(ii->first) << ";\n";
489 OS << " return 0;\n";
492 OS << " return 0;\n";
495 // Emit composeSubRegIndices
496 OS << "unsigned " << ClassName
497 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
498 << " switch (IdxA) {\n"
499 << " default:\n return IdxB;\n";
500 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
502 for (unsigned j = 0; j != e; ++j) {
503 if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
506 OS << " case " << getQualifiedName(SubRegIndices[i])
507 << ": switch(IdxB) {\n default: return IdxB;\n";
510 OS << " case " << getQualifiedName(SubRegIndices[j])
511 << ": return " << getQualifiedName(Comp) << ";\n";
519 // Emit the constructor of the class...
520 OS << ClassName << "::" << ClassName
521 << "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
522 << "int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
523 << " : TargetRegisterInfo(ID"
524 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
525 << " SubRegIndexTable,\n"
526 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {\n"
527 << " InitMCRegisterInfo(D, " << Regs.size()+1 << ");\n"
530 // Collect all information about dwarf register numbers
531 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
532 DwarfRegNumsMapTy DwarfRegNums;
534 // First, just pull all provided information to the map
535 unsigned maxLength = 0;
536 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
537 Record *Reg = Regs[i]->TheDef;
538 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
539 maxLength = std::max((size_t)maxLength, RegNums.size());
540 if (DwarfRegNums.count(Reg))
541 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
542 << "specified multiple times\n";
543 DwarfRegNums[Reg] = RegNums;
546 // Now we know maximal length of number list. Append -1's, where needed
547 for (DwarfRegNumsMapTy::iterator
548 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
549 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
550 I->second.push_back(-1);
552 // Emit reverse information about the dwarf register numbers.
553 OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, "
554 << "unsigned Flavour) const {\n"
555 << " switch (Flavour) {\n"
557 << " assert(0 && \"Unknown DWARF flavour\");\n"
560 for (unsigned i = 0, e = maxLength; i != e; ++i) {
561 OS << " case " << i << ":\n"
562 << " switch (DwarfRegNum) {\n"
564 << " assert(0 && \"Invalid DwarfRegNum\");\n"
567 for (DwarfRegNumsMapTy::iterator
568 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
569 int DwarfRegNo = I->second[i];
571 OS << " case " << DwarfRegNo << ":\n"
572 << " return " << getQualifiedName(I->first) << ";\n";
579 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
580 Record *Reg = Regs[i]->TheDef;
581 const RecordVal *V = Reg->getValue("DwarfAlias");
582 if (!V || !V->getValue())
585 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
586 Record *Alias = DI->getDef();
587 DwarfRegNums[Reg] = DwarfRegNums[Alias];
590 // Emit information about the dwarf register numbers.
591 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
592 << "unsigned Flavour) const {\n"
593 << " switch (Flavour) {\n"
595 << " assert(0 && \"Unknown DWARF flavour\");\n"
598 for (unsigned i = 0, e = maxLength; i != e; ++i) {
599 OS << " case " << i << ":\n"
600 << " switch (RegNum) {\n"
602 << " assert(0 && \"Invalid RegNum\");\n"
605 // Sort by name to get a stable order.
608 for (DwarfRegNumsMapTy::iterator
609 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
610 int RegNo = I->second[i];
611 OS << " case " << getQualifiedName(I->first) << ":\n"
612 << " return " << RegNo << ";\n";
619 OS << "} // End llvm namespace \n";
622 void RegisterInfoEmitter::runDesc(raw_ostream &OS) {
623 CodeGenTarget Target(Records);
624 CodeGenRegBank &RegBank = Target.getRegBank();
625 RegBank.computeDerivedInfo();
626 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
627 RegBank.computeOverlaps(Overlaps);
629 OS << "namespace llvm {\n\n";
631 const std::string &TargetName = Target.getName();
632 std::string ClassName = TargetName + "GenMCRegisterInfo";
633 OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
634 << " explicit " << ClassName << "(const TargetRegisterDesc *D);\n";
637 OS << "\nnamespace {\n";
639 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
641 // Emit an overlap list for all registers.
642 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
643 const CodeGenRegister *Reg = Regs[i];
644 const CodeGenRegister::Set &O = Overlaps[Reg];
645 // Move Reg to the front so TRI::getAliasSet can share the list.
646 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
647 << getQualifiedName(Reg->TheDef) << ", ";
648 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
651 OS << getQualifiedName((*I)->TheDef) << ", ";
655 // Emit the empty sub-registers list
656 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
657 // Loop over all of the registers which have sub-registers, emitting the
658 // sub-registers list to memory.
659 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
660 const CodeGenRegister &Reg = *Regs[i];
661 if (Reg.getSubRegs().empty())
663 // getSubRegs() orders by SubRegIndex. We want a topological order.
664 SetVector<CodeGenRegister*> SR;
665 Reg.addSubRegsPreOrder(SR);
666 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
667 for (unsigned j = 0, je = SR.size(); j != je; ++j)
668 OS << getQualifiedName(SR[j]->TheDef) << ", ";
672 // Emit the empty super-registers list
673 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
674 // Loop over all of the registers which have super-registers, emitting the
675 // super-registers list to memory.
676 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
677 const CodeGenRegister &Reg = *Regs[i];
678 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
681 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
682 for (unsigned j = 0, je = SR.size(); j != je; ++j)
683 OS << getQualifiedName(SR[j]->TheDef) << ", ";
687 OS << "\n const TargetRegisterDesc " << TargetName
688 << "RegDesc[] = { // Descriptors\n";
689 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
691 // Now that register alias and sub-registers sets have been emitted, emit the
692 // register descriptors now.
693 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
694 const CodeGenRegister &Reg = *Regs[i];
696 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
697 if (!Reg.getSubRegs().empty())
698 OS << Reg.getName() << "_SubRegsSet,\t";
700 OS << "Empty_SubRegsSet,\t";
701 if (!Reg.getSuperRegs().empty())
702 OS << Reg.getName() << "_SuperRegsSet";
704 OS << "Empty_SuperRegsSet";
707 OS << " };\n"; // End of register descriptors...
709 OS << "}\n\n"; // End of anonymous namespace...
711 // MCRegisterInfo initialization routine.
712 OS << "static inline void Init" << TargetName
713 << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
714 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
715 << Regs.size()+1 << ");\n}\n\n";
717 OS << "} // End llvm namespace \n";